CN104734677A - Single stage comparator - Google Patents
Single stage comparator Download PDFInfo
- Publication number
- CN104734677A CN104734677A CN201510176346.1A CN201510176346A CN104734677A CN 104734677 A CN104734677 A CN 104734677A CN 201510176346 A CN201510176346 A CN 201510176346A CN 104734677 A CN104734677 A CN 104734677A
- Authority
- CN
- China
- Prior art keywords
- switch
- voltage
- input
- control signal
- stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Manipulation Of Pulses (AREA)
- Measurement Of Current Or Voltage (AREA)
Abstract
The invention provides a single stage comparator comprising a first voltage terminal, a second voltage terminal, a first input terminal, a second input terminal, an output terminal and a single stage comparison unit. The single stage comparison unit comprises a first switch, a second switch, a third switch, a first current source, a second current source, an inverter, a capacitor and an MOS tube. The first current source is connected to the position between the first voltage terminal and the drain electrode of the MOS tube; the capacitor is connected to the position between the source electrode of the MOS tube and the second voltage terminal; the first switch is connected to the position between the second input terminal and the gate electrode of the MOS tube; the second switch is connected to the position between the first input terminal and the gate electrode of the MOS tube; the second current source and the third switch are connected to the position between the source electrode of the MOS tube and a second power supply terminal sequentially. The input terminal of the inverter is connected to a connection node between the MOS tube and the first current source, and the output terminal of the inverter is connected to the output terminal of a comparator body. Compared with the prior art, the single stage comparator has the advantages that the influence on the comparator overturning threshold by input errors resulted from device mismatch can be reduced.
Description
[technical field]
The present invention relates to technical field of circuit design, particularly a kind of single-stage comparator.
[background technology]
The amplifying stage of traditional comparator is generally made up of two-layer configuration.Please refer to shown in Fig. 1, it is the circuit diagram of traditional a kind of comparator.Comparator in Fig. 1 comprises positive input INP, negative input INM, output OUT, first order amplifying stage 110 and second level amplifying stage 120.Wherein, first order amplifying stage 110 comprises current source I1, PMOS transistor MP1 and MP2, nmos pass transistor MN1 and MN2; Second level amplifying stage 120 comprises current source I2, nmos pass transistor MN3, inverter INV1 and INV2.
Comparator in Fig. 1 is when voltage higher than negative input INM of the voltage of positive input INP, and output OUT becomes high level; When voltage lower than negative input INM of the voltage of positive input INP, output OUT becomes low level.Below the specific works process of comparator shown in Fig. 1 is specifically introduced.
When voltage lower than negative input INM of the voltage of positive input INP, the electric current of PMOS transistor MP2 will be greater than the electric current (namely PMOS transistor MP2 will get more electric current from current source I1) of PMOS transistor MP1, and nmos pass transistor MN2 and MN1 forms current mirror, then the electric current of nmos pass transistor MN2 equals the electric current of nmos pass transistor MN1, also equals the electric current of PMOS transistor MP1.Like this, the electric current of PMOS transistor MP2 is greater than the electric current of nmos pass transistor MN2, and the grid voltage of NOS transistor MN3 uprises, and causes the drain voltage step-down of nmos pass transistor MN3, thus makes output OUT become low level.
When input voltage higher than negative input INM of the voltage of positive input INP, the electric current of PMOS transistor MP2 will be less than the electric current (namely PMOS transistor MP1 will get more electric current from current source I1) of MP1, and nmos pass transistor MN2 and MN1 forms current mirror, then the electric current of nmos pass transistor MN2 equals the electric current of nmos pass transistor MN1, also equals the electric current of PMOS transistor MP1.Like this, the electric current of PMOS transistor MP2 is less than the electric current of nmos pass transistor MN2, and the grid voltage step-down of nmos pass transistor MN3 causes the drain voltage of nmos pass transistor MN3 to uprise, thus makes output OUT become high level.
There are two shortcomings in the comparator in Fig. 1:
The first, there is mismatch condition when actual production in PMOS transistor MP1 and MP2, namely both characteristics there are differences, such as, certain deviation is there is between both threshold voltages, and random distribution, the comparator input deviation (input offset) of equivalence can be caused like this, thus cause actual turn threshold to there is deviation.Such as, positive input INP meets input signal VIN, negative input INM meets a fixed reference potential VREF, when comparator exists input deviation, the turn threshold of comparator becomes VIN=VREF+Vos, wherein, input signal VIN is the input voltage of positive input terminal VIP, VREF is the input voltage of negative input end INM, and Vos is the input deviation of equivalence, and desirable comparator turn threshold should be VIN=VREF.In addition, the mismatch between nmos pass transistor MN1 and MN2 also can have shared to above-mentioned input deviation Vos, makes the excursion of input deviation Vos larger.The input deviation Vos of comparator shown in usual Fig. 1 is 20mV to the maximum.
The second, because comparator is two-layer configuration, every grade all exists parasitic capacitance, can contribute the time of delay of output signal, causes the output delay outputing signal OUT.General progression is more, and time delay is larger.
Therefore, be necessary to provide a kind of technical scheme of improvement to solve the problems referred to above.
[summary of the invention]
The object of the present invention is to provide a kind of single-stage comparator, its input deviation that not only can reduce to cause due to device mismatch on the impact of comparator turn threshold, but also can reduce the time of delay of comparator output signal.
In order to solve the problem, the invention provides a kind of single-stage comparator, it comprises the first voltage end, the second voltage end, first input end, the second input, output and single-stage comparing unit.Described single-stage comparing unit is for the size of the voltage of the voltage and the second input that compare first input end, and export the level signal representing corresponding comparative result, described single-stage comparing unit comprises the first switch, second switch and the 3rd switch, first current source and the second current source, inverter, electric capacity and metal-oxide-semiconductor.Wherein, first current source is connected between the first voltage end and the drain electrode of metal-oxide-semiconductor, electric capacity is connected between the source electrode of metal-oxide-semiconductor and the second voltage end, first switch is connected between the second input and the grid of metal-oxide-semiconductor, second switch is connected between first input end and the grid of metal-oxide-semiconductor, and the second current source and the 3rd switch are connected between the source electrode of metal-oxide-semiconductor and second source end successively.The input of inverter is connected with the connected node between metal-oxide-semiconductor and the first current source, and the output of inverter is connected with the output of single-stage comparator as the output of described single-stage comparing unit.
Further, first switch is all connected with the first control signal with the control end of the 3rd switch, the control end of second switch is connected with the second control signal, when the first control signal controls the first switch and the 3rd switch conduction, second control signal controls second switch and turns off, now the second input is connected directly to the grid of described metal-oxide-semiconductor, described single-stage comparing unit realizes the collection of the voltage of the second input; When the first control signal controls the first switch and the 3rd switch OFF, second control signal controls second switch conducting, now first input end is connected directly to the grid of described metal-oxide-semiconductor, described single-stage comparing unit realizes comparing of the voltage of first input end and the voltage of the second input.By arranging the first control signal and the second control signal, make the grid being connected to described metal-oxide-semiconductor that the second input and first input end replace successively.
Further, described first control signal and the second control signal are clock signal, there is certain Dead Time between the first control signal and the second control signal, to avoid switch S 1, S2 and S3 conducting simultaneously.
Further, the gate source voltage of the metal-oxide-semiconductor when gate source voltage of metal-oxide-semiconductor during the first switch conduction equals second switch conducting.
Further, the first current source is equal with the second current source, and/or designs larger by the breadth length ratio W/L of metal-oxide-semiconductor.
Further, described first voltage end is power end, and described second voltage end is earth terminal, and described metal-oxide-semiconductor is nmos pass transistor; The positive pole of the first current source is connected with power end, and its negative pole is connected with the drain electrode of nmos pass transistor, and the lining body of nmos pass transistor is connected with earth terminal; The positive pole of the second current source is connected with the source electrode of nmos pass transistor, and its negative pole is connected with a link of the 3rd switch, and another link of the 3rd switch is connected with earth terminal.
Further, described first voltage end is earth terminal, and described second voltage end is power end, and described metal-oxide-semiconductor is PMOS transistor; The negative pole of the first current source is connected with earth terminal, and its positive pole is connected with the drain electrode of PMOS transistor, and the lining body of PMOS transistor is connected with the source electrode of PMOS transistor; The negative pole of the second current source is connected with the source electrode of PMOS transistor, and its positive pole is connected with a link of the 3rd switch, and another link of the 3rd switch is connected with power end.
Further, described single-stage comparator also comprises sampling latch unit, the input of this sampling latch unit is connected with the output of inverter, its output is connected with the output of single-stage comparator, the level signal that described single-stage comparing unit of sampling when described sampling latch unit was used for after the second switch conducting scheduled time exports, its output exports and keeps the level signal that samples.
Further, described employing latch units comprises d type flip flop, the data input pin of this d type flip flop is connected with the output of inverter, its input end of clock is connected with the 3rd control signal, its output is connected with the output OUT of single-stage comparator, and the 3rd control signal triggers the level signal that described d type flip flop sampling single-stage comparing unit exports after the second switch conducting scheduled time.
Compared with prior art, the present invention adopts single-stage comparator configuration, and this single-stage comparator realizes comparing the voltage of positive input and the voltage of negative input by a metal-oxide-semiconductor, thus the input deviation that not only can reduce to cause due to device mismatch is on the impact of comparator turn threshold, but also the time of delay of comparator output signal can be reduced.
[accompanying drawing explanation]
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.Wherein:
Fig. 1 is the circuit diagram of traditional a kind of comparator;
Fig. 2 is the circuit diagram of the present invention's single-stage comparator in one embodiment;
Fig. 3 is control signal CK1, CK2 and the CK3 sequential chart in one embodiment in Fig. 2;
Fig. 4 is the circuit diagram of the present invention's single-stage comparator in another embodiment.
[embodiment]
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Alleged herein " embodiment " or " embodiment " refers to special characteristic, structure or the characteristic that can be contained at least one implementation of the present invention.Different local in this manual " in one embodiment " occurred not all refers to same embodiment, neither be independent or optionally mutually exclusive with other embodiments embodiment.Unless stated otherwise, connection herein, be connected, word that the expression that connects is electrically connected all represents and is directly or indirectly electrical connected.
Comparator in the present invention is single-stage comparator configuration, and this single-stage comparator realizes comparing the voltage of positive input and the voltage of negative input by a metal-oxide-semiconductor, thus the input deviation that not only can reduce to cause due to device mismatch is on the impact of comparator turn threshold, but also the time of delay of comparator output signal can be reduced.
Please refer to shown in Fig. 2, it is the circuit diagram of the present invention's single-stage comparator in one embodiment.This single-stage comparator comprises power end V, earth terminal G, positive input INP (or claiming first input end), negative input INM (or claiming the second input), output OUT and single-stage comparing unit 210.
Described single-stage comparing unit 210 for the voltage swing of the voltage and negative input INM that compare positive input INP, and exports the level signal representing corresponding comparative result.Described single-stage comparing unit 210 comprises the first switch S 1, second switch S2 and the 3rd switch S 3, first current source I1 and the second current source I2, inverter INV1, electric capacity C1 and nmos pass transistor MN1.Wherein, the first current source I1 is connected between the drain electrode of power end V and nmos pass transistor MN1.Be specially, the positive pole of the first current source I1 is connected with power end V, and its negative pole is connected with the drain electrode of nmos pass transistor MN1; Electric capacity C1 is connected between the source electrode of nmos pass transistor and earth terminal G, and the lining body of nmos pass transistor MN1 is connected with earth terminal G; First switch S 1 is connected between the grid of negative input INM and nmos pass transistor MN1, and second switch S2 is connected between the grid of positive input INP and nmos pass transistor MN1; Second current source I2 and the 3rd switch S 3 are connected between the source electrode of nmos pass transistor MN1 and earth terminal G successively, be specially, the positive pole of the second current source I2 is connected with the source electrode of nmos pass transistor MN1, its negative pole is connected with a link of the 3rd switch S 3, and another link of the 3rd switch S 3 is connected with earth terminal G.
The input of described inverter INV1 is connected with the connected node between nmos pass transistor MN1 and the first current source I1, and the output of inverter INV1 is connected with the output OUT of single-stage comparator as the output of described single-stage comparing unit 210.
First switch S 1 is all connected with the first control signal CK1 with the control end of the 3rd switch S 3, and the control end of second switch S2 is connected with the second control signal CK2.When the first control signal CK1 control switch S1 and S3 conducting, second control signal CK2 control switch S2 turns off, now negative input INM is connected directly to the grid of described nmos pass transistor MN1, described single-stage comparing unit 210 realizes the collection of the voltage of negative input; When the first control signal CK1 control switch S1 and S3 turns off, second control signal CK2 control switch S3 conducting, now positive input INP is connected directly to the grid of described nmos pass transistor MN1, described single-stage comparing unit 210 realizes comparing of the voltage of positive input INP and the voltage of negative input INM, by arranging the first control signal CK1 and the second control signal CK2, make the grid being connected to described nmos pass transistor MN1 that negative input INM and positive input INP replaces successively.It should be noted that to there is certain Dead Time between the first control signal CK1 and the second control signal CK2, to avoid switch S 1, S2 and S3 conducting simultaneously.Please refer to shown in Fig. 3, it is control signal CK1, CK2 and the CK3 sequential chart in one embodiment in Fig. 2.In the embodiment shown in fig. 3, control signal CK1, CK2 and CK3 are clock signal, wherein, control switch S 1 and S3 conducting when the first control signal CK1 is high level, for controlling switch S 1 and S3 shutoff during low level; Switch S 2 conducting is controlled when second control signal CK2 is high level, turn off for controlling switch S 2 during low level, the high level of the first control signal CK1 and the second control signal CK mutually not overlapping (namely there is certain Dead Time between control signal CK1 and Ck2).
For the ease of understanding the present invention, specifically introduce the course of work of the single-stage comparing unit 210 in Fig. 2 below in conjunction with Fig. 3.
When the first control signal CK1 be high level, the second control signal CK2 be low level time, switch S 1 and S3 conducting, switch S 2 turn off, the grid voltage GN1 of nmos pass transistor MN1 equals the voltage of negative input INM, now, nmos pass transistor MN1 is operated in common leakage amplifying stage state, and the voltage that the source voltage (it equals the voltage VC1 of electric capacity C1) of nmos pass transistor equals negative input INM deducts the gate source voltage of nmos pass transistor MN1.
When the first control signal CK1 be low level, the second control signal CK2 be high level time, switch S 1 and S3 turn off, switch S 2 conducting time, the grid voltage GN1 of nmos pass transistor MN1 equals the voltage of positive input INP, now, nmos pass transistor MN1 is operated in common source amplifying stage state, if grid voltage GN1 is greater than the voltage VC1 of electric capacity C1 and the gate source voltage sum of nmos pass transistor MN1, then the drain voltage of nmos pass transistor MN1 reduces, and causes inverter INV1 to export high level; If grid voltage GN1 is less than the voltage VC1 of electric capacity C1 and the gate source voltage sum of nmos pass transistor MN1, then the drain voltage of nmos pass transistor MN1 raises, and causes inverter INV1 output low level.
Now the above-mentioned course of work of single-stage comparing unit 210 is further described.
When switch S 1 and S3 conducting, switch S 2 turn off, the voltage VC1=INM-Vgs1 (1) that electric capacity C1 stores, wherein, INM is the voltage of negative input INM, and Vgs1 is the gate source voltage that nmos pass transistor MN1 is operated in common leakage amplifying stage state.
When switch S 1 and S3 turn off, switch S 2 conducting time, relatively be the gate source voltage sum VA of voltage VC1 on the voltage of positive input INP and electric capacity C1 and nmos pass transistor MN1, and VA=VC1+Vgs2 (2), wherein, VC1 is the voltage that electric capacity C1 stores, it is equal with the VC1 in formula (1), and Vgs2 is the gate source voltage that nmos pass transistor MN1 is operated in common source amplifying stage state.Formula (1) is substituted into formula (2) known, VA=INM-Vgs1+Vgs2, due to Vgs1 and the Vgs2 approximately equal of nmos pass transistor MN1, therefore, VA=VM, that is, when switch S 1 and S3 turn off, during switch S 2 conducting, actual specific compared be the size of the voltage of positive input INP and the voltage of negative input INM, namely described single-stage comparing unit 210 exports high level comparison signal when the voltage of positive input INP is greater than the voltage of negative input INM, the output low level comparison signal when the voltage of positive input INP is less than the voltage of negative input INM.
In order to ensure Vgs1 and the Vgs2 approximately equal of nmos pass transistor MN1, need analyze as follows metal-oxide-semiconductor.
According to metal-oxide-semiconductor saturation region current formula:
Solve and can obtain:
Wherein, Vgs is the gate source voltage of metal-oxide-semiconductor, and I is the drain current (it equals source current) of metal-oxide-semiconductor, and μ is mobility, and Cox is unit area grid capacitance,
for the breadth length ratio of metal-oxide-semiconductor, Vth is the threshold voltage of metal-oxide-semiconductor.
Known according to formula (3), nmos pass transistor MN1 is operated in the gate source voltage of common leakage amplifying stage state
wherein, I2 is the current value of the second current source I2 in Fig. 2.
Known according to formula (3), nmos pass transistor MN1 is operated in the gate source voltage of common source amplifying stage state
wherein, I1 is the current value of the first current source I1 in Fig. 2.
Generally
vth is less relatively for item, and especially when the breadth length ratio W/L design of metal-oxide-semiconductor is larger, this is less.In addition, the first current source I1 and the second current source I2 is designed equal, contributes to allowing difference between Vgs1 and Vgs2 less.That is, by the first current source I1 and the second current source I2 is designed equal, and the breadth length ratio W/L of nmos pass transistor MN1 is designed comparatively large, very easily can realize Vgs1 and the Vgs2 approximately equal of nmos pass transistor MN1.
In summary, by design, make the gate source voltage Vgs1 of the nmos pass transistor MN1 in Fig. 2 in common leakage amplifying stage state and the gate source voltage Vgs2 approximately equal in common source amplifying stage state, to make single-stage comparing unit 210 can the voltage of accurate comparison positive input INP and the voltage swing of negative input INM, thus the input deviation making the comparator in the present invention there is not the comparator of the prior art shown in Fig. 1 to cause due to device mismatch, and owing to being that single-stage compares, therefore, comparator in the present invention can also reduce the time of delay outputed signal.
Shown in Fig. 2, single-stage comparator in the present invention also comprises sampling latch unit 220, the input of described sampling latch unit 220 is connected with the output of inverter INV1, its output is connected with the output OUT of single-stage comparator, the level signal that described sampling latch unit 220 exports for described single-stage comparing unit 210 of sampling when the second switch S2 conducting scheduled time (namely described single-stage comparing unit 210 completes and compares), its output exports and keeps the level signal that samples.
In the embodiment shown in Figure 2, the shown latch units 220 that adopts comprises d type flip flop ffdf1, the data input pin d of this d type flip flop ffdf1 is connected with the output of inverter INV1, its reset terminal r is connected with earth terminal G, its input end of clock ck is connected with the 3rd control signal CK3, its output is connected with the output OUT of single-stage comparator, and the 3rd control signal CK3 triggers the level signal of described d type flip flop ffdf1 sampling single-stage comparing unit 210 output afterwards in the second switch S2 conducting scheduled time (i.e. the second control signal CK2 high level scheduled time).Adopt the object of d type flip flop be realize single-stage comparing unit 210 be operated in comparative result correct time read comparative result.When single-stage comparing unit 210 is operated in store status (when CK1 is high level), single-stage comparing unit 210 exports may be incorrect, now can not read comparative result; State (when CK2 is high level) is compared when single-stage comparing unit 210 enters into from store status, certain settling time (or scheduled time) may be needed owing to setting up correct result than single-stage comparing unit 210, when not reaching settling time, comparative result also likely mistake, now also should not read comparative result.In this embodiment, d type flip flop ffdf1 is trailing edge trigger.
Shown in Fig. 3, in a clock cycle, the rising edge of high level one end of the second control signal CK2 is early than the rising edge of high level one end of the 3rd control signal CK3; The trailing edge of the other end of the high level of the 3rd control signal CK3, a little earlier in the trailing edge of the other end of the second control signal CK2 high level, can avoid the comparative result of d type flip flop ffdf1 sample error like this; The rising edge of high level one end of the second control signal CK2 wants long enough to the time (or time delay) of the trailing edge of the high level other end of the 3rd control signal CK3, so that single-stage comparing unit 210 has time enough to export correct comparative result, namely this time delay is greater than the time of delay of single-stage comparing unit 210.In another embodiment, the d type flip flop ffdf1 in Fig. 2 also can be replaced rising edge d type flip flop, the level signal that described single-stage comparing unit 210 exports as long as it can be sampled when described single-stage comparing unit 210 completes and compares.
Please refer to shown in Fig. 4, it is the circuit diagram of the present invention's single-stage comparator in another embodiment, and Fig. 4 is the execution mode adopting PMOS transistor based on principle of the present invention.The difference of Fig. 4 and Fig. 2 is, the nmos pass transistor MN1 in Fig. 2 is replaced with PMOS transistor MP1.
Concrete, the single-stage comparator shown in Fig. 4 comprises power end V, earth terminal G, positive input INP, negative input INM, output OUT, single-stage comparing unit 410 and sampling latch unit 420.
Described single-stage comparing unit 410 comprises the first switch S 1, the 2nd S2 and Three S's 3, the first current source I1 and the first current source I2, inverter INV1, electric capacity C1 and PMOS transistor MP1.Wherein, current source I1 is connected between earth terminal G and the drain electrode of PMOS transistor MP1, is specially, and the negative pole of the first current source I1 is connected with earth terminal G, and its positive pole is connected with the drain electrode of PMOS transistor MP1; Electric capacity C1 is connected between the source electrode of PMOS transistor and power end V, and the lining body of PMOS transistor MP1 is connected with the source electrode of PMOS transistor MP1; First switch S 1 is connected between negative input INM and the grid of PMOS transistor MP1, and second switch S2 is connected between positive input INP and the grid of PMOS transistor MP1; Second current source I2 and the 3rd switch S 3 are connected between the source electrode of PMOS transistor MP1 and power end V successively, be specially, the negative pole of the second current source I2 is connected with the source electrode of PMOS transistor MP1, its positive pole is connected with a link of the 3rd switch S 3, and another link of the 3rd switch S 3 is connected with power end V.The input of described inverter INV1 is connected with the connected node between PMOS transistor MP1 and the first current source I1, and the output of inverter INV1 is as the output of described single-stage comparing unit 410.
When the first control signal CK1 control switch S1 and S3 conducting, second control signal CK2 control switch S2 turns off, now negative input INM is connected directly to the grid of described PMOS transistor MP1, described single-stage comparing unit 410 realizes the collection of the voltage of negative input INM; When the first control signal CK1 control switch S1 and S3 turns off, second control signal CK2 control switch S3 conducting, now positive input INP is connected directly to the grid of described PMOS transistor MP1, described single-stage comparing unit 410 realizes comparing of the voltage of positive input INP and the voltage of negative input INM, by arranging the first control signal CK1 and the second control signal CK2, make the grid being connected to described PMOS transistor MP1 that negative input INM and positive input INP replaces successively.
The input of described sampling latch unit 420 is connected with the output of inverter INV1, its output is connected with the output OUT of single-stage comparator, the level signal that described sampling latch unit 420 exports for described single-stage comparing unit 410 of sampling when described single-stage comparing unit 410 completes and compares, its output exports and keeps the level signal that samples.In the embodiment shown in fig. 4, described sampling latch unit 420 comprises d type flip flop ffdf1, the data input pin d of this trailing edge d type flip flop ffdf1 is connected with the output of inverter INV1, its reset terminal r is connected with earth terminal G (represent and do not reset), its input end of clock ck is connected with the 3rd control signal CK3, its output q is connected with the output OUT of single-stage comparator, and the 3rd control signal CK3 triggers the level signal that described d type flip flop ffdf1 sampling single-stage comparing unit 210 exports when trailing edge.
In one embodiment, the control signal CK1 in Fig. 4, the sequential chart of Ck2 and CK3 are still as shown in Figure 3.
When the first clock signal C K1 is high level, when second clock signal CK2 is low level, switch S 1 and S3 conducting, switch S 2 turns off, the grid voltage GN1 of PMOS transistor MP1 equals the voltage of negative input INM, now, PMOS transistor MP1 is operated in common leakage amplifying stage state, the source voltage VC1=INM+ ∣ Vgsp1 ∣ of PMOS transistor MP1, wherein, VC1 is the voltage of the connected node VC1 between electric capacity C1 and the source electrode of PMOS transistor MP1, INM is the voltage of comparator negative input INM, Vgsp1 is the gate source voltage that PMOS MP1 is operated in common leakage amplifying stage state.
When the first clock signal C K1 is low level, when second clock signal CK2 is high level, switch S 1 and S3 turn off, switch S 2 conducting, the grid voltage GN1 of PMOS transistor MP1 equals the voltage of positive input INP, now, PMOS transistor MP1 is operated in common source amplifying stage state, relatively be the size of INP+|Vgsp2| and VC1 voltage, wherein, INP is the voltage of positive input INP, Vgsp2 is the gate source voltage that PMOS MP1 is operated in common source amplifying stage state, VC1 is the voltage (VC1=INM+ ∣ Vgsp1 ∣) of node VC1, if (INP+|Vgsp2|) > VC1, the drain voltage of PMOS transistor MP1 reduces, inverter INV1 is caused to export high level, after d type flip flop ffdf1 samples, comparator output terminal OUT is high level, if (INP+|Vgsp2|) drain voltage of < VC1, PMOS transistor MP1 raises, cause inverter INV1 output low level, after d type flip flop ffdf1 samples, comparator output terminal OUT is low level.
By the first current source I1 and the second current source I2 is designed equal, and the breadth length ratio W/L of PMOS transistor MP1 is designed comparatively large, can very easily realize Vgsp1 and Vgsp2 equal.Like this, single-stage comparing unit 410 actual specific compared be the size of the voltage of positive input INP and the voltage of negative input INM.
In summary, comparator in the present invention comprises single-stage comparing unit, this single-stage comparing unit realizes comparing the voltage of positive input and the voltage of negative input by a metal-oxide-semiconductor, thus the input deviation making the comparator in the present invention there is not the comparator of the prior art shown in Fig. 1 to cause due to device mismatch, and owing to being that single-stage compares, therefore, the comparator in the present invention can also reduce the time of delay outputed signal.
In the present invention, " connection ", be connected, word that " companys ", the expression such as " connecing " are electrical connected, if no special instructions, then represent direct or indirect electric connection.
It is pointed out that the scope be familiar with person skilled in art and any change that the specific embodiment of the present invention is done all do not departed to claims of the present invention.Correspondingly, the scope of claim of the present invention is also not limited only to previous embodiment.
Claims (9)
1. a single-stage comparator, is characterized in that, it comprises the first voltage end, the second voltage end, first input end, the second input, output and single-stage comparing unit,
Described single-stage comparing unit is for the size of the voltage of the voltage and the second input that compare first input end, and export the level signal representing corresponding comparative result, described single-stage comparing unit comprises the first switch, second switch and the 3rd switch, first current source and the second current source, inverter, electric capacity and metal-oxide-semiconductor
Wherein, first current source is connected between the first voltage end and the drain electrode of metal-oxide-semiconductor, electric capacity is connected between the source electrode of metal-oxide-semiconductor and the second voltage end, first switch is connected between the second input and the grid of metal-oxide-semiconductor, second switch is connected between first input end and the grid of metal-oxide-semiconductor, second current source and the 3rd switch are connected between the source electrode of metal-oxide-semiconductor and second source end successively
The input of inverter is connected with the connected node between metal-oxide-semiconductor and the first current source, and the output of inverter is connected with the output of single-stage comparator as the output of described single-stage comparing unit.
2. single-stage comparator according to claim 1, is characterized in that,
First switch is all connected with the first control signal with the control end of the 3rd switch, the control end of second switch is connected with the second control signal, when the first control signal controls the first switch and the 3rd switch conduction, second control signal controls second switch and turns off, now the second input is connected directly to the grid of described metal-oxide-semiconductor, described single-stage comparing unit realizes the collection of the voltage of the second input; When the first control signal controls the first switch and the 3rd switch OFF, second control signal controls second switch conducting, now first input end is connected directly to the grid of described metal-oxide-semiconductor, described single-stage comparing unit realizes comparing of the voltage of first input end and the voltage of the second input
By arranging the first control signal and the second control signal, make the grid being connected to described metal-oxide-semiconductor that the second input and first input end replace successively.
3. single-stage comparator according to claim 2, it is characterized in that, described first control signal and the second control signal are clock signal, there is certain Dead Time between the first control signal and the second control signal, to avoid switch S 1, S2 and S3 conducting simultaneously.
4. single-stage comparator according to claim 2, is characterized in that,
The gate source voltage of the metal-oxide-semiconductor when gate source voltage of metal-oxide-semiconductor during the first switch conduction equals second switch conducting.
5. single-stage comparator according to claim 4, is characterized in that,
First current source is equal with the second current source, and/or
The breadth length ratio W/L of metal-oxide-semiconductor is designed larger.
6., according to the arbitrary described single-stage comparator of claim 1-5, it is characterized in that,
Described first voltage end is power end, and described second voltage end is earth terminal, and described metal-oxide-semiconductor is nmos pass transistor;
The positive pole of the first current source is connected with power end, and its negative pole is connected with the drain electrode of nmos pass transistor, and the lining body of nmos pass transistor is connected with earth terminal;
The positive pole of the second current source is connected with the source electrode of nmos pass transistor, and its negative pole is connected with a link of the 3rd switch, and another link of the 3rd switch is connected with earth terminal.
7., according to the arbitrary described single-stage comparator of claim 1-5, it is characterized in that,
Described first voltage end is earth terminal, and described second voltage end is power end, and described metal-oxide-semiconductor is PMOS transistor;
The negative pole of the first current source is connected with earth terminal, and its positive pole is connected with the drain electrode of PMOS transistor, and the lining body of PMOS transistor is connected with the source electrode of PMOS transistor;
The negative pole of the second current source is connected with the source electrode of PMOS transistor, and its positive pole is connected with a link of the 3rd switch, and another link of the 3rd switch is connected with power end.
8., according to the arbitrary described single-stage comparator of claim 1-5, it is characterized in that,
It also comprises sampling latch unit, the input of this sampling latch unit is connected with the output of inverter, its output is connected with the output of single-stage comparator, the level signal that described single-stage comparing unit of sampling when described sampling latch unit was used for after the second switch conducting scheduled time exports, its output exports and keeps the level signal that samples.
9. single-stage comparator according to claim 8, is characterized in that,
Described employing latch units comprises d type flip flop, the data input pin of this d type flip flop is connected with the output of inverter, its input end of clock is connected with the 3rd control signal, its output is connected with the output OUT of single-stage comparator, and the 3rd control signal triggers the level signal that described d type flip flop sampling single-stage comparing unit exports after the second switch conducting scheduled time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510176346.1A CN104734677B (en) | 2015-04-14 | 2015-04-14 | Single stage comparator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510176346.1A CN104734677B (en) | 2015-04-14 | 2015-04-14 | Single stage comparator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104734677A true CN104734677A (en) | 2015-06-24 |
| CN104734677B CN104734677B (en) | 2017-05-24 |
Family
ID=53458192
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510176346.1A Active CN104734677B (en) | 2015-04-14 | 2015-04-14 | Single stage comparator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104734677B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1511173A2 (en) * | 2003-08-28 | 2005-03-02 | Flying Mole Corporation | Power conversion apparatus and dead time generator |
| CN102420594A (en) * | 2011-12-15 | 2012-04-18 | 无锡中星微电子有限公司 | Comparator |
| CN102843136A (en) * | 2012-09-15 | 2012-12-26 | 复旦大学 | Method for correcting offset of high-speed high-precision large-range low-power-consumption dynamic comparator |
| CN104113310A (en) * | 2013-04-22 | 2014-10-22 | 三星显示有限公司 | Mismatched Differential Circuit |
| CN104320139A (en) * | 2014-09-29 | 2015-01-28 | 清华大学 | Charge matching-based offset correction method of full-symmetric four-terminal dynamic comparator |
| CN204578500U (en) * | 2015-04-14 | 2015-08-19 | 无锡中星微电子有限公司 | Single-stage comparator |
-
2015
- 2015-04-14 CN CN201510176346.1A patent/CN104734677B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1511173A2 (en) * | 2003-08-28 | 2005-03-02 | Flying Mole Corporation | Power conversion apparatus and dead time generator |
| CN102420594A (en) * | 2011-12-15 | 2012-04-18 | 无锡中星微电子有限公司 | Comparator |
| CN102843136A (en) * | 2012-09-15 | 2012-12-26 | 复旦大学 | Method for correcting offset of high-speed high-precision large-range low-power-consumption dynamic comparator |
| CN104113310A (en) * | 2013-04-22 | 2014-10-22 | 三星显示有限公司 | Mismatched Differential Circuit |
| CN104320139A (en) * | 2014-09-29 | 2015-01-28 | 清华大学 | Charge matching-based offset correction method of full-symmetric four-terminal dynamic comparator |
| CN204578500U (en) * | 2015-04-14 | 2015-08-19 | 无锡中星微电子有限公司 | Single-stage comparator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104734677B (en) | 2017-05-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103023469B (en) | A kind of boot-strapped switch circuit | |
| US9379702B2 (en) | Sample and hold switch circuit | |
| KR102549745B1 (en) | Voltage comparator, voltage comparation method of the same, and reset method of the same | |
| CN102981543A (en) | Drive circuit of ultralow-power-consumption linear voltage stabilizer | |
| CN102832919A (en) | Grid voltage bootstrapped switch circuit | |
| CN105187039A (en) | CMOS gate voltage bootstrapping switch circuit | |
| CN104333357B (en) | Hold time optimization circuits | |
| CN204578500U (en) | Single-stage comparator | |
| US9331685B2 (en) | Comparator system | |
| CN103529895B (en) | A kind of High-stability voltage regulator | |
| CN104881072A (en) | Low-dropout voltage regulator and power supply system | |
| CN105897196A (en) | Feedforward compensation push-pull operational amplifier | |
| CN105763177A (en) | Hysteresis comparator | |
| CN105070318A (en) | High-speed shift register applied to successive approximation type analog-to-digital converter | |
| CN204631670U (en) | Low difference voltage regulator and electric power system | |
| CN107370485B (en) | Negative voltage level conversion circuit | |
| CN104734677A (en) | Single stage comparator | |
| CN107565951A (en) | Multimode signal generating circuit | |
| CN102082562A (en) | Duty cycle regulating circuit and duty cycle regulating method | |
| CN203588106U (en) | Improved voltage following circuit | |
| CN104300949A (en) | Low-voltage resetting circuit for radio frequency chip of internet of things | |
| CN107040249B (en) | Circuit for trimming and judging reverse voltage threshold of comparator | |
| CN203747798U (en) | Sampling switch circuit | |
| CN105425008A (en) | Internet of things high sensitivity magnetic-sensor sampling circuit | |
| CN103326700A (en) | Bootstrap sampling switch circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 214028 Jiangsu Province, Wuxi City District Qingyuan Road No. 18 Taihu International Science Park sensor network university science and Technology Park 530 building A1001 Applicant after: WUXI ZHONGGAN MICROELECTRONIC CO., LTD. Address before: 214028 Jiangsu Province, Wuxi City District Qingyuan Road No. 18 Taihu International Science Park sensor network university science and Technology Park 530 building A1001 Applicant before: Wuxi Vimicro Co., Ltd. |
|
| COR | Change of bibliographic data | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |