CN104734666A - Chip control circuit - Google Patents
Chip control circuit Download PDFInfo
- Publication number
- CN104734666A CN104734666A CN201310698694.6A CN201310698694A CN104734666A CN 104734666 A CN104734666 A CN 104734666A CN 201310698694 A CN201310698694 A CN 201310698694A CN 104734666 A CN104734666 A CN 104734666A
- Authority
- CN
- China
- Prior art keywords
- chip
- filter circuit
- device chip
- data signals
- electronic data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Networks Using Active Elements (AREA)
Abstract
A chip control circuit comprises a control chip, a plurality of equipment chips connected with the control chip, a first filter circuit, and a second filter circuit, wherein the control chip can send electronic data signals to each equipment chip or receives electronic data signals sent by each equipment chip; the first filter circuit is connected with the control chip; the second filter circuit is connected with the first filter circuit and each equipment chip; and the distance between the first filter circuit and the control chip is equal to the distance between the second filter circuit and the plurality of equipment chips. When the control chip sends the electronic data signals to each equipment chip, the electronic data signals are filtered sequentially via the first filter circuit and the second filter circuit and then sent to each equipment chip. When the control chip receives the electronic data signals sent by each equipment chip, the electronic data signals are filtered sequentially via the second filter circuit and the first filter circuit and then sent to the control chip.
Description
Technical field
The present invention relates to a kind of chip control circuit.
Background technology
Along with electronic device operation clock frequency is more and more higher, track lengths is more and more longer, also more and more higher to the high-speed transfer designing requirement between electronic device.As, common a kind of wire structures, include a unique controller chip and some device chip being connected to described controller chip.Described controller chip can receive from several device chip or send electronic data signals, and the contact of not electronic data signals intercommunication between device chip.But this some device chip is connected on same controller chip simultaneously, transmit between described controller chip and described some device chip or waveform between the electronic data signals that receives just very unstable.
Summary of the invention
In view of above content, be necessary to provide a kind of chip control circuit improving electronic data signals.
A kind of chip control circuit, include a control chip, some device chip being connected to described control chip, one first filter circuit, with one second filter circuit, described control chip can send electronic data signals to each device chip or receive the electronic data signals of each device chip transmission, described first filter circuit is connected to described control chip, described second filter circuit is connected to described first filter circuit and each device chip, when described control chip sends electronic data signals to each device chip, described electronic data signals is sent to each device chip after carrying out filtering by described first filter circuit and the second filter circuit successively, when described control chip receives the electronic data signals sent of each device chip, described electronic data signals is sent to described control chip after carrying out filtering by described second filter circuit and described first filter circuit successively.
Further, described chip control circuit also includes a first node, and described first filter circuit is connected to described control chip by described first node.
Further, described first filter circuit includes one first resistance and an electric capacity, and one end of described first resistance is connected to a power supply, and the other end is connected to described first node, and one end of described electric capacity is connected to described first node, other end ground connection.
Further, described chip control circuit also includes a Section Point, and described second filter circuit is connected to each device chip by described Section Point.
Further, described chip control circuit also includes some 3rd nodes, and each device chip is connected to described Section Point by each the 3rd node.
Further, the device chip in described some device chip is also connected with one second resistance, and described second resistance is connected to described power supply.
Further, the resistance of described first resistance is 110 Ω, and the resistance of described second resistance is 220 Ω.
Further, described second filter circuit comprises an inductance.
Compared with prior art, control chip in said chip control circuit and be connected with the first filter circuit and the second filter circuit between some device chip, the waveform of the electronic data signals transmitted between described controller chip and described some device chip or receive just can carry out filtering by described first filter circuit and the second filter circuit, and the electronic data signals transmitting between described controller chip and described some device chip or receive is stablized.
Accompanying drawing explanation
Fig. 1 is a stereogram of a better embodiment of chip control circuit of the present invention.
Fig. 2 is a stereogram of another better embodiment of chip control circuit of the present invention.
Main element symbol description
| Control chip | 10 |
| First node | 20 |
| Device chip | 30 |
| First device chip | 31 |
| 3rd node | 311 |
| Second device chip | 32 |
| 4th node | 321 |
| 3rd device chip | 33 |
| 5th node | 331 |
| 4th device chip | 34 |
| 6th node | 341 |
| First filter circuit | 40 |
| Power supply | 50 |
| Second filter circuit | 60 |
| Section Point | 70 |
Following embodiment will further illustrate the present invention in conjunction with above-mentioned accompanying drawing.
Embodiment
Refer to Fig. 1 and Fig. 2, in a better embodiment of the present invention, a chip control circuit comprises a control chip 10 and some device chip 30 being connected to described control chip 10.In one embodiment, described control chip 10 is all two-way chips with described device chip 30, all can be used for sending or receiving electronic data signals.Described control chip 10 can receive or send electronic data signals from each device chip 30.Described device chip 30 can be 3 (see figure 1)s or more than 3, as 5 (see figure 2)s.The transmission of electronic data signals is not had between described some device chip 30.
Described control chip 10 connects a first node 20.Described first node 20 connects one first filter circuit 40.Described filter circuit 40 includes an one first resistance R1 and electric capacity C1.One end of described first resistance R1 is connected with a power supply 50, and the other end connects described first node 20.The resistance of described first resistance R1 is transformable.The resistance of described first resistance R1 can increase according to the length of the wiring between described control chip 10 and described device chip 30 and become large.In one embodiment, the resistance of described first resistance R1 is 110 Ω.One end of described first electric capacity C1 connects described first node 20, other end ground connection.
Described first filter circuit 40 is also connected with one second filter circuit 60.In one embodiment, described second filter circuit 60 comprises an inductance.Described inductance using by can be used as a wire during current stabilization on it, when curent change, during as become large or diminishing, stops ER effect large or diminish, to reach the effect of filtering.Described second filter circuit 60 also connects a Section Point 70.
Refer to Fig. 1, described three device chip 30 include three device chip 33 of one first device chip 31,1 second device chip 32 and between described first device chip 31 and the second device chip 32.Described first device chip 31, second device chip 32, in parallel with the 3rd device chip 33.Described first device chip 31 is connected to described Section Point 70 by one the 3rd node 311.Described 3rd node 311 is connected with one second resistance R2.Described second resistance R2 is connected to described power supply 50.Described second device chip 32 is connected to described Section Point 70 by one the 4th node 321.Described 3rd node 321 connects one the 3rd resistance R3.Described 3rd resistance R3 is connected to described power supply 50.Described 3rd device chip 33 is connected to described Section Point 70 by one the 5th node 331.In one embodiment, the resistance of described second resistance R2 and described 3rd resistance R3 is 220 Ω.
Refer to Fig. 2, described device chip 30 can the first device chip 31 with in the second device chip 32 separately again and connect one the 4th device chip 34.Each the 4th device chip 34 is all connected to described Section Point 70 by one the 6th node 341.Such as similar, described device chip 30 can be device chip that is multiple and that connect, and when connected, each device chip is all connected to described Section Point by a node and gets final product 70.In addition, described first device chip 31 is respectively connected with device chip 32 resistance that one is connected to described power supply 50.In another embodiment, if be connected to position between the device chip of described Section Point 70 and described Section Point 70 far away time, also can as described in connect the first device chip 31 one be connected to as described in the resistance (not shown) of power supply 50.
During use, when described control chip 10 sends electronic data signals to each device chip in described device chip 30, described electronic data signals is when described first filter circuit 20 and the second filter circuit 60, described electronic data signals ripple is carried out filtering by described first filter circuit 20 and the second filter circuit 60 successively, thus enables electronic data signals be sent to each device chip of described device chip 30 reposefully from described control chip 10.When each device chip in described device chip 30 sends electronic data signals to described control chip 10, described electronic data signals is when described second filter circuit 60 and the first filter circuit 20, described electronic data signals ripple is carried out filtering by described second filter circuit 60 and the first filter circuit 20 successively, thus enables electronic data signals be sent to control chip 10 from each device chip of described device chip 30 reposefully.
In the present embodiment, described first filter circuit 20 is near described control chip 10.Described second filter circuit 60 is near described device chip 30.Such as, distance between described control chip 10 and described device chip 30 is divided into 10 parts, described first filter circuit 20 is positioned at first part near described control chip 10, and described second filter circuit 60 is positioned at first part near described device chip 10.That is, the distance between described first filter circuit 20 and described control chip 10 equals the distance between described device chip 30 and described second filter circuit 60.Like this, no matter be that described control chip 10 sends electronic data signals to each device chip in described device chip 30, or each device chip in described control chip 10 receiving equipment chip 30 sends electronic data signals, each device chip in described control chip 10 and described device chip 30 is all stable electronic data signals ripples.
Claims (8)
1. a chip control circuit, include a control chip and some device chip being connected to described control chip, described control chip can send electronic data signals to each device chip or receive the electronic data signals of each device chip transmission, it is characterized in that: described chip control circuit also includes one first filter circuit and one second filter circuit, described first filter circuit is connected to described control chip, described second filter circuit is connected to described first filter circuit and each device chip, distance between described first filter circuit and control chip equals the distance between described second filter circuit and described some device chip, when described control chip sends electronic data signals to each device chip, described electronic data signals is sent to each device chip after carrying out filtering by described first filter circuit and the second filter circuit successively, when described control chip receives the electronic data signals sent of each device chip, described electronic data signals is sent to described control chip after carrying out filtering by described second filter circuit and described first filter circuit successively.
2. chip control circuit as claimed in claim 1, it is characterized in that: described chip control circuit also includes a first node, described first filter circuit is connected to described control chip by described first node.
3. chip control circuit as claimed in claim 2, it is characterized in that: described first filter circuit includes one first resistance and an electric capacity, one end of described first resistance is connected to a power supply, the other end is connected to described first node, one end of described electric capacity is connected to described first node, other end ground connection.
4. chip control circuit as claimed in claim 3, it is characterized in that: described chip control circuit also includes a Section Point, described second filter circuit is connected to each device chip by described Section Point.
5. chip control circuit as claimed in claim 4, it is characterized in that: described chip control circuit also includes some 3rd nodes, each device chip is connected to described Section Point by each the 3rd node.
6. chip control circuit as claimed in claim 5, it is characterized in that: the device chip in described some device chip is also connected with one second resistance, described second resistance is connected to described power supply.
7. chip control circuit as claimed in claim 1, it is characterized in that: the resistance of described first resistance is 110 Ω, the resistance of described second resistance is 220 Ω.
8. chip control circuit as claimed in claim 1, is characterized in that: described second filter circuit comprises an inductance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310698694.6A CN104734666A (en) | 2013-12-19 | 2013-12-19 | Chip control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310698694.6A CN104734666A (en) | 2013-12-19 | 2013-12-19 | Chip control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104734666A true CN104734666A (en) | 2015-06-24 |
Family
ID=53458181
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310698694.6A Pending CN104734666A (en) | 2013-12-19 | 2013-12-19 | Chip control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104734666A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060109939A1 (en) * | 2004-11-19 | 2006-05-25 | Steven Ciccarelli | Noise reduction filtering in a wireless communication system |
| CN1868133A (en) * | 2003-08-28 | 2006-11-22 | Gct半导体公司 | System and method for filtering signals in a transceiver |
| CN101488884A (en) * | 2008-01-14 | 2009-07-22 | 宏正自动科技股份有限公司 | Control device, data processing device and its use method |
| CN102902333A (en) * | 2011-07-27 | 2013-01-30 | 鸿富锦精密工业（深圳）有限公司 | Power supply control circuit |
| CN102928040A (en) * | 2012-11-01 | 2013-02-13 | 江苏科技大学 | Ship-lock multi-channel water level measuring system and filter method thereof |
| CN103457637A (en) * | 2013-08-21 | 2013-12-18 | 南京宇能仪表有限公司 | Double-channel power line carrier communication module circuit and application thereof |
-
2013
- 2013-12-19 CN CN201310698694.6A patent/CN104734666A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1868133A (en) * | 2003-08-28 | 2006-11-22 | Gct半导体公司 | System and method for filtering signals in a transceiver |
| US20060109939A1 (en) * | 2004-11-19 | 2006-05-25 | Steven Ciccarelli | Noise reduction filtering in a wireless communication system |
| CN101488884A (en) * | 2008-01-14 | 2009-07-22 | 宏正自动科技股份有限公司 | Control device, data processing device and its use method |
| CN102902333A (en) * | 2011-07-27 | 2013-01-30 | 鸿富锦精密工业（深圳）有限公司 | Power supply control circuit |
| CN102928040A (en) * | 2012-11-01 | 2013-02-13 | 江苏科技大学 | Ship-lock multi-channel water level measuring system and filter method thereof |
| CN103457637A (en) * | 2013-08-21 | 2013-12-18 | 南京宇能仪表有限公司 | Double-channel power line carrier communication module circuit and application thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101464724B (en) | Multi-channel master-salve equipment communication circuit | |
| CN101594171B (en) | Power cord chopper communication transceiving circuit | |
| CN109547314A (en) | One kind being based on the cascade M-LVDS bus system of long line and method | |
| CN105141492A (en) | CAN transmitting-receiving module and manufacturing method thereof | |
| CN204948102U (en) | A kind of CAN transceiver module | |
| CN203708242U (en) | Power line modem | |
| US20170194928A1 (en) | Coupling circuits for use with universal power over ethernet | |
| CN204681392U (en) | A kind of vehicular transreceiver of Auto-matching reception antenna type | |
| CN104734666A (en) | Chip control circuit | |
| CN209462396U (en) | Based on the cascade M-LVDS bus system of long line | |
| JP2016066946A (en) | Signal transmission cable | |
| CN106326174A (en) | Two-wire communication circuit | |
| CN105159158A (en) | Electrical bus applicable to micro satellites | |
| CN205017297U (en) | Serial port communication's level shifting circuit | |
| CN204930874U (en) | A kind of express delivery cabinet | |
| CN109240262B (en) | Bus circuit and intelligent goods shelf system | |
| CN201515367U (en) | Power line chopping communication transceiver circuit | |
| CN209400918U (en) | CAN bus network structure | |
| US20130049461A1 (en) | Circuit topology of printed circuit board | |
| CN201689889U (en) | Cascade circuit for physical layer of Ethernet | |
| CN104243256A (en) | RS485 bus star-shaped extension device and method | |
| CN201122963Y (en) | Device for power supply by twisted pair line and implementing multi-machine digital communication | |
| CN203644031U (en) | RS485 signal forwarding device | |
| CN104079285A (en) | Signal line receiving circuit, signal line power supply circuit and signal line power supply system | |
| CN203661089U (en) | Coupling circuit of Ethernet PHY chip and optical module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150624 |