CN104733520A - Thyristor for electrostatic protection - Google Patents
Thyristor for electrostatic protection Download PDFInfo
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- CN104733520A CN104733520A CN201510118418.7A CN201510118418A CN104733520A CN 104733520 A CN104733520 A CN 104733520A CN 201510118418 A CN201510118418 A CN 201510118418A CN 104733520 A CN104733520 A CN 104733520A
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- pmos
- nmos tube
- pipe
- electrostatic protection
- pnp pipe
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Abstract
The invention discloses a thyristor for electrostatic protection. The thyristor comprises a first NMOS tube M2, a second NMOS tube M3, a first PMOS tube M1, a second PMOS tube M4, a PNP tube T1, an NPN tube T2 and a pull-down resistor RPWELL. By means of the thyristor for electrostatic protection, the defects that in the prior art, the protection reliability is low, the misoperation rate is high, and the safety performance is poor can be overcome, and the advantages of being high in protection reliability, low in misoperation rate and good in safety are achieved accordingly.
Description
Technical field
The present invention relates to electronic circuit technology field, particularly, relate to a kind of electrostatic protection thyristor.
Background technology
Be otherwise known as silicon controlled rectifier device (Silicon-Controlled Rectifier, SCR) thyristor.In integrated circuit CMOS technology; thyristor is well used in electrostatic discharge protective circuit to prevent electrostatic breakdown (ESD); usually the anode of thyristor and negative electrode are connected in electrostatic discharge protective circuit; under normal operation; the electrical potential difference at thyristor the two poles of the earth is no more than its trigger voltage; thyristor not conducting; and when producing ESD electrostatic pulse; because ESD electrostatic pulse has large voltage; high-octane characteristic; therefore be easy to trigger turn on thyristors, thus via thyristor release, realize the object of electrostatic protection.
At present, use SCR as ESD protective device, usually can run into two problems, one is that the trigger voltage of SCR is too high, effectively can not realize esd protection.Two is once after SCR conducting, only needs lower maintenance voltage that SCR just can be made to maintain conducting state, SCR therefore will be avoided when chip normally works by false triggering to be occurred latch-up (Latch up) between anode and negative electrode.
The present invention is directed to above-mentioned two problems, devise a kind of Novel SCR circuit, not only there is very low trigger voltage, and can ensure to avoid SCR be triggered and occur Latch up when chip normally works.
Fig. 1 is the structure chart of traditional SCR.Under normal circumstances, this SCR not conducting.When forward esd pulse appears in anode, and during minus earth, along with the rising of ESD positive voltage, NWELL/PWELL is finally made reverse breakdown to occur and produce larger reverse breakdown current, this electric current flows through PWELL resistance and produces the base-emitter positively biased that pressure drop makes parasitic NPN pipe, thus NPN pipe conducting have electric current to flow through, this On current flows through again NWELL resistance and produces emitter-base stage positively biased that pressure drop makes parasitic PNP pipe at its two ends, and thus PNP pipe also can conducting.Positive feedback effect makes SCR(PNPN thus) be triggered conducting.Can see that the trigger voltage of SCR depends on the reverse breakdown of NWELL/PWELL, and this reverse breakdown voltage is general all very high, therefore the trigger voltage of SCR is also very high.This traditional SCR when this SCR is used as esd protection circuit, there will be the inner protected circuit situation that SCR is not also triggered by burning, so can not provide effective esd protection.
Fig. 2 is that existing a kind of low-voltage triggers SCR(diode-trigger SCR).Under normal circumstances, this SCR not conducting.When forward esd pulse appears in anode, and during minus earth, along with the rising of ESD positive voltage, finally make the whole conducting of series diode, have larger current directly to flow into negative electrode from anode through series diode and PWELL resistance.Now PWELL resistance two ends produce the base-emitter positively biased that voltage drop makes parasitic NPN, the conducting of NPN pipe.This On current flows through again NWELL resistance and produces emitter-base stage positively biased that pressure drop makes parasitic PNP pipe at its two ends, and thus PNP pipe also can conducting.Positive feedback effect makes SCR(PNPN thus) be triggered conducting.By regulating the number of series diode, we effectively can control the trigger voltage of this SCR, thus can realize the SCR of a low-voltage triggering.But the shortcoming of this structure is, under chip normal operative condition, if anode flows into appearance Latch-up electric current, this SCR is easy to be made circuit be in Latch-up state by false triggering.
Can see from top is introduced, the trigger voltage that existing SCR has is too high, effectively can not realize esd protection, although the trigger voltage had is lower, the risk of Latch-up occurs when still can not reduce normal work.
Realizing in process of the present invention, inventor finds at least to exist in prior art that protection reliability is low, misuse rate is high and the defect such as poor stability.
Summary of the invention
The object of the invention is to, for the problems referred to above, propose a kind of electrostatic protection thyristor, to realize the advantage that protection reliability is high, misuse rate is low and fail safe is good.
For achieving the above object, the technical solution used in the present invention is: a kind of electrostatic protection thyristor, comprises the first NMOS tube M2, the second NMOS tube M3, the first PMOS M1, the second PMOS M4, PNP pipe T
1, NPN pipe T
2, and pull down resistor R
pWELL; Wherein:
Described PNP pipe T
1emitter as the anode A node of this electrostatic protection thyristor, PNP pipe T
1emitter be connected with the source electrode of the first PMOS M1 and the source electrode of the second PMOS M4 respectively; PNP pipe T
1base stage respectively with the drain electrode of the first PMOS M1, the source electrode of the first NMOS tube M2, the grid of the second PMOS M4 and NPN pipe T
2collector electrode connect; PNP pipe T
1collector electrode respectively with drain electrode and the NPN pipe T of the second PMOS M4
2base stage connect;
Described NPN pipe T
2base stage by pull down resistor R
pWELLafterwards as the negative electrode Cathode of this electrostatic protection thyristor, NPN pipe T
2base stage by pull down resistor R
pWELLafter be also connected with the drain electrode of the second NMOS tube M3;
The grid of described first PMOS M1 is connected with the drain electrode of the grid of the first NMOS tube M2, the grid of the second NMOS tube M3 and the second NMOS tube M3 respectively; The drain electrode of the first NMOS tube M2 is connected with the source electrode of the second NMOS tube M3.
Owing to have employed pull down resistor R
pWELL, make this electrostatic protection thyristor, when there being ESD, the second PMOS M4 opens, and is formed from anode A node through the second PMOS M4, pull down resistor R
pWELLto the path of negative electrode Cathode, make NPN pipe T
2the effective lifting of base potential, NPN pipe T
2open.
Further, this electrostatic protection thyristor, also comprises delay capacitor C
1; Described delay capacitor C
1be connected between the grid of the first PMOS M1 and the source electrode of the first PMOS M1.
Further, this electrostatic protection thyristor, also comprises coupling resistance R
1; Described coupling resistance R
1be connected between the grid of the first PMOS M1 and the drain electrode of the second NMOS tube M3;
When not having ESD to occur, the first NMOS tube M2, the second NMOS tube M3 close, and the first PMOS M1 opens parasitic PNP pipe and PNP pipe T
1base potential be pulled up to anode A node current potential, PNP pipe T
1emitter-base stage can not positively biased, PNP pipe cannot be opened; Thyristor cannot conducting;
When there is ESD situation, make the first NMOS tube M2, the second NMOS tube M3 unlatching, PNP pipe T
1base potential dragged down, simultaneously the second PMOS M4 opens and makes NPN pipe T
2base potential be driven high, PNP pipe T
1emitter-base stage and NPN pipe T
2base-emitter all enter positively biased state, whole electrostatic protection thyristor can open electric discharge rapidly.
The electrostatic protection thyristor of various embodiments of the present invention, owing to comprising the first NMOS tube M2, the second NMOS tube M3, the first PMOS M1, the second PMOS M4, PNP pipe T
1, NPN pipe T
2, and pull down resistor R
pWELL; Thus can overcome in prior art that protection reliability is low, misuse rate is high and the defect of poor stability, to realize the advantage that protection reliability is high, misuse rate is low and fail safe is good.
Other features and advantages of the present invention will be set forth in the following description, and, partly become apparent from specification, or understand by implementing the present invention.
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Accompanying drawing explanation
Accompanying drawing is used to provide a further understanding of the present invention, and forms a part for specification, together with embodiments of the present invention for explaining the present invention, is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is the structure chart of traditional SCR;
Fig. 2 is the operation principle schematic diagram that existing a kind of low-voltage triggers SCR;
Fig. 3 is the operation principle schematic diagram of electrostatic protection thyristor of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the preferred embodiments of the present invention are described, should be appreciated that preferred embodiment described herein is only for instruction and explanation of the present invention, is not intended to limit the present invention.
According to the embodiment of the present invention, as shown in Figure 3, provide a kind of electrostatic protection thyristor, i.e. a kind of Novel thyristor circuit design for electrostatic protection.
Object of the present invention designs a kind of SCR efficiently exactly and is used as esd protection circuit, has lower trigger voltage on the one hand, can reduce the risk that Latch-up occurs on the other hand when normal work.
Fig. 3 is technical scheme of the present invention.During usual application, the minus earth of SCR, anode connection signal PAD or power vd D.When not having ESD to occur, NMOS tube M2, M3 close, PMOS M1 opens base stage (A point) voltage boost of parasitic PNP pipe to anode potential, guarantee that the emitter-base stage of PNP pipe can not positively biased, PNP pipe cannot be opened, even if now flow into Latch-up electric current at anode also cannot make SCR conducting, therefore effectively prevent the generation of Latch-up phenomenon.When there is ESD situation, along with the quick rising of esd pulse voltage on anode, due to coupling effect and the late effect of capacitance resistance network, M2, M3 are opened, base stage (A point) current potential of PNP pipe is dragged down, M4 opens and the base stage of NPN pipe (B point) current potential is driven high simultaneously, and therefore emitter-the base stage of PNP pipe and the base-emitter of NPN pipe are easy to enter positively biased state, and whole SCR can open electric discharge rapidly.Therefore, under ESD state, this structure can realize lower trigger voltage.
Compared with prior art, technical scheme of the present invention, at least has the following advantages:
(1) technical scheme of the present invention, has comparatively low trigger voltage, can provide efficient esd protection;
(2) technical scheme of the present invention, can reduce the risk that Latch-up occurs in the chips greatly during practical application;
(3) technical scheme of the present invention, without the need to increasing any processing step and production cost.
Last it is noted that the foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, although with reference to previous embodiment to invention has been detailed description, for a person skilled in the art, it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein portion of techniques feature.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (3)
1. an electrostatic protection thyristor, is characterized in that, comprises the first NMOS tube M2, the second NMOS tube M3, the first PMOS M1, the second PMOS M4, PNP pipe T
1, NPN pipe T
2, and pull down resistor R
pWELL; Wherein:
Described PNP pipe T
1emitter as the anode A node of this electrostatic protection thyristor, PNP pipe T
1emitter be connected with the source electrode of the first PMOS M1 and the source electrode of the second PMOS M4 respectively; PNP pipe T
1base stage respectively with the drain electrode of the first PMOS M1, the source electrode of the first NMOS tube M2, the grid of the second PMOS M4 and NPN pipe T
2collector electrode connect; PNP pipe T
1collector electrode respectively with drain electrode and the NPN pipe T of the second PMOS M4
2base stage connect;
Described NPN pipe T
2base stage by pull down resistor R
pWELLafterwards as the negative electrode Cathode of this electrostatic protection thyristor, NPN pipe T
2base stage by pull down resistor R
pWELLafter be also connected with the drain electrode of the second NMOS tube M3;
The grid of described first PMOS M1 is connected with the drain electrode of the grid of the first NMOS tube M2, the grid of the second NMOS tube M3 and the second NMOS tube M3 respectively; The drain electrode of the first NMOS tube M2 is connected with the source electrode of the second NMOS tube M3.
2. electrostatic protection thyristor according to claim 1, is characterized in that, this electrostatic protection thyristor, also comprises delay capacitor C
1; Described delay capacitor C
1be connected between the grid of the first PMOS M1 and the source electrode of the first PMOS M1.
3. electrostatic protection thyristor according to claim 1 and 2, is characterized in that, this electrostatic protection thyristor, also comprises coupling resistance R
1; Described coupling resistance R
1be connected between the grid of the first PMOS M1 and the drain electrode of the second NMOS tube M3;
When not having ESD to occur, the first NMOS tube M2, the second NMOS tube M3 close, and the first PMOS M1 opens parasitic PNP pipe and PNP pipe T
1base potential be pulled up to anode A node current potential, PNP pipe T
1emitter-base stage can not positively biased, PNP pipe cannot be opened; Thyristor cannot conducting;
When there is ESD situation, make the first NMOS tube M2, the second NMOS tube M3 unlatching, PNP pipe T
1base potential dragged down, simultaneously the second PMOS M4 opens and makes NPN pipe T
2base potential be driven high, PNP pipe T
1emitter-base stage and NPN pipe T
2base-emitter all enter positively biased state, whole electrostatic protection thyristor can open electric discharge rapidly.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510118418.7A CN104733520B (en) | 2015-03-18 | 2015-03-18 | A kind of electrostatic protection IGCT |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510118418.7A CN104733520B (en) | 2015-03-18 | 2015-03-18 | A kind of electrostatic protection IGCT |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104733520A true CN104733520A (en) | 2015-06-24 |
| CN104733520B CN104733520B (en) | 2017-10-31 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510118418.7A Active CN104733520B (en) | 2015-03-18 | 2015-03-18 | A kind of electrostatic protection IGCT |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106129056A (en) * | 2016-07-01 | 2016-11-16 | 中国电子科技集团公司第五十八研究所 | The export structure of high ESD tolerance based on PD SOI technology |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050269641A1 (en) * | 2004-06-04 | 2005-12-08 | Chun-Hsiang Lai | Electrostatic protection circuit |
| US6989979B1 (en) * | 2003-09-22 | 2006-01-24 | Pericom Semiconductor Corp. | Active ESD shunt with transistor feedback to reduce latch-up susceptibility |
| CN102208408A (en) * | 2010-03-31 | 2011-10-05 | 上海宏力半导体制造有限公司 | Gate-drive thyristor and electrostatic protection circuit |
| CN104242285A (en) * | 2014-09-11 | 2014-12-24 | 北京大学 | Clamp ESD protection circuit for latch-up prevention type power supply |
| CN204464291U (en) * | 2015-03-18 | 2015-07-08 | 单毅 | A kind of electrostatic protection thyristor |
-
2015
- 2015-03-18 CN CN201510118418.7A patent/CN104733520B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6989979B1 (en) * | 2003-09-22 | 2006-01-24 | Pericom Semiconductor Corp. | Active ESD shunt with transistor feedback to reduce latch-up susceptibility |
| US20050269641A1 (en) * | 2004-06-04 | 2005-12-08 | Chun-Hsiang Lai | Electrostatic protection circuit |
| CN102208408A (en) * | 2010-03-31 | 2011-10-05 | 上海宏力半导体制造有限公司 | Gate-drive thyristor and electrostatic protection circuit |
| CN104242285A (en) * | 2014-09-11 | 2014-12-24 | 北京大学 | Clamp ESD protection circuit for latch-up prevention type power supply |
| CN204464291U (en) * | 2015-03-18 | 2015-07-08 | 单毅 | A kind of electrostatic protection thyristor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106129056A (en) * | 2016-07-01 | 2016-11-16 | 中国电子科技集团公司第五十八研究所 | The export structure of high ESD tolerance based on PD SOI technology |
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| Publication number | Publication date |
|---|---|
| CN104733520B (en) | 2017-10-31 |
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