CN104733474B - Array base palte and preparation method thereof, display device - Google Patents
Array base palte and preparation method thereof, display device Download PDFInfo
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Abstract
The present invention relates to display technology field, more particularly to a kind of array base palte and preparation method thereof, display device.The array base palte includes substrate, the substrate is provided with first electrode layer and the second electrode lay, electrode dielectric layer is provided between the first electrode layer and the second electrode lay, groove is provided with the electrode dielectric layer, the groove is located at the close side of the close the second electrode lay of the first electrode layer, the screen layer of coupled capacitor between the first electrode layer and the second electrode lay can be shielded by being provided with the groove, the screen layer insulate with the first electrode layer and the second electrode lay, and the shielding layer grounding.The array base palte of the present invention solves the technical problem that can not effectively avoid the coupled voltages between two electrodes, and it can be applied in Thin Film Transistor-LCD.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of array base palte and preparation method thereof, display device.
Background technology
Current thin film transistor liquid crystal display (TFT-LCD) (Thin Film Transistor Liquid Crystal Display,
Abbreviation TFT-LCD) display pattern mainly have TN (Twisted Nematic, twisted-nematic) pattern, IPS (In Plane
Switching, in-plane conversion) pattern, FFS (Fringe Field Switching, fringe field switching) pattern etc..TFT-
LCD array base palte generally include gate electrode, source drain electrode (including between source electrode, drain electrode and source electrode and drain electrode
Raceway groove), pixel electrode, public electrode etc., electric charge is easily collected on electrode, can produce coupled capacitor between electrodes.
Some coupled capacitors are not what people wanted, such as the coupled capacitor between source electrode and pixel electrode.These
Coupled capacitor can not only cause the waste of electric energy, it is also possible to cause the generation of crosstalk phenomenon, crosstalk phenomenon can make display picture
Distortion.Coupled capacitor between coupled capacitor, data wire and pixel electrode especially between source electrode and pixel electrode etc., meeting
Cause serious crosstalk phenomenon.
The content of the invention
Embodiments of the invention provide a kind of array base palte and preparation method thereof, display device, and it can greatly reduce
Coupled capacitor between two electrodes.
To reach above-mentioned purpose, embodiments of the invention adopt the following technical scheme that：
On the one hand, there is provided a kind of array base palte, including substrate, the substrate are provided with first electrode layer and second electrode
Layer, is provided with electrode dielectric layer, groove is provided with the electrode dielectric layer between the first electrode layer and the second electrode lay,
The groove is located at the close side of the close the second electrode lay of the first electrode layer, and the groove is provided with and can shielded
The screen layer of coupled capacitor between the first electrode layer and the second electrode lay, the screen layer and the first electrode layer
Insulated with the second electrode lay, and the shielding layer grounding.
In addition to setting screen layer in the close side of the first electrode, the electrode dielectric layer also extends into institute
The top of first electrode layer is stated, and the screen layer also extends into the top of the first electrode layer.
In the preferred scheme of such scheme, the electrode dielectric layer also further extends into the remote of the first electrode layer
From the remote side of the second electrode lay, and groove also is provided with the electrode dielectric layer of the remote side, the screen layer enters one
Step is extended on the groove of the remote side of the remote the second electrode lay of the first electrode layer.
Or in addition in the close side of the first electrode, screen layer is set, the electrode dielectric layer also position
In the remote side of the remote the second electrode lay of the first electrode layer, and it also is provided with the electrode dielectric layer of the remote side
Groove, the screen layer are also located on the groove of the remote side of the remote the second electrode lay of the first electrode layer.
Further, the first electrode layer and the second electrode lay are source electrode layer and pixel electrode layer respectively, or grid
Electrode layer and pixel electrode layer, either data wire and pixel electrode layer or scan line and pixel electrode layer.
Any of the above-described scheme is preferably, in addition to common electrode layer, the screen layer by with the common electrode layer
It is grounded.Specifically, including the array base palte of common electrode layer has following two structures：
The first structure：The first electrode layer is source electrode layer, and the second electrode lay is pixel electrode layer, the electricity
Pole insulating barrier is covered on the source electrode layer and the common electrode layer, and the pixel electrode layer is located at the electrode dielectric layer
On；The groove exposes the part common electrode layer.
Second of structure：The first electrode layer is source electrode layer, and the second electrode lay is pixel electrode layer, the electricity
Pole insulating barrier is covered on the source electrode layer and the pixel electrode layer, and the common electrode layer is located at the electrode dielectric layer
On.
On the other hand, there is provided a kind of display device of the array base palte comprising described in any of the above-described scheme.
Another further aspect, there is provided a kind of preparation method of array base palte, the array base palte include substrate, specific making side
Method includes：
Deposition of first electrode film on the substrate, the figure of first electrode layer is formed by patterning processes；
Second electrode film is deposited on the substrate, and the figure of the second electrode lay is formed by patterning processes；
Depositing electrode insulating layer of thin-film on the substrate, the figure of electrode dielectric layer is formed by patterning processes, it is described
Electrode dielectric layer is provided with groove, institute between the first electrode layer and the second electrode lay in the electrode dielectric layer
State the close side that groove is located at the close the second electrode lay of the first electrode layer；
The deposition shield layer film on the substrate formed with the electrode dielectric layer, screen layer is formed by patterning processes
Figure, the screen layer are located in the groove, and the screen layer insulate with the first electrode layer and the second electrode lay,
And the shielding layer grounding.
Specifically, the first electrode layer is source electrode layer, and the second electrode lay is pixel electrode layer；The making
Method also includes forming common electrode layer on the substrate, for the first structure introduced in above-mentioned array base palte scheme,
The preparation method is specially：
Source electrode layer and common electrode layer are formed on the substrate；
The depositing electrode insulating layer of thin-film on the substrate for forming active electrode layer and common electrode layer, passes through patterning processes shape
Into the figure of electrode dielectric layer, the electrode dielectric layer is covered on the source electrode layer and the common electrode layer, the electricity
Groove is provided with the insulating barrier of pole, the groove exposes the part common electrode layer；
The deposition shield layer film on the substrate formed with the electrode dielectric layer, screen layer is formed by patterning processes
Figure, the screen layer are located in the groove, and the screen layer insulate with the source electrode layer and the pixel electrode layer, and
The screen layer is grounded by being connected with the common electrode layer；
The pixel electrode layer is formed on the substrate formed with the electrode dielectric layer.
For second of the structure introduced in above-mentioned array base palte scheme, the preparation method is specially：
Source electrode layer and pixel electrode layer are formed on the substrate；
The depositing electrode insulating layer of thin-film on the substrate for forming active electrode layer and pixel electrode layer, passes through patterning processes shape
Into the figure of electrode dielectric layer, the electrode dielectric layer is covered on the source electrode layer and the pixel electrode layer, the electricity
Groove is provided with the insulating barrier of pole；
The common electrode layer is formed on the substrate formed with the electrode dielectric layer, the groove exposes part institute
State common electrode layer；
The deposition shield layer film on the substrate formed with the electrode dielectric layer, screen layer is formed by patterning processes
Figure, the screen layer are located in the groove, and the screen layer insulate with the source electrode layer and the pixel electrode layer, and
The screen layer is grounded by being connected with the common electrode layer.
Array base palte provided in an embodiment of the present invention, set in insulating barrier between electrodes can shield two electrodes it
Between coupled capacitor screen layer, when some electrode potential changes, the electric capacity that the electrode is formed with screen layer is charged, by
In shielding layer grounding, so the current potential of screen layer will not change, therefore the change of the electrode potential will not be to another electrode
Current potential impacts or influenceed the very little become.Therefore, the screen layer of the embodiment of the present invention can greatly reduce two electrodes it
Between coupled capacitor, both reduced the waste of electric energy, and can is enough effectively prevented from the generation of crosstalk phenomenon between two electrodes.
Because screen layer can greatly reduce the coupled capacitor between two electrodes, so without between two electrodes of increase
Distance, also therefore it will not reduce the transmitance of array base palte.Additionally, due to without increasing the distance between two electrodes, so this
The technical scheme of inventive embodiments is also applied for high-resolution array base palte, and it can either make array base palte keep high-resolution
Rate, while can also be effectively prevented from the generation of crosstalk phenomenon between two electrodes.
Brief description of the drawings
Fig. 1 a are the array base palte schematic cross-section of one embodiment of the invention.
Fig. 1 b are that screen layer extends to the signal of the array base palte section directly over first electrode layer in one embodiment of the invention
Figure.
Fig. 1 c are the array base palte that screen layer extends to directly over first electrode layer and remote side in one embodiment of the invention
Schematic cross-section.
Fig. 1 d are that screen layer is located at the array base palte schematic cross-section close to side and remote side in one embodiment of the invention.
Fig. 2 a are the array base palte schematic cross-section of one embodiment of the invention.
Fig. 2 b are the array base palte that screen layer extends to directly over first electrode layer and remote side in one embodiment of the invention
Schematic cross-section.
Fig. 2 c are that screen layer is located at close to side in one embodiment of the invention and the array base palte section away from side is illustrated
Figure.
Fig. 3 is the array base palte surface texture schematic diagram of one embodiment of the invention.
Fig. 4 is cross section structure schematic diagram of the array base palte of embodiment illustrated in fig. 3 along A1-A2.
Fig. 5 is the array base palte schematic cross-section of one embodiment of the invention.
Reference：
1- substrates, 2- first electrode layers, 3- the second electrode lays, 4- electrode dielectric layers, 5- grooves, 6- screen layers, 7- are public
Electrode layer, 8- is close to side, and 9- is away from side, 10- source electrode layers, 11- pixel electrode layers, 12- grid lines, 13- data wires, 14- electric leakages
Pole.
Embodiment
Array base palte of the embodiment of the present invention and preparation method thereof, display device are retouched in detail below in conjunction with the accompanying drawings
State.
It will be appreciated that described embodiment is only the part of the embodiment of the present invention, rather than whole embodiments.
Based on the embodiment in the present invention, those of ordinary skill in the art are obtained all under the premise of creative work is not made
Other embodiments, belong to the scope of protection of the invention.
As shown in Figure 1a, array base palte provided in an embodiment of the present invention includes substrate 1, and the substrate 1 is provided with the first electricity
Pole layer 2 and the second electrode lay 3, electrode dielectric layer 4, the electricity are provided between the first electrode layer 2 and the second electrode lay 3
Groove 5 is provided with pole insulating barrier 4, the groove 5 is located at the close of the close the second electrode lay 3 of the first electrode layer 2
Side 8, the groove 5 are provided with the shielding that can shield coupled capacitor between the first electrode layer 2 and the second electrode lay 3
Layer 6, the screen layer 6 is insulated with the first electrode layer 2 and the second electrode lay 3, and the screen layer 6 is grounded.
Or as shown in Figure 2 a, array base palte provided in an embodiment of the present invention includes substrate 1, the substrate 1 is provided with the
One electrode layer 2 and the second electrode lay 3, electrode dielectric layer 4, institute are provided between the first electrode layer 2 and the second electrode lay 3
State and groove 5 is provided with electrode dielectric layer 4, the groove 5 is located at the close the second electrode lay 3 of the first electrode layer 2
Close to side 8, the groove 5, which is provided with, can shield coupled capacitor between the first electrode layer 2 and the second electrode lay 3
Screen layer 6, the screen layer 6 is insulated with the first electrode layer 2 and the second electrode lay 3, and the screen layer 6 is grounded.
Wherein, the first electrode layer and the second electrode lay can be same layer or different electrodes or other conduction knots respectively
Structure.The section of the groove can be V-shaped, U-shaped or T-shaped or other have the shape of phase same-action.When groove is V words
When shape or U-shaped, screen layer can fill whole groove, can also only be covered in the side of groove, naturally it is also possible to only paste
In certain part of groove.
The material of screen layer can be the alloy or gold of Cr, W, Ti, Ta, Mo, Al or Cu metal or conducting metal
Belong to oxide.Transparent electrode material is generally selected, such as tin indium oxide (Indium Tin Oxide, abbreviation ITO), indium zinc oxide
(IZO) or other transparent electrode materials, because transparent electrode material can improve the transmitance of array base palte.Electrode dielectric layer can
Can be SiH to select oxide, nitride or oxynitrides, corresponding reacting gas4、NH3、N2Mixed gas or
SiH2Cl2、NH3、N2Mixed gas.
Array base palte provided in an embodiment of the present invention, set in insulating barrier between electrodes can shield two electrodes it
Between coupled capacitor screen layer, when some electrode potential changes, the electric capacity that the electrode is formed with screen layer is charged, by
In shielding layer grounding, so the current potential of screen layer will not change, therefore the change of the electrode potential will not be to another electrode
Current potential impacts or influenceed the very little become.Therefore, the screen layer of the embodiment of the present invention can greatly reduce two electrodes it
Between coupled capacitor, both reduced the waste of electric energy, and can is enough effectively prevented from the generation of crosstalk phenomenon between two electrodes.
Because screen layer can greatly reduce the coupled capacitor between two electrodes, so without between two electrodes of increase
Distance, also therefore it will not reduce the transmitance of array base palte.Additionally, due to without increasing the distance between two electrodes, so this
The technical scheme of inventive embodiments is also applied for high-resolution array base palte, and it can either make array base palte keep high-resolution
Rate, while can also be effectively prevented from the generation of crosstalk phenomenon between two electrodes.
In order to further reduce influence of the current potential of first electrode layer to the current potential of the second electrode lay, generally increase is to first
The shielding surface of electrode layer.Preferably, array base palte as shown in Figure 1 b, the electrode dielectric layer 4 extend to described first
The top of electrode layer 2, and the screen layer 6 also extends into the top of the first electrode layer 2.The screen layer extends to described
The top of first electrode layer, such as can be surface, the electric field of top of first electrode layer can be greatly reduced to described
The influence of the second electrode lay, it can further reduce the coupled capacitor between first electrode layer and the second electrode lay.
In another embodiment of the present invention, array base palte as shown in Figure 1 d, the electrode dielectric layer 4 is also located at described first
The remote side 9 of the remote the second electrode lay 3 of electrode layer 2, and it also has been provided with ditch in the electrode dielectric layer on the remote side 9
Groove, the screen layer 6 are also located on the groove of the remote side 9 of the remote the second electrode lay 3 of the first electrode layer 2.
Or array base palte as shown in Figure 2 c, the electrode dielectric layer 4 are also located at the remote of the first electrode layer 2
The remote side 9 of the second electrode lay 3, and it also has been provided with groove, the screen layer in the electrode dielectric layer on the remote side 9
6 are also located on the groove of the remote side 9 of the remote the second electrode lay 3 of the first electrode layer 2.
Although the electric field of the remote side of the remote the second electrode lay of first electrode layer is to the shadow of the second electrode lay
Sound is relatively small, but can not ignore, so in order to further reduce between first electrode layer and the second electrode lay
Coupled capacitor, can the remote side of the remote the second electrode lay of the first electrode layer be also provided with screen layer.
In one embodiment of the invention, array base palte as illustrated in figure 1 c, the electrode dielectric layer 4 further extends into described
The remote side 9 of the remote the second electrode lay 3 of first electrode layer 2, and it also is provided with ditch in the electrode dielectric layer of the remote side
Groove, the screen layer 6 further extend into the groove of the remote side of the remote the second electrode lay 3 of the first electrode layer 2
On.
Or array base palte as shown in Figure 2 b, the electrode dielectric layer 4 further extend into the first electrode layer 2
The remote the second electrode lay 3 remote side 9, and also be provided with groove, the shielding in the electrode dielectric layer of the remote side
Layer 6 is further extended on the groove of the remote side of the remote the second electrode lay 3 of the first electrode layer 2.
If the first electrode layer is located at below the second electrode lay or set with the second electrode lay with layer
(such as：First electrode layer is source electrode layer, and the second electrode lay is pixel electrode layer, and source electrode layer is located under pixel electrode layer
Face or source electrode layer are set with pixel electrode layer with layer), the array base palte as shown in Fig. 1 c, 2b, the screen layer is further
Extend on the groove of the remote side of the remote the second electrode lay of the first electrode layer, refer to that the screen layer is located at institute
The close side of the close the second electrode lay of first electrode layer is stated, and extends to the surface of the first electrode layer, and is entered
One step extends to the remote side of the remote the second electrode lay of the first electrode layer.If the first electrode layer is located at institute
State above the second electrode lay or set with the second electrode lay with layer, the screen layer further extends into first electricity
On the groove of the remote side of the remote the second electrode lay of pole layer, refer to that the screen layer is located at leaning on for the first electrode layer
The close side of the nearly the second electrode lay, and extend to the underface of the first electrode layer, and further extend into described the
The remote side of the remote the second electrode lay of one electrode layer.So it is further to increase the area of screen layer, and reduces by the
The electric field of the top (or lower section) of one electrode layer and the remote side of the remote the second electrode lay of first electrode layer is to described
The influence of two electrode layers, it can further reduce the coupled capacitor between first electrode layer and the second electrode lay.
Certainly, in order to further reduce influence of the current potential of first electrode to the current potential of the second electrode lay, can also incite somebody to action
Screen layer is configured around first electrode.
In different embodiments, the first electrode layer and the second electrode lay can be different electrodes or other conduction knots
Structure.Can be specifically：The first electrode layer and the second electrode lay are source electrode layer and pixel electrode layer respectively, or gate electrode
Layer and pixel electrode layer, either data wire and pixel electrode layer or scan line and pixel electrode layer.Pixel electrode and other electricity
Screen layer is set between pole, can avoid producing coupled capacitor between pixel electrode and other electrodes, and then keep away pixel electrode
From the interference to other electrodes.Certainly, the first electrode layer and the second electrode lay can also be source electrode layer and public affairs respectively
Common electrode layer, or gate electrode layer and common electrode layer etc..
The shielding layer grounding, refer to that screen layer is connected by the wire with ground connection and be grounded.Embodiment can
So that shielding layer grounding wire in the manufacturing process of array base palte, is fabricated separately, but which is relatively complicated, and manufacture craft is multiple
It is miscellaneous, the space of array base palte is also occupied, influences transmitance etc..In order to simplify manufacture craft, the space profit of optimization array substrate
With improving transmitance etc., be generally attached screen layer and the existing earth lead of array base palte, such as：Including common electrical
In the array base palte of pole layer, by the screen layer by with the common electrode layer (such a situation, first electrode and second electrode
It is not public electrode) it is grounded.Screen layer is connected with common electrode layer, can shield source electrode and pixel electrode it
Between coupled capacitor, the coupled capacitor between gate electrode and pixel electrode, the coupled capacitor between data wire and pixel electrode or
Coupled capacitor between person's scan line and pixel electrode etc..
In one embodiment of the present invention, array base palte as shown in Figure 4, the first electrode layer is source electrode layer 10,
The second electrode lay is pixel electrode layer 11, and the electrode dielectric layer 4 is covered in the source electrode layer 10 and the common electrical
On pole layer 7, the pixel electrode layer 11 is located on the electrode dielectric layer 4；The groove 5 exposes the part public electrode
Layer 7, the screen layer 6 is grounded by being connected with the common electrode layer 7.
Fig. 3 is the top view of the array base palte shown in Fig. 4, and its pixel region is typically to be enclosed by grid line 12 and data wire 13
Into general source electrode layer 10 is in addition to including source electrode, in addition to drain electrode 14, and the drain electrode 14 connects with pixel electrode layer 11
Connect.
The screen layer, common electrode layer, pixel electrode layer are tin indium oxide (ITO), indium zinc oxide (IZO) or other are saturating
Prescribed electrode material, it can so improve the transmitance of array base palte.The pixel electrode layer can be dressing structure, finger
Deng advantageously forming fringe field.
Array base palte provided in an embodiment of the present invention is a kind of FFS types array base palte, in source electrode layer and pixel electrode layer
Between electrode dielectric layer in the screen layer that can shield coupled capacitor between two electrodes is set, when source electrode layer potential change
When, the electric capacity that source electrode layer is formed with screen layer is charged, due to shielding layer grounding, so the current potential of screen layer will not occur
Change, therefore the change of the electrode potential will not impact or influence the very little become to pixel electrode layer current potential.Therefore, originally
The screen layer of inventive embodiments can greatly reduce the coupled capacitor between source electrode layer and pixel electrode layer, both reduce electricity
The waste of energy, and can are enough effectively prevented from the generation of crosstalk phenomenon between two electrodes.
Because screen layer can greatly reduce the coupled capacitor between source electrode layer and pixel electrode layer, so without increasing
Therefore the distance of big source electrode layer and pixel electrode layer edge, also will not reduce the transmitance of array base palte.Additionally, due to not
With increase source electrode layer and pixel electrode layer edge distance, so the technical scheme of the embodiment of the present invention is also applied for high-resolution
The array base palte of rate, it can either make array base palte keep high-resolution, while can also be effectively prevented from source electrode layer and pixel
The generation of crosstalk phenomenon between electrode layer.
In another preferred embodiment of the present invention, array base palte as shown in Figure 5, the first electrode layer is source electrode layer
10, the second electrode lay is pixel electrode layer 11, and the electrode dielectric layer 4 is covered in the source electrode layer 10 and the pixel
On electrode layer 11, the common electrode layer 7 is located on the electrode dielectric layer 4；The groove 5 exposes the part common electrical
Pole layer 7, the screen layer 6 are grounded by being connected with the common electrode layer 7.
The screen layer, common electrode layer, pixel electrode layer are tin indium oxide (ITO), indium zinc oxide (IZO) or other are saturating
Prescribed electrode material, it can so improve the transmitance of array base palte.The pixel electrode can be dressing structure, finger
Deng advantageously forming fringe field.
The screen layer of the array base palte of the embodiment of the present invention greatly can reduce between source electrode layer and pixel electrode layer
Coupled capacitor, both reduced the waste of electric energy, and can is enough effectively prevented from the generation of crosstalk phenomenon between two electrodes, and this hair
The technical scheme of bright embodiment is also applied for high-resolution array base palte, and it can either make array base palte keep high-resolution,
The generation of crosstalk phenomenon between source electrode layer and pixel electrode layer can be also effectively prevented from simultaneously.
A kind of another preferred embodiment of the present invention, there is provided the display dress of array base palte comprising described in any of the above-described embodiment
Put.Coupled capacitor between two electrodes can be shielded by being set in the insulating barrier of the array base palte of the display device between electrodes
Screen layer, screen layer can greatly reduce the coupled capacitor between two electrodes, both reduce the waste of electric energy, and and can is enough effective
Ground avoids the generation of crosstalk phenomenon between two electrodes.And the technical scheme of the embodiment of the present invention is also applied for high-resolution array
The display device of substrate, it can either keep high-resolution, while can also be effectively prevented from the hair of crosstalk phenomenon between two electrodes
It is raw.
A kind of preparation method of array base palte is provided in one embodiment of the invention, the array base palte includes substrate, described
Preparation method includes：
S101, on the substrate deposition of first electrode film, the figure of first electrode layer is formed by patterning processes.
First electrode film can use Al, Cu, Mo or Cr monofilm, or any two kinds in Al, Cu, Mo, Cr or
The composite membrane of two or more compositions, it can specifically use the method for sputtering or thermal evaporation deposition film forming.First electrode can be source
Electrode, gate electrode, data wire or scan line etc..
S102, second electrode film is deposited on the substrate, the figure of the second electrode lay is formed by patterning processes.
Second electrode film can be tin indium oxide (ITO), indium zinc oxide (IZO) or other transparent electrode thin films, typically
Transparent conductive film can be deposited by the method for sputtering or thermal evaporation.Second electrode can be pixel electrode or public electrode
Deng.
S103, on the substrate depositing electrode insulating layer of thin-film, the figure of electrode dielectric layer is formed by patterning processes,
The electrode dielectric layer is provided with ditch between the first electrode layer and the second electrode lay in the electrode dielectric layer
Groove, the groove are located at the close side of the close the second electrode lay of the first electrode layer.
The electrode insulation layer film can deposit film forming by plasma enhanced chemical vapor deposition method, and electrode is exhausted
Edge layer film can select oxide, nitride or oxynitrides, and corresponding reacting gas can be SiH4、NH3、N2's
Mixed gas or SiH2Cl2、NH3、N2Mixed gas.
By step S101, S102, S103, first electrode layer, the second electrode lay and electrode dielectric layer are form respectively,
This does not limit step S101, S102, S103 sequencing.S101 can be first step, S103 be second step,
S102 is third step, such as：First electrode layer and the second electrode lay are respectively source electrode and pixel electrode, and source electrode and pixel
Electrode in same layer, then can not first pass through patterning processes and form source electrode, the depositing electrode on the substrate for forming active electrode
Insulating layer of thin-film, electrode dielectric layer, the pixel deposition electrode on the substrate formed with electrode dielectric layer are formed by patterning processes
Film, pixel electrode is formed by patterning processes.S101 and S102 can be to carry out simultaneously, then carry out S103 steps, such as：If
First electrode layer and the second electrode lay are respectively source electrode and pixel electrode, and source electrode and pixel electrode then may be used in same layer
To form source electrode and pixel electrode respectively by same patterning processes, sunk on the substrate for forming active electrode and pixel electrode
Product electrode insulation layer film, electrode dielectric layer is formed by patterning processes.S102 can be that first step, S103 are second step
Suddenly, S101 is third step, such as：First electrode layer and the second electrode lay are respectively source electrode and public electrode, then can first lead to
Cross patterning processes and form public electrode, the depositing electrode insulating layer of thin-film on the substrate formed with public electrode, pass through composition work
Skill forms electrode dielectric layer, the sedimentary origin electrode film on the substrate formed with electrode dielectric layer, source is formed by patterning processes
Electrode.
S104, the deposition shield layer film on the substrate formed with the electrode dielectric layer, formed and shielded by patterning processes
The figure of layer is covered, the screen layer is located in the groove, the screen layer and the first electrode layer and the second electrode
Layer insulation, and the shielding layer grounding.
The section of the groove can be V-shaped, U-shaped or T-shaped or other have the shape of phase same-action.Work as groove
For V-shaped or U-shaped when, screen layer can fill whole groove, can also only be covered in the side of groove, naturally it is also possible to only
It is covered in certain part of groove.
The material of shielding layer film can be the alloy of Cr, W, Ti, Ta, Mo, Al or Cu metal or conducting metal
Or metal oxide.Generally shielding layer film selection transparent electrode material, as tin indium oxide (ITO), indium zinc oxide (IZO) or its
His transparent electrode material, because transparent electrode material can improve the transmitance of array base palte.Shielding layer film, which can use, to be splashed
Penetrate or the method for thermal evaporation deposits film forming.
Array base palte provided in an embodiment of the present invention is a kind of preparation method of FFS types array base palte, in source electrode layer and
Setting can shield the screen layer of coupled capacitor between two electrodes in electrode dielectric layer between pixel electrode layer, and screen layer can
Greatly reduce the coupled capacitor between source electrode layer and pixel electrode layer, both reduce the waste of electric energy, and can is enough effectively
Avoid the generation of crosstalk phenomenon between two electrodes.And the technical scheme of the embodiment of the present invention is also applied for high-resolution array base
Plate, it can either make array base palte keep high-resolution, while can also be effectively prevented between source electrode layer and pixel electrode layer
The generation of crosstalk phenomenon.
In one embodiment of the present invention, in the preparation method of the array base palte, the first electrode layer is source electrode
Layer, the second electrode lay is pixel electrode layer；The preparation method also includes forming common electrode layer on the substrate, has
Body is：
S201, source electrode layer and common electrode layer are formed on the substrate.
The source electrode layer can use Al, Cu, Mo or Cr monofilm, or any two kinds in Al, Cu, Mo, Cr or
The composite membrane of two or more compositions, it can typically use the method for sputtering or thermal evaporation deposition film forming.The common electrode layer can
Think tin indium oxide (ITO), indium zinc oxide (IZO) or other transparent electrode materials, can so improve the transmission of array base palte
Rate.
S202, the depositing electrode insulating layer of thin-film on the substrate for forming active electrode layer and common electrode layer, pass through composition
Technique forms the figure of electrode dielectric layer, and the electrode dielectric layer is covered on the source electrode layer and the common electrode layer,
Groove is provided with the electrode dielectric layer, the groove exposes the part common electrode layer.
The electrode insulation layer film can deposit film forming by plasma enhanced chemical vapor deposition method, and electrode is exhausted
Edge layer film can select oxide, nitride or oxynitrides, and corresponding reacting gas can be SiH4、NH3、N2's
Mixed gas or SiH2Cl2、NH3、N2Mixed gas.
Source electrode layer on usual array base palte is provided with drain electrode, and the drain electrode passes through the via in electrode dielectric layer
It is connected with pixel electrode.In order to simplify manufacture craft, can the groove and the via in a patterning processes shape
Into.
S203, the deposition shield layer film on the substrate formed with the electrode dielectric layer, formed and shielded by patterning processes
The figure of layer is covered, the screen layer is located in the groove, the screen layer and the source electrode layer and the pixel electrode layer
Insulation, and the screen layer is grounded by being connected with the common electrode layer.
The material of shielding layer film can be the alloy of Cr, W, Ti, Ta, Mo, Al or Cu metal or conducting metal
Or metal oxide.Generally shielding layer film selection transparent electrode material, as tin indium oxide (ITO), indium zinc oxide (IZO) or its
His transparent electrode material, because transparent electrode material can improve the transmitance of array base palte.Shielding layer film, which can use, to be splashed
Penetrate or the method for thermal evaporation deposits film forming.
Screen layer is connected with common electrode layer, can shield the coupled capacitor between source electrode and pixel electrode, meanwhile, screen
The step of shielding layer grounding wire is fabricated separately can be saved by covering layer and being connected with common electrode layer, make the manufacture craft of array base palte
More simplify, the problems such as it also avoid taking the space of array base palte because making shielding layer grounding wire.
S204, the pixel electrode layer is formed on the substrate formed with the electrode dielectric layer.
The pixel electrode layer can be tin indium oxide (ITO), indium zinc oxide (IZO) or other transparent electrode thin films, have
Body can deposit transparent conductive film by the method for sputtering or thermal evaporation.
The Making programme of the embodiment of the present invention can be S201, S202, S203, S204 carry out successively or S201,
S202, S204, S203 are carried out successively, are forming not limiting sequentially for screen layer and pixel electrode layer.Generally for simplification
Manufacture craft, screen layer and pixel electrode layer can be formed simultaneously, be to be formed in a patterning processes.Specifically can be with
It is depositing indium tin oxide (ITO), indium zinc oxide (IZO) or other transparent electricity on the substrate formed with the electrode dielectric layer
Very thin films, screen layer and pixel electrode layer are formed by a patterning processes.The step of etching of the patterning processes, make shielding
Electrode film between layer and pixel electrode layer is carved, so that the two insulate.
Array base palte provided in an embodiment of the present invention is a kind of preparation method of FFS types array base palte, in source electrode layer and
Setting can shield the screen layer of coupled capacitor between two electrodes in electrode dielectric layer between pixel electrode layer, and screen layer can
Greatly reduce the coupled capacitor between source electrode layer and pixel electrode layer, both reduce the waste of electric energy, and can is enough effectively
Avoid the generation of crosstalk phenomenon between two electrodes.And the technical scheme of the embodiment of the present invention is also applied for high-resolution array base
Plate, it can either make array base palte keep high-resolution, while can also be effectively prevented between source electrode layer and pixel electrode layer
The generation of crosstalk phenomenon.
In another preferred embodiment of the present invention, the preparation method of the array base palte also includes：
S301, source electrode layer and pixel electrode layer are formed on the substrate.
The pixel electrode layer can be tin indium oxide (ITO), indium zinc oxide (IZO) or other transparent electrode thin films, have
Body can deposit transparent conductive film by the method for sputtering or thermal evaporation.
S302, the depositing electrode insulating layer of thin-film on the substrate for forming active electrode layer and pixel electrode layer, pass through composition
Technique forms the figure of electrode dielectric layer, and the electrode dielectric layer is covered on the source electrode layer and the pixel electrode layer,
Groove is provided with the electrode dielectric layer.
The electrode insulation layer film can deposit film forming by plasma enhanced chemical vapor deposition method, and electrode is exhausted
Edge layer film can select oxide, nitride or oxynitrides, and corresponding reacting gas can be SiH4、NH3、N2's
Mixed gas or SiH2Cl2、NH3、N2Mixed gas.
Source electrode layer on usual array base palte is provided with drain electrode, and the drain electrode passes through the via in electrode dielectric layer
It is connected with pixel electrode.In order to simplify manufacture craft, can the groove and the via in a patterning processes shape
Into.
S303, the common electrode layer is formed on the substrate formed with the electrode dielectric layer.
The common electrode layer is tin indium oxide (ITO), indium zinc oxide (IZO) or other transparent electrode materials, so may be used
To improve the transmitance of array base palte.
S304, the deposition shield layer film on the substrate formed with the electrode dielectric layer, formed and shielded by patterning processes
The figure of layer is covered, the screen layer is located in the groove, the screen layer and the source electrode layer and the pixel electrode layer
Insulation, and the screen layer is grounded by being connected with the common electrode layer.
Screen layer is connected with common electrode layer, can shield the coupled capacitor between source electrode and pixel electrode, meanwhile, screen
The step of shielding layer grounding wire is fabricated separately can be saved by covering layer and being connected with common electrode layer, make the manufacture craft of array base palte
More simplify, the problems such as it also avoid taking the space of array base palte because making shielding layer grounding wire.
The Making programme of the embodiment of the present invention can be S301, S302, S303, S304 carry out successively or S301,
S302, S304, S303 are carried out successively, are forming not limiting sequentially for screen layer and common electrode layer.Generally for simplification
Manufacture craft, screen layer and common electrode layer can be formed simultaneously, be to be formed in a patterning processes.Specifically can be with
It is depositing indium tin oxide (ITO), indium zinc oxide (IZO) or other transparent electricity on the substrate formed with the electrode dielectric layer
Very thin films, screen layer and common electrode layer are formed by a patterning processes.
Array base palte provided in an embodiment of the present invention is the preparation method of another FFS types array base palte, in source electrode layer
Setting can shield the screen layer of coupled capacitor between two electrodes, screen layer energy in electrode dielectric layer between pixel electrode layer
Enough coupled capacitors greatly reduced between source electrode layer and pixel electrode layer, had both reduced the waste of electric energy, and can is enough effective
Ground avoids the generation of crosstalk phenomenon between two electrodes.And the technical scheme of the embodiment of the present invention is also applied for high-resolution array
Substrate, it can either make array base palte keep high-resolution, at the same can also be effectively prevented from source electrode layer and pixel electrode layer it
Between crosstalk phenomenon generation.
The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, change or replacement can be readily occurred in, should all be contained
Cover within protection scope of the present invention.Therefore, protection scope of the present invention described should be defined by scope of the claims.
Claims (6)
1. a kind of array base palte, including substrate, the substrate is provided with first electrode layer and the second electrode lay, the first electrode
Electrode dielectric layer is provided between layer and the second electrode lay, it is characterised in that groove is provided with the electrode dielectric layer, it is described
Groove is located at the close side of the close the second electrode lay of the first electrode layer, and the groove is described provided with that can shield
The screen layer of coupled capacitor between first electrode layer and the second electrode lay, the screen layer and the first electrode layer and institute
State the second electrode lay insulation, and the shielding layer grounding；
The array base palte also includes common electrode layer, and the screen layer is grounded by being connected with the common electrode layer；
The first electrode layer is source electrode layer, and the second electrode lay is pixel electrode layer, and the electrode dielectric layer is covered in
On the source electrode layer and the common electrode layer, the pixel electrode layer is located on the electrode dielectric layer；The groove is sudden and violent
Common electrode layer described in exposed portion.
2. array base palte according to claim 1, it is characterised in that the electrode dielectric layer extends to the first electrode
The top of layer, and the screen layer also extends into the top of the first electrode layer.
3. array base palte according to claim 2, it is characterised in that the electrode dielectric layer further extends into described
The remote side of the remote the second electrode lay of one electrode layer, and groove also is provided with the electrode dielectric layer of the remote side, institute
State screen layer further extend into the first electrode layer the remote the second electrode lay remote side groove on.
4. array base palte according to claim 1, it is characterised in that the electrode dielectric layer is also located at the first electrode
The remote side of the remote the second electrode lay of layer, and it also is provided with groove, the shielding in the electrode dielectric layer of the remote side
Layer is also located on the groove of the remote side of the remote the second electrode lay of the first electrode layer.
5. a kind of display device, it is characterised in that include the array base palte any one of claim 1-4.
6. a kind of preparation method of array base palte, including：
The deposition of first electrode film on substrate, the figure of first electrode layer is formed by patterning processes；
Second electrode film is deposited on the substrate, and the figure of the second electrode lay is formed by patterning processes；
Depositing electrode insulating layer of thin-film on the substrate, the figure of electrode dielectric layer, the electrode are formed by patterning processes
Insulating barrier is provided with groove, the ditch between the first electrode layer and the second electrode lay in the electrode dielectric layer
Groove is located at the close side of the close the second electrode lay of the first electrode layer；
The deposition shield layer film on the substrate formed with the electrode dielectric layer, the figure of screen layer is formed by patterning processes
Shape, the screen layer are located in the groove, and the screen layer insulate with the first electrode layer and the second electrode lay, and
The shielding layer grounding；
The first electrode layer is source electrode layer, and the second electrode lay is pixel electrode layer；The preparation method is additionally included in
Common electrode layer is formed on the substrate, is specially：
Source electrode layer and common electrode layer are formed on the substrate；
The depositing electrode insulating layer of thin-film on the substrate for forming active electrode layer and common electrode layer, electricity is formed by patterning processes
The figure of pole insulating barrier, the electrode dielectric layer are covered on the source electrode layer and the common electrode layer, and the electrode is exhausted
Groove is provided with edge layer, the groove exposes the part common electrode layer；
The deposition shield layer film on the substrate formed with the electrode dielectric layer, the figure of screen layer is formed by patterning processes
Shape, the screen layer are located in the groove, and the screen layer insulate with the source electrode layer and the pixel electrode layer, and institute
Screen layer is stated to be grounded by being connected with the common electrode layer；
The pixel electrode layer is formed on the substrate formed with the electrode dielectric layer.
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| CN104269416A (en) * | 2014-09-26 | 2015-01-07 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method and display device of array substrate |
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| CN104269416A (en) * | 2014-09-26 | 2015-01-07 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method and display device of array substrate |
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