CN104733375B - The production method of damascene structure - Google Patents
The production method of damascene structure Download PDFInfo
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- CN104733375B CN104733375B CN201310713317.5A CN201310713317A CN104733375B CN 104733375 B CN104733375 B CN 104733375B CN 201310713317 A CN201310713317 A CN 201310713317A CN 104733375 B CN104733375 B CN 104733375B
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Abstract
A kind of production method of damascene structure, including:Substrate is provided, dielectric layer and titanium nitride layer are sequentially formed in the substrate, there is conductive layer in the substrate；The titanium nitride layer is etched, forms opening in the titanium nitride layer, opening exposes the surface of dielectric layer, and the opening is located above the conductive layer；Along the dielectric layer of opening etched portions thickness, groove is formed in the dielectric layer；After the groove is formed, anneal to the substrate；After an annealing process, the dielectric layer of the channel bottom is performed etching, forms through-hole in the dielectric layer of channel bottom, the through-hole exposes the conductive layer of lower section, and the through-hole and groove constitute damascene structure.The present invention anneals to substrate after groove is formed so that the stress of entire semiconductor structure is in balance again, improves the uniformity and process window of technique.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, the more particularly to production method of damascene structure.
Background technology
With the development of semiconductor technology, the integrated level of VLSI chip has been up to several hundred million or even tens
The wiring of the scale of a device, large scale integrated circuit is increasingly complex, and two layers or more of multilevel metal interconnection structure is widely used.
First groove through-hole again may be used as a kind of interconnection structure in damascene structure（Trench First Via Last）Skill
Art makes, and specifically, please refers to Fig.1-the cross-sectional view of preparation method of existing damascene structure shown in Fig. 4.
First, referring to FIG. 1, providing substrate 10, there is conductive layer 20 in the substrate 10, shape successively in the substrate 10
The surface of the conductive layer 20 is covered at having dielectric layer 30 and titanium nitride layer 40, the dielectric layer 30.
Then, it continues to refer to figure 1, forms the first photoresist layer 50, first photoresist on the titanium nitride layer 40
The first opening is formed in layer 50, first opening is positioned at the top of conductive layer 20.
Then, referring to FIG. 2, with first photoresist layer 50（Incorporated by reference to Fig. 1）For mask, to the titanium nitride layer 40
It performs etching, forms opening in the titanium nitride layer 40, for the opening positioned at the top of the conductive layer 20, the opening is fixed
The shape for the groove that justice is subsequently formed in dielectric layer 30 and position.
Then, it is then mask with the titanium nitride layer 40 with continued reference to FIG. 2, removing the first photoresist layer 50 first,
The dielectric layer 30 is performed etching along the opening, forms groove in the dielectric layer 30, the groove is located at conductive layer
20 tops.
Then, referring to FIG. 3, forming the second photoresist layer 60 on the titanium nitride layer 40, second photoresist layer
There is the second opening, second opening to cover the titanium nitride layer 40 and partial groove, second opening is fixed in 60
The shape of the follow-up through-hole to be formed of justice and position.
Then, referring to FIG. 4, being mask with second photoresist 60, along second opening to the dielectric layer 30
Technique is performed etching, forms through-hole in the dielectric layer 30, the through-hole exposes the conductive layer 20 of lower section, the through-hole and ditch
Slot constitutes damascene structure.
In practice, it has been found that using the bad appearance of prior art substrate in through-hole manufacturing process, photoetching process it is equal
Even property and process window are required for further increasing.
Invention content
Problems solved by the invention is how to improve the uniformity for making the technique during damascene structure.
To solve the above problems, the present invention provides a kind of production method of damascene structure, including：Substrate, institute are provided
It states and is sequentially formed with dielectric layer and titanium nitride layer in substrate, there is conductive layer in the substrate；The titanium nitride layer is etched, in institute
It states and forms opening in titanium nitride layer, opening exposes the surface of dielectric layer, and the opening is located above the conductive layer；Along opening
The dielectric layer of etched portions thickness forms groove in the dielectric layer；After the groove is formed, the substrate is moved back
Fire；After an annealing process, the dielectric layer of the channel bottom is performed etching, through-hole is formed in the dielectric layer of channel bottom,
The through-hole exposes the conductive layer of lower section, and the through-hole and groove constitute damascene structure.
Optionally, the annealing is carried out using baking annealing, furnace anneal or laser annealing technique.
Optionally, the temperature range of the furnace anneal is 100-500 degrees Celsius.
Optionally, the temperature range of the baking annealing process is 100-500 degrees Celsius, the time model of the baking annealing
Enclose is 60-100 seconds.
Optionally, the wave-length coverage of the laser annealing is 0.5-20 microns, and laser annealing uses scan pattern or flicker
Pattern carries out.
Optionally, it is cooled down after annealing, cooling temperature is 21-25 degrees Celsius, and cooling time is 30-100 seconds.
Optionally, the thickness range of the titanium nitride layer is 200-500 angstroms.
Optionally, the thickness range of the dielectric layer is 2000-3000 angstroms.
Optionally, the process for opening being formed in the titanium nitride layer is：The first photoresist is formed on the titanium nitride layer
Layer, there is the first opening for exposing titanium nitride layer surface in first photoresist layer；The nitridation is etched along the first opening
Titanium layer forms opening in titanium nitride layer.
Optionally, after formation of the groove, first photoresist layer is removed.
Optionally, the forming process of the through-hole is：After annealing, the second photoresist for covering the titanium nitride layer is formed
Layer, there is the second opening of the dielectric layer for exposing channel bottom in second photoresist layer；Along the second opening etching groove
The dielectric layer of bottom, forms through-hole in the dielectric layer.
Optionally, further include：Full metal is filled in groove and through-hole, forms interconnection structure.
Compared with prior art, technical scheme of the present invention has the following advantages：
The forming method of the damascene structure of the present invention is etching the titanium nitride layer, the shape in the titanium nitride layer
At opening, opening exposes the surface of dielectric layer, and the opening is located above the conductive layer, then thick along opening etched portions
The dielectric layer of degree, after forming groove in the dielectric layer, the original stress equilibrium state in entire semiconductor structure is broken, in shape
It after groove, anneals to substrate so that the stress in the entire semiconductor structure formed after opening and groove is attributed to again
Balance, prevents the warpage of substrate before forming through-hole so that the through-hole that channel bottom is formed has preferable pattern, improves
The process window of lithography and etching technique.
Further, the temperature range of furnace anneal is 100-500 degrees Celsius, and the temperature range of the baking annealing process is
100-500 degrees Celsius, the time range of the baking annealing is 60-100 seconds, and the wave-length coverage of the laser annealing is 0.5-20
Micron, laser annealing are carried out using scan pattern or flash pattern, are cooled down after annealing, and cooling temperature is 21-25 degrees Celsius,
Cooling time is 30-100 seconds so that the effect of stress equilibrium is preferable.
Description of the drawings
The cross-sectional view of preparation method of Fig. 1~existing damascene structure shown in Fig. 4；
Fig. 5~Fig. 8 is the cross-sectional view of the manufacturing process of the damascene structure of one embodiment of the invention.
Specific implementation mode
The prior art finds the bad appearance of substrate, and the uniformity and work of photoetching process during via etch
Skill window needs to be further increased.The study found that conductive layer（Such as the metals such as copper）Generally there is compression stress, on the electrically conductive
Dielectric layer is formed, then forms titanium nitride layer on dielectric layer, titanium nitride layer has tensile stress, the stretching that titanium nitride layer generates
Stress can offset the compression stress generated in conductive layer and/or dielectric layer so that total is in original stress equilibrium state, still
It is formed in opening and/or dielectric layer in titanium nitride layer after forming groove, substrate makes the original stress equilibrium state quilt of total
Break, total will present single compression stress, so that warpage can occur for substrate, which not only influences in substrate
Structure pattern, can also influence subsequent process steps（Such as via etch）Process uniformity, and influence subsequent technique
The process window of step.
For this purpose, the present invention proposes a kind of production method of damascene structure, including：Substrate is provided, in the substrate
It is sequentially formed with dielectric layer and titanium nitride layer, there is conductive layer in the substrate；The titanium nitride layer is etched, in the titanium nitride
Opening is formed in layer, opening exposes the surface of dielectric layer, and the opening is located above the conductive layer；Along opening etched portions
The dielectric layer of thickness forms groove in the dielectric layer；After the groove is formed, anneal to the substrate；It is moving back
After ignition technique, the dielectric layer of the channel bottom is performed etching, forms through-hole, the through-hole in the dielectric layer of channel bottom
Expose the conductive layer of lower section, the through-hole and groove constitute damascene structure.Before via etch step, substrate is carried out
Annealing so that the stress equilibrium being broken in entire semiconductor structure is attributed to balance, improves the pattern of substrate, prevent again
The warpage of semiconductor substrate when via etch is conducive to the uniformity of photoetching process and the improvement of process window.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.When describing the embodiments of the present invention, for purposes of illustration only, schematic diagram can disobey general proportion
Make partial enlargement, and the schematic diagram is example, should not limit the scope of the invention herein.In addition, in reality
In making should include length, width and depth three-dimensional space.
Fig. 5~Fig. 8 is the cross-sectional view of the manufacturing process of the damascene structure of one embodiment of the invention.
First, incorporated by reference to Fig. 5, substrate 100 is provided, dielectric layer 300 and titanium nitride layer are sequentially formed in the substrate 100
400, there is in the substrate 100 conductive layer 200.The material of the substrate 100 is silicon.
The substrate 100 includes semiconductor substrate and the underlying dielectric layer in semiconductor substrate, the semiconductor lining
Several semiconductor devices can be formed in bottom, conductive layer 200 is formed in the underlying dielectric layer, and the material of conductive layer 200 is
The metals such as copper, aluminium or tungsten.
The material of semiconductor substrate can be with silicon（Si）, germanium（Ge）Or SiGe（GeSi）, silicon carbide（SiC）；Can also be
Silicon-on-insulator（SOI）, germanium on insulator（GOI）；Or can also be III-V races such as other materials, such as GaAs
Close object.
The material of the dielectric layer 300 is silica etc., and thickness range is 2000-3000 angstroms.The titanium nitride layer 400
Thickness range be 200-500 angstroms.The stress of the semiconductor structure formed at this time is in equilibrium state, i.e. substrate 100 will not be sent out
Raw warpage.The semiconductor structure includes substrate 100, the conductive layer 200 in substrate 100, the medium in substrate 100
Layer 300, the titanium nitride layer 400 on dielectric layer 300.
Then, continuing in conjunction with Fig. 5, the first photoresist layer 500, first light are formed on the titanium nitride layer 400
The first opening is formed in photoresist layer 500, first opening is located at 200 top of the conductive layer, and first opening is used for
Define the shape of opening to be formed and position subsequently in titanium nitride layer 400.
Then, continuing in conjunction with Fig. 5, technique is performed etching to the titanium nitride layer 400 along first opening, described
Opening is formed in titanium nitride layer 400, the opening is located at 200 top of the conductive layer.The opening subsequently will be for defining
The shape of the groove formed in the dielectric layer 300 and position.
Then, referring to FIG. 6, removing first photoresist layer 500（In conjunction with Fig. 5）, with the opening for mask, to institute
It states dielectric layer 300 and performs etching technique, form groove in the dielectric layer 300, the groove is located at 200 top of conductive layer.
After forming opening in titanium nitride layer 400 and forming groove in dielectric layer 300, the semiconductor structure is answered
Dynamic balance state is broken so that semiconductor structure shows single compression stress so that warpage can occur for substrate, follow-up straight
Connect the bad appearance to form the second photoresist layer（When basement warping, the temperature not military training when heat in coating technique is dried in substrate
So that the uniformity of the thickness of the second photoresist layer formed is deteriorated）, formed in the second photoresist layer by exposed and developed
Second opening pattern can be deteriorated, to influence channel bottom formation through-hole pattern.
In other embodiments of the invention, the removal of first photoresist layer can also be after being subsequently formed groove
Removal, to during etch nitride titanium is formed and is open, ensure that the thickness of titanium nitride layer will not change too much, to
So that the tensile stress in titanium nitride layer will not reduce it is too many, can be easily so that integrating semiconductor subsequently through annealing
The stress of structure is attributed to equilibrium state again.Stress rebalances：Compression stress in semiconductor structure and tensile stress
The tensile stress or compression stress of very little is presented in counteracting or entire semiconductor structure.
Then, it with continued reference to FIG. 6, after the groove is formed, anneals to the substrate 100.
In the present embodiment, after the trenches are formed, is formed before the second photoresist layer, annealed to substrate so that half
Stress in conductor structure is in equilibrium state again, it is therefore prevented that the warpage of substrate 100 so that the second photoresist being subsequently formed
Layer has good pattern, is conducive to the improvement of the process uniformity and process window of subsequent processing step, to through-hole light
The pattern of substrate after quarter, via etch has improvement result.
The annealing can utilize baking annealing（bake anneal）, furnace anneal (furnace anneal) or swash
Photo-annealing (laser anneal) technique carries out.As an embodiment of the present invention, the annealing is carried out using boiler tube, described
The temperature range of annealing is 100-500 degrees Celsius.As another embodiment of the present invention, the annealing process utilizes baking process
It carries out, the temperature range of the baking process is 100-500 degrees Celsius, and the time range of the baking process is 60-100 seconds.
Another as the present invention applies example, and the annealing process is carried out using laser annealing technique, the wave-length coverage of the laser annealing
It it is 0.5-20 microns, laser annealing is carried out using scan pattern (scan mode) or flash pattern (splash mode).In order to
The stress of entire semiconductor structure is more preferably set to be in equilibrium state, the cooling temperature after annealing is 21-25 degrees Celsius, cooling time
It is 30-100 seconds.
Then, referring to FIG. 7, after an annealing process, the second light is formed on the titanium nitride layer 400 and dielectric layer 300
Photoresist layer 600 has the second opening, groove of second opening positioned at dielectric layer 300 in second photoresist layer 600
Interior, second opening defines the shape of through-hole to be formed and position subsequently in dielectric layer 300.
Due to the second photoresist layer 600 formation before, dielectric layer 300, titanium nitride layer 400 to substrate 100 and its top
It is annealed so that the stress of entire semiconductor structure is in equilibrium state, therefore, when forming the second photoresist layer 300,
Warpage will not occur for substrate 100, and when coating process forms the second photoresist layer 600, the second photoresist layer 600 is heated relatively more equal
It is even, make the second photoresist layer to be formed that there is good thickness evenness, thus form the second photoresist layer 600 and in the second light
The window of photoetching process that the second opening is formed in photoresist layer 600 becomes larger, the pattern of the second photoresist layer 600 of formation and uniformly
Property have larger improvement, formed in the second photoresist layer 600 second opening have with preferable pattern, be more advantageous to subsequently
Via etch process progress.
Then, referring to FIG. 8, being mask with second photoresist layer 600, along second opening to the dielectric layer
300 perform etching technique, through-hole are formed in the dielectric layer 300, the through-hole exposes the conductive layer 200 of lower section, described logical
Hole and groove constitute damascene structure.
Full metal is filled subsequently in damascene structure forms interconnection structure.
To sum up, the production method of damascene structure provided by the invention after formation of the groove anneals to substrate,
So that the stress in the entire semiconductor structure formed after opening and groove is attributed to balance again, base is prevented before forming through-hole
The warpage at bottom so that the through-hole that channel bottom is formed has preferable pattern, improves the process window of lithography and etching technique.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (12)
1. a kind of production method of damascene structure, which is characterized in that including：
Semiconductor structure is provided, the semiconductor structure includes substrate, the conductive layer in substrate, the medium in substrate
Layer, the titanium nitride layer on dielectric layer, the tensile stress that titanium nitride layer generates, which can be offset in conductive layer and/or dielectric layer, to be generated
Compression stress so that the stress of the semiconductor structure is in equilibrium state；
The titanium nitride layer is etched, forms opening in the titanium nitride layer, opening exposes the surface of dielectric layer, the opening
Above the conductive layer；
Along the dielectric layer of opening etched portions thickness, groove is formed in the dielectric layer, after forming groove, the semiconductor junction
The original stress equilibrium state of structure is broken so that semiconductor structure shows single compression stress；
It after the groove is formed, anneals to the substrate so that the stress in semiconductor structure is in equilibrium-like again
State；
After an annealing process, the dielectric layer of the channel bottom is performed etching, through-hole is formed in the dielectric layer of channel bottom,
The through-hole exposes the conductive layer of lower section, and the through-hole and groove constitute damascene structure.
2. the production method of damascene structure as described in claim 1, which is characterized in that the annealing is moved back using baking
Fire, furnace anneal or laser annealing technique carry out.
3. the production method of damascene structure as claimed in claim 2, which is characterized in that the temperature model of the furnace anneal
Enclose is 100-500 degrees Celsius.
4. the production method of damascene structure as claimed in claim 2, which is characterized in that the temperature of the baking annealing process
The time range of ranging from 100-500 degrees Celsius of degree, the baking annealing is 60-100 seconds.
5. the production method of damascene structure as claimed in claim 2, which is characterized in that the wavelength model of the laser annealing
It is 0.5-20 microns to enclose, and laser annealing is carried out using scan pattern or flash pattern.
6. such as the production method of claim 3-5 any one of them damascene structures, which is characterized in that carried out after annealing cold
But, cooling temperature is 21-25 degrees Celsius, and cooling time is 30-100 seconds.
7. the production method of damascene structure as described in claim 1, which is characterized in that the thickness model of the titanium nitride layer
Enclose is 200-500 angstroms.
8. the production method of damascene structure as described in claim 1, which is characterized in that the thickness range of the dielectric layer
It is 2000-3000 angstroms.
9. the production method of damascene structure as described in claim 1, which is characterized in that formed and opened in the titanium nitride layer
Mouthful process be：The first photoresist layer is formed on the titanium nitride layer, is had in first photoresist layer and is exposed nitridation
First opening on titanium layer surface；The titanium nitride layer is etched along the first opening, forms opening in titanium nitride layer.
10. the production method of damascene structure as claimed in claim 9, which is characterized in that after formation of the groove, remove institute
State the first photoresist layer.
11. the production method of damascene structure as described in claim 1, which is characterized in that the forming process of the through-hole
For：After annealing, the second photoresist layer for covering the titanium nitride layer is formed, has in second photoresist layer and exposes ditch
Second opening of the dielectric layer of trench bottom；Dielectric layer along the second opening etching groove bottom, forms through-hole in the dielectric layer.
12. the production method of damascene structure as described in claim 1, which is characterized in that further include：In groove and through-hole
The middle full metal of filling, forms interconnection structure.
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| CN104733375B true CN104733375B (en) | 2018-08-10 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6017817A (en) * | 1999-05-10 | 2000-01-25 | United Microelectronics Corp. | Method of fabricating dual damascene |
| US6313007B1 (en) * | 2000-06-07 | 2001-11-06 | Agere Systems Guardian Corp. | Semiconductor device, trench isolation structure and methods of formations |
| CN1450621A (en) * | 2002-04-09 | 2003-10-22 | 旺宏电子股份有限公司 | Method for eliminating stress and damage while forming isolation component |
| CN101226895A (en) * | 2007-12-21 | 2008-07-23 | 上海宏力半导体制造有限公司 | Method for manufacturing shallow groove isolation structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW483104B (en) * | 2001-01-10 | 2002-04-11 | Macronix Int Co Ltd | Dual damascene manufacturing method using photoresist top surface image method to improve trench first |
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2013
- 2013-12-20 CN CN201310713317.5A patent/CN104733375B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6017817A (en) * | 1999-05-10 | 2000-01-25 | United Microelectronics Corp. | Method of fabricating dual damascene |
| US6313007B1 (en) * | 2000-06-07 | 2001-11-06 | Agere Systems Guardian Corp. | Semiconductor device, trench isolation structure and methods of formations |
| CN1450621A (en) * | 2002-04-09 | 2003-10-22 | 旺宏电子股份有限公司 | Method for eliminating stress and damage while forming isolation component |
| CN101226895A (en) * | 2007-12-21 | 2008-07-23 | 上海宏力半导体制造有限公司 | Method for manufacturing shallow groove isolation structure |
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