CN104733319A - MOS transistor structure and manufacturing method thereof - Google Patents

Abstract

The invention provides a method for manufacturing a MOS transistor, comprising: a. providing a semiconductor substrate and a dummy gate stack; b. forming and depositing first spacer parts on both sides of the dummy gate stack; c. Depositing the first sidewall portion perpendicular to the surface of the substrate to form a second sidewall portion; d. removing the first sidewall portion located on the top of the dummy gate stack and the second sidewall located on the source-drain extension region part of the outer part to form sidewalls; e. form source and drain regions in the substrate on both sides of the dummy gate stack, and form an interlayer dielectric layer; f. remove the dummy gate stack to form an opening, and fill the gate stack at this position in the opening; g. remove the spacer to form a vacancy; h. deposit a sacrificial material layer on the interlayer dielectric layer and the dummy gate stack to fill the top of the vacancy, and Chemical mechanical polishing is performed until the top of the gate stack is exposed. Compared with the prior art, the invention effectively reduces the gate parasitic capacitance and improves the device performance.

Description

A kind of MOS transistor structure and manufacturing method thereof

technical field

The present invention relates to a semiconductor device structure and a manufacturing method thereof, in particular to a MOS transistor structure and a manufacturing method thereof.

technical background

In the MOSFET structure, the gate parasitic capacitance is a key factor affecting the frequency response and switching speed of the device, and determines the gate RC delay and RF frequency response. In order to improve the performance of the device, we need to reduce the parasitic capacitance of the MOSFET as much as possible. As the size of the device decreases, the influence of the parasitic capacitance becomes more and more significant. Further reducing the parasitic capacitance of the device can significantly improve the performance of the device.

Parasitic capacitance is directly determined by the physical structure of the device, and its size is directly related to the size of the device. As shown in FIG. 1 , the gate parasitic capacitance mainly includes three parts: the inner edge parasitic capacitance C _if , the outer edge parasitic capacitance C _of and the overlapping parasitic capacitance C _ov . Among them, the parasitic capacitance C _of the outer edge is the most important part of the parasitic capacitance of the gate, and its size is closely related to the length of the gate, the height of the gate and the filling material between the gate and the source and drain. Due to many limitations, for a device of a specific size, the gate length and gate height cannot be further reduced, and the change of the device structure will also cause many other negative effects, and it is difficult to further reduce the parasitic capacitance of the device.

Based on this problem, the present invention provides a new type of semiconductor structure. After forming the interlayer dielectric layer, the spacer is etched away, and vacancies are formed in the interlayer dielectric layer above the gate and source and drain regions, and the previous space is replaced by air. The sidewall material effectively reduces the dielectric constant of the material in the outer edge region, and at the same time weakens the capacitive coupling effect between the source-drain region and the gate, thereby effectively reducing the parasitic capacitance and optimizing device performance.

Contents of the invention

The invention provides a MOS transistor structure and a manufacturing method thereof, which reduce parasitic capacitance and optimize device performance. Specifically, the manufacturing method provided by the invention comprises the following steps:

a. providing a semiconductor substrate and a dummy gate stack, with source and drain extension regions in the substrate on both sides of the dummy gate stack;

b. forming and depositing first spacer parts on both sides of the dummy gate stack;

c. forming a second sidewall portion on the surface of the deposited first sidewall portion perpendicular to the substrate;

d. removing the part of the first sidewall part located on the top of the dummy gate stack and the part outside the second sidewall part on the source-drain extension region to form a sidewall;

e. forming source and drain regions in the substrate on both sides of the dummy gate stack, and forming an interlayer dielectric layer above the source and drain regions;

f. removing the dummy gate stack to form an opening, and filling the gate stack in and in the opening;

g. removing the side wall to form a void;

h. Depositing a sacrificial material layer on the interlayer dielectric layer and the dummy gate stack, and performing chemical mechanical polishing until the top of the gate stack is exposed.

Wherein, in step b, the material of the first sidewall part is silicon nitride.

Wherein, in step b, the thickness of the first sidewall portion is 10-30 nm.

Wherein, in step c, the material of the second side wall part is the same as that of the second side wall part.

Wherein, in step d, the method for removing the first sidewall portion is anisotropic etching.

Wherein, in step d, the material of the interlayer dielectric layer is different from that of the sidewall.

Wherein, in step d, the material of the interlayer dielectric layer is silicon oxide.

Wherein, in step g, the method for removing the sidewall is selective etching.

Wherein, in step h, the material of the sacrificial material layer is the same as that of the interlayer dielectric layer.

Correspondingly, the present invention also provides a MOS transistor structure, including:

Substrate;

a gate stack overlying the substrate;

source and drain regions located in the substrates on both sides of the gate stack;

an interlayer dielectric layer covering the source and drain regions;

vacancies, located on both sides of the gate stack, surrounded by the interlayer dielectric layer and the substrate; and

A cover layer covering the top of the void.

Wherein, the surface of the vacancy adjacent to the interlayer dielectric layer is arc-shaped, and the width of the top is smaller than the width of the bottom.

Wherein, the width of the top of the vacancy is 10-30 nm, and the width difference between the top and the bottom is 30-60 nm.

Wherein, the thickness is less than 5nm.

According to the MOS transistor structure provided by the present invention, after the interlayer dielectric layer is formed, the sidewall is etched away, vacancies are formed in the interlayer dielectric layer above the gate and the source and drain regions, and the previous sidewall material is replaced with air, effectively The dielectric constant of the material in the outer edge region is reduced, and at the same time, the capacitive coupling effect between the source drain region and the gate is weakened, thereby effectively reducing parasitic capacitance and optimizing device performance.

Description of drawings

Other characteristics, objects and advantages of the present invention will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

FIG. 1 is a schematic diagram of the gate parasitic capacitance of a MOS device;

2 to 12 are cross-sectional views of various manufacturing stages of a MOS device according to a specific embodiment of the present invention.

The same or similar reference numerals in the drawings represent the same or similar components.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

Referring to FIG. 12 , the present invention provides a MOS transistor structure, including: a substrate 100 ; a gate stack 200 located above the substrate 100 ; vacancies 106 located on both sides of the gate stack 200 ; The capping layer 107 on the top of the vacancy 106; the source and drain regions 202 in the substrate on both sides of the gate stack 200; and the interlayer dielectric layer 300 covering the source and drain regions 202. Wherein, the surface of the vacancy 106 adjacent to the interlayer dielectric layer 300 is arc-shaped, the width of the top is smaller than the width of the bottom, the width of the top of the vacancy 106 is 10-30 nm, and the width difference between the top and the bottom is 30-30 nm. 60nm. Wherein, the thickness of the capping layer 107 is less than 5 nm.

The substrate 100 is preferably a thin single-crystal silicon layer, and may also be a single-crystal germanium-silicon alloy.

The gate stack 200 may be only a metal gate, or may be a metal/polysilicon composite gate, wherein the upper surface of the polysilicon has silicide.

According to the MOS transistor structure provided by the present invention, after the interlayer dielectric layer is formed, the sidewall is etched away, vacancies are formed in the interlayer dielectric layer above the gate and the source and drain regions, and the previous sidewall material is replaced with air, effectively The dielectric constant of the material in the outer edge region is reduced, and at the same time, the capacitive coupling effect between the source drain region and the gate is weakened, thereby effectively reducing parasitic capacitance and optimizing device performance.

The manufacturing method of the present invention will be described in detail below in conjunction with the accompanying drawings, including the following steps. It should be noted that the drawings of the various embodiments of the present invention are only for illustrative purposes, and therefore are not necessarily drawn to scale.

Firstly, a substrate 100 is provided. The substrate material is a semiconductor material, such as silicon, germanium, gallium arsenide, etc. Preferably, in this embodiment, the substrate used is a silicon substrate.

Next, a dummy gate stack 101 is formed on the surface of the substrate. The dummy gate structure 101 can be single layer or multi-layer. The dummy gate structure 101 may include polymer material, amorphous silicon, polysilicon or TiN, and may have a thickness of 10 nm˜200 nm. In this example, the dummy gate structure includes polysilicon and silicon dioxide. Specifically, polysilicon is first deposited on the semiconductor substrate by chemical vapor deposition, and then a dielectric layer of silicon dioxide is formed on the polysilicon by epitaxial growth, oxidation, CVD, and the like. Then, the silicon dioxide dielectric layer and the polysilicon are photolithographically and etched using a conventional CMOS process, and patterned to form a dummy gate stack, as shown in FIG. 2 .

Next, as shown in FIG. 3 , the substrate 100 on both sides of the dummy gate structure 102 is lightly doped to form lightly doped source and drain regions 201 as source and drain extension regions. Halo implantation can also be performed to form a Halo implantation region under the source-drain extension region. The impurity type of shallow doping is consistent with the device type, and the impurity type of Halo implantation is opposite to the device type.

Next, a first spacer portion 102 is deposited on the semiconductor structure. The purpose of the first sidewall part 102 is to make the top of the formed sidewall have a certain thickness, so as not to be covered by the interlayer dielectric layer 300 formed in the subsequent process, so as to facilitate selective etching. The material of the first spacer portion 102 is an insulating medium, which may be silicon oxide or silicon nitride. In the present invention, in order to facilitate selective etching, the material of the first sidewall portion 102 is silicon nitride. Specifically, a layer of silicon nitride can be deposited on the semiconductor structure by chemical vapor deposition, plasma deposition, etc., with a thickness of 10-30 nm.

Next, as shown in FIG. 5 , a second sidewall portion 103 is formed on the surface of the first sidewall portion 102 perpendicular to the substrate, and the material of the second sidewall portion 103 and the first sidewall portion 102 same. Specifically, LPCVD is used to deposit silicon nitride with a thickness of 40 nm to 80 nm on the semiconductor substrate on both sides of the first sidewall part 102 to form a sacrificial sidewall dielectric layer, and then perform anisotropy on the sacrificial sidewall dielectric layer. Etching to form a second spacer portion 103 with a width of 30nm-70nm on both sides of the dummy gate structure. The second sidewall portion 103 can also be formed of silicon oxide, silicon oxynitride, silicon carbide and combinations thereof, and/or other suitable materials. The second side wall part 103 may have a multi-layer structure. The second spacer portion 103 can also be formed by deposition and etching processes, and its thickness range can be 10nm-100nm, such as 30nm, 50nm or 80nm.

Next, the first spacer portion 102 located on the top of the dummy gate stack 101 and the surface of the source-drain extension region 201 is removed to form a spacer 105 . Specifically, anisotropic etching is used to etch the semiconductor structure with a thickness equal to the thickness of the first sidewall portion 102 until the substrate where the source and drain regions are located and the top of the dummy gate stack are exposed. At this time, the first side wall part 102 and the second side wall part 103 jointly form a complete side wall structure 105 , as shown in FIG. 6 , the width of the top of the side wall 105 is greater than the width of the first side wall part 102 .

Next, the source and drain regions 202 are implanted as shown in FIG. 7 . First deposit a silicon dioxide dielectric layer (not shown in the figure) with a thickness of 10nm to 35nm, and use the dielectric layer as a buffer layer to perform ion implantation to form source and drain regions 202, which are covered by sidewalls 105 The region of is the source-drain extension region 201 . For P-type crystals, the dopant is boron or boron fluoride or indium or gallium. For N-type crystals, the dopant is phosphorus or arsenic or antimony. The doping concentration is 5e10 ¹⁹ cm ^-3 to 1e10 ²⁰ cm ^-3 .

Next, an interlayer dielectric layer 300 is formed on the semiconductor structure, as shown in FIG. 8 . In order to perform selective etching in subsequent processes, the material of the interlayer dielectric layer 300 is different from that of the sidewall 105 . In this embodiment, the material of the interlayer dielectric layer 300 is silicon oxide.

Next, the dummy gate structure 101 is removed to form dummy gate vacancies. The dummy gate structure 101 may be removed by wet etching and/or dry etching. In one embodiment, plasma etching is used to remove the dummy gate structure 101 . Next, as shown in FIG. 9 , a gate stack 200 is formed in the gate vacancy. The gate stack 200 includes a gate dielectric layer and a gate contact layer, and the gate contact layer may be only a metal gate, or a metal/polysilicon composite gate, wherein the upper surface of the polysilicon has silicide.

Next, the sidewall 105 is removed to form a vacancy 106 , and the vacancy 106 is located above the source-drain extension region 201 . Specifically, the sidewall 105 may be removed by wet selective etching, and the etching selectivity ratio of the used etching solution to silicon nitride and silicon oxide is greater than 30:1. The semiconductor structure after etching is shown in FIG. 10 .

Next, a sacrificial material layer 400 is deposited on the semiconductor structure, and chemical mechanical polishing (CMP) is performed until the top of the gate stack is exposed. The etched part is covered to facilitate interconnection and wiring in subsequent processes. The material of the sacrificial material layer 400 is the same as that of the interlayer dielectric layer 300 . The specific process steps are shown in FIG. 11 . After the CMP is completed, a capping layer 107 is formed on top of the vacancies 105 , as shown in FIG. 12 .

According to the MOS transistor structure provided by the present invention, after the interlayer dielectric layer is formed, the sidewall is etched away, vacancies are formed in the interlayer dielectric layer above the gate and the source and drain regions, and the previous sidewall material is replaced with air, effectively The dielectric constant of the material in the outer edge region is reduced, and at the same time, the capacitive coupling effect between the source drain region and the gate is weakened, thereby effectively reducing parasitic capacitance and optimizing device performance.

Although the example embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made to these embodiments without departing from the spirit and scope of the invention as defined by the appended claims. For other examples, those of ordinary skill in the art will readily understand that the order of process steps may be varied while remaining within the scope of the present invention.

In addition, the scope of application of the present invention is not limited to the process, structure, manufacture, material composition, means, methods and steps of the specific embodiments described in the specification. From the disclosure of the present invention, those of ordinary skill in the art will easily understand that for the processes, structures, manufacturing, material compositions, means, methods or steps that currently exist or will be developed in the future, where they are implemented in accordance with the description of the present invention Corresponding embodiments that perform substantially the same function or achieve substantially the same results can be applied in accordance with the present invention. Therefore, the appended claims of the present invention are intended to include such processes, structures, manufactures, compositions of matter, means, methods or steps within their protection scope.

Claims (13)

1. a manufacture method for MOS transistor, comprising:

A., Semiconductor substrate (100) and pseudo-gate stack (101) are provided, in the substrate of described pseudo-gate stack (102) both sides, there is source and drain extension (201);

B. the first sidewall section (102) is formed in described pseudo-gate stack both sides;

C. described first sidewall section (102) perpendicular to formation second sidewall section (103) on the surface of substrate;

D. remove described first sidewall section (102) to be positioned at pseudo-gate stack (101) top and to be positioned at the part in upper second sidewall section (103) outside, source and drain extension (201), form side wall (105);

E. in the substrate of pseudo-gate stack both sides, form source-drain area, and above described source-drain area, form interlayer dielectric layer (300);

F. remove described pseudo-gate stack (101) to form opening, and fill gate stack (200) in said opening;

G. remove described side wall (105), form room (106);

H. it is made to fill room (106) top at described interlayer dielectric layer (300) and the upper deposit sacrificial material layer (400) of described pseudo-gate stack (101), and carry out chemico-mechanical polishing, until expose described gate stack (101) top, the sacrificial material layer be not etched away is made to form cap rock (107) at described room (106) top.

2. manufacture method according to claim 1, is characterized in that, in stepb, the material of described first sidewall section (102) is silicon nitride.

3. manufacture method according to claim 1 and 2, is characterized in that, in stepb, the thickness of described first sidewall section (102) is 10 ~ 30nm.

4. manufacture method according to claim 1, is characterized in that, in step c, described second sidewall section (103) is identical with the material of the first sidewall section (102).

5. manufacture method according to claim 1, is characterized in that, in steps d, the method for described removal first sidewall section (102) is anisotropic etching.

6. manufacture method according to claim 1, is characterized in that, in steps d, the material of described interlayer dielectric layer (300) is different from the material of side wall (105).

7. the manufacture method according to claim 1 or 6, is characterized in that, in steps d, the material of described interlayer dielectric layer (300) is silica.

8. manufacture method according to claim 1, is characterized in that, in step g, the method for described removal side wall (105) is selective etch.

9. manufacture method according to claim 1, is characterized in that, in step h, the material of described sacrificial material layer (400) is identical with interlayer dielectric layer (300).

10. a mos transistor structure, comprising:

Substrate (100);

Gate stack (200), is positioned at described substrate (100) top;

Source-drain area (202), is arranged in described gate stack (200) both sides substrate;

Interlayer dielectric layer (300), covers described source-drain area (202);

Room (106), is positioned at described gate stack (200) both sides, is surrounded by described interlayer dielectric layer (300) and substrate (100); And

Cap rock (107), covers described room (106) top.

11. transistor arrangements according to claim 10, is characterized in that, described room (106) face adjacent with interlayer dielectric layer (300) is arc, and the width at its top is less than the width of bottom.

12. transistor arrangements according to claim 10, is characterized in that, the width at described room (106) top is 10 ~ 30nm, and the stand out of top and bottom is 30 ~ 60nm.

13. transistor body structures according to claim 10, is characterized in that, the thickness of described cap rock (107) is less than 5nm.