CN104733319A - MOS transistor structure and manufacturing method thereof - Google Patents
MOS transistor structure and manufacturing method thereof Download PDFInfo
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- CN104733319A CN104733319A CN201310714649.5A CN201310714649A CN104733319A CN 104733319 A CN104733319 A CN 104733319A CN 201310714649 A CN201310714649 A CN 201310714649A CN 104733319 A CN104733319 A CN 104733319A
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- 239000010410 layer Substances 0.000 claims abstract description 55
- 239000000463 material Substances 0.000 claims abstract description 43
- 239000011229 interlayer Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 238000005498 polishing Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 7
- 239000011435 rock Substances 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 19
- 238000000151 deposition Methods 0.000 abstract description 4
- 230000008021 deposition Effects 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 230000001808 coupling effect Effects 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
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- 125000001475 halogen functional group Chemical group 0.000 description 3
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- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
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- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910015900 BF3 Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 1
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- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
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- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
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- 230000003647 oxidation Effects 0.000 description 1
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Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a manufacturing method of a MOS transistor, which comprises the following steps: a. providing a semiconductor substrate and a pseudo gate stack; b. forming a deposition first sidewall portion on both sides of the dummy gate stack; c. forming a second sidewall portion on a surface of the deposited first sidewall portion perpendicular to the substrate; d. removing the first side wall part positioned at the top of the pseudo gate stack and the part of the source drain expansion region positioned at the outer side of the second side wall part to form a side wall; e. forming source and drain regions in the substrate at two sides of the pseudo gate stack, and forming an interlayer dielectric layer; f. removing the pseudo gate stack to form an opening, and filling the position in the opening with a gate stack; g. removing the side wall to form a vacancy; h. and depositing a sacrificial material layer on the interlayer dielectric layer and the pseudo gate stack to fill the top of the vacancy, and carrying out chemical mechanical polishing until the top of the gate stack is exposed. Compared with the prior art, the invention effectively reduces the parasitic capacitance of the grid electrode and improves the performance of the device.
Description
Technical field
The present invention relates to a kind of semiconductor device structure and manufacture method thereof, particularly, relate to a kind of mos transistor structure and manufacture method thereof.
Technical background
In MOSFET structure, parasitic gate electric capacity is the key factor affecting device frequency response and switching speed, determines grid RC time delay and RF frequency response.In order to improve device performance, we need the parasitic capacitance reducing MOSFET as much as possible, and day by day reduce along with device size, and the impact of parasitic capacitance is more and more significant, and the parasitic capacitance reducing device further significantly can improve device performance.
Parasitic capacitance is directly determined by the physical structure of device, and its size is directly related with the size of device.As shown in Figure 1, parasitic gate electric capacity mainly comprises three parts: i.e. inward flange parasitic capacitance C
if, outward flange parasitic capacitance C
ofand overlapping parasitic capacitance C
ov.Wherein, outward flange parasitic capacitance C
oftopmost part in grid parasitic capacitance, its size and grid length, gate height and the packing material between grid and source and drain closely related.By many restrictions, for the device of specific dimensions, its grid length and gate height cannot reduce further, and the change of device architecture also can cause other negative effect a lot, and the parasitic capacitance of device is difficult to be reduced further.
Based on this problem, the invention provides a kind of novel semi-conductor structure, side wall is etched away after formation interlayer dielectric layer, room is formed in interlayer dielectric layer above grid and source-drain area, spacer material before replacing with air, efficiently reduces the dielectric constant of outer edge zone material, weakens the capacitance coupling effect between source-drain area and grid simultaneously, thus efficiently reduce parasitic capacitance, optimize device performance.
Summary of the invention
The invention provides a kind of mos transistor structure and preparation method thereof, reduce parasitic capacitance, optimize device performance.Particularly, manufacture method provided by the invention comprises the following steps:
A., Semiconductor substrate and pseudo-gate stack are provided, in the substrate of described pseudo-gate stack both sides, there is source and drain extension;
B. deposit first sidewall section is formed in described pseudo-gate stack both sides;
C. the second sidewall section is formed at described deposit first sidewall section perpendicular on the surface of substrate;
D. remove described first sidewall section and be positioned at the part pseudo-gate stack top and source and drain extension be positioned at outside the second sidewall section, form side wall;
E. in the substrate of pseudo-gate stack both sides, form source-drain area, and form interlayer dielectric layer above described source-drain area;
F. remove described pseudo-gate stack to form opening, and also fill gate stack in said opening;
G. remove described side wall, form room;
H. deposit sacrificial material layer on described interlayer dielectric layer and pseudo-gate stack, and carry out chemico-mechanical polishing, until expose gate stack top.
Wherein, in stepb, the material of described first sidewall section is silicon nitride.
Wherein, in stepb, the thickness of described first sidewall section is 10 ~ 30nm.
Wherein, in step c, described second sidewall section is identical with the material of the second sidewall section.
Wherein, in steps d, the method for described removal first sidewall section is anisotropic etching.
Wherein, in steps d, the material of described interlayer dielectric layer is different from the material of side wall.
Wherein, in steps d, the material of described interlayer dielectric layer is silica.
Wherein, in step g, the method for described removal side wall is selective etch.
Wherein, in step h, the material of described sacrificial material layer is identical with interlayer dielectric layer.
Accordingly, present invention also offers a kind of mos transistor structure, comprising:
Substrate;
Gate stack, is positioned at described types of flexure;
Source-drain area, is arranged in described gate stack both sides substrate;
Interlayer dielectric layer, covers described source-drain area;
Room, is positioned at described gate stack both sides, is surrounded by described interlayer dielectric layer and substrate; And
Cap rock, covers top, described room.
Wherein, the face adjacent with interlayer dielectric layer, described room is arc, and the width at its top is less than the width of bottom.
Wherein, the width at top, described room is 10 ~ 30nm, and the stand out of top and bottom is 30 ~ 60nm.
Wherein, described thickness is less than 5nm.
According to mos transistor structure provided by the invention, side wall is etched away after formation interlayer dielectric layer, room is formed in interlayer dielectric layer above grid and source-drain area, spacer material before replacing with air, efficiently reduce the dielectric constant of outer edge zone material, weaken the capacitance coupling effect between source-drain area and grid simultaneously, thus efficiently reduce parasitic capacitance, optimize device performance.
Accompanying drawing explanation
By reading the detailed description done non-limiting example done with reference to the following drawings, other features, objects and advantages of the present invention will become more obvious:
Fig. 1 is the schematic diagram of MOS device grid parasitic capacitance;
Fig. 2 ~ Figure 12 is the profile of each fabrication stage of MOS device according to a specific embodiment of the present invention.
In accompanying drawing, same or analogous Reference numeral represents same or analogous parts.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, embodiments of the invention are described in detail.
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.
See Figure 12, the invention provides a kind of mos transistor structure, comprising: substrate 100; Be positioned at the gate stack 200 above described substrate 100; Be positioned at the room 106 of described gate stack 200 both sides; Be positioned at the cap rock 107 at top, described room 106; Be arranged in the source-drain area 202 of described gate stack 200 both sides substrate; And cover the interlayer dielectric layer 300 of source-drain area 202.Wherein, the face adjacent with interlayer dielectric layer 300, described room 106 is arc, and the width at its top is less than the width of bottom, and the width at top, described room 106 is 10 ~ 30nm, and the stand out of top and bottom is 30 ~ 60nm.Wherein, the thickness of described cap rock 107 is less than 5nm.
This substrate 100 first-selection is a thin monocrystalline silicon layer, also can be the germanium-silicon alloy of monocrystalline.
Gate stack 200 can be only metal gates, also can be metal/Polysilicon Composite Structures grid, wherein polysilicon upper surface have silicide.
According to mos transistor structure provided by the invention, side wall is etched away after formation interlayer dielectric layer, room is formed in interlayer dielectric layer above grid and source-drain area, spacer material before replacing with air, efficiently reduce the dielectric constant of outer edge zone material, weaken the capacitance coupling effect between source-drain area and grid simultaneously, thus efficiently reduce parasitic capacitance, optimize device performance.
Below in conjunction with accompanying drawing, manufacture method of the present invention is described in detail, comprises the following steps.It should be noted that, the accompanying drawing of each embodiment of the present invention is only the object in order to illustrate, so there is no necessity and draws in proportion.
First substrate 100 is provided.Described backing material is semi-conducting material, can be silicon, germanium, GaAs etc., and preferably, in the present embodiment, substrate used is silicon substrate.
Next, pseudo-gate stack 101 is formed at described substrate surface.Described pseudo-grid structure 101 can be individual layer, also can be multilayer.Pseudo-grid structure 101 can comprise polymeric material, amorphous silicon, polysilicon or TiN, and thickness can be 10nm ~ 200nm.In this example, pseudo-grid structure comprises polysilicon and silicon dioxide.Concrete, first adopt the method depositing polysilicon on the semiconductor substrate of chemical vapor deposition, then square one-tenth layer of silicon dioxide dielectric layer on the polysilicon, formation method can be epitaxial growth, oxidation, CVD etc.Then adopt stand CMOS, photoetching and etching are carried out to described silica dioxide medium layer and polysilicon, will be graphical, form pseudo-gate stack, as shown in Figure 2.
Next, as shown in Figure 3, shallow doping is carried out to the substrate 100 of pseudo-grid structure 102 both sides, to form the lightly-doped source drain region 201 as source and drain extension area.Halo injection can also be carried out, to form Halo injection region below source and drain extension area.Wherein the dopant type of shallow doping is consistent with type of device, and the dopant type that Halo injects is contrary with type of device.
Next, deposit first sidewall section 102 on described semiconductor structure.The object of described first sidewall section 102 makes the side wall top of formation have certain thickness, thus the interlayer dielectric layer 300 that can not be formed in subsequent technique covers, and is convenient to selective etch.The material of the first sidewall section 102 is dielectric, can be silica or silicon nitride.In the present invention, for the ease of selective etch, the material of described first sidewall section 102 is silicon nitride.Concrete, can adopt the method such as chemical vapor deposition, plasma deposition deposit one deck silicon nitride on described semiconductor structure, its thickness is 10 ~ 30nm.
Next, as shown in Figure 5, at described first sidewall section 102 perpendicular to the surface of substrate being formed the second sidewall section 103, described second sidewall section 103 is identical with the material of the first sidewall section 102.Concrete, with the LPCVD silicon nitride that deposit 40nm ~ 80nm is thick in the Semiconductor substrate of the first sidewall section 102 both sides, formed and sacrifice side wall medium layer, then anisotropic etching is carried out to described sacrifice side wall medium layer, form in pseudo-grid structure both sides the second sidewall section 103 that width is 30nm ~ 70nm.Second sidewall section 103 can also by silica, silicon oxynitride, carborundum and combination thereof, and/or other suitable materials are formed.Second sidewall section 103 can have sandwich construction.Second sidewall section 103 can also be formed by comprising deposition-etch technique, and its thickness range can be 10nm-100nm, as 30nm, 50nm or 80nm.
Next, remove the first sidewall section 102 being positioned at pseudo-gate stack 101 top and surface, source and drain extension 201, form side wall 105.Concrete, adopt anisotropic etching to etch described semiconductor structure, etch thicknesses equals the thickness of the first sidewall section 102, until expose the substrate at source-drain area place and pseudo-gate stack top.Now the first sidewall section 102 and the second sidewall section 103 combine the complete sidewall structure 105 of formation, and as shown in Figure 6, the width on described side wall 105 top is greater than the width of the first sidewall section 102.
Next, carry out source-drain area 202 as shown in Figure 7 to inject.First deposit a layer thickness is the silica dioxide medium layer (not shown) that 10nm ~ 35nm is thick, and with this dielectric layer for resilient coating, carries out ion implantation to form source-drain area 202, is wherein source and drain extension area 201 by the region that side wall 105 covers.For P-type crystal, dopant is boron or boron fluoride or indium or gallium etc.For N-type crystal, dopant is phosphorus or arsenic or antimony etc.Doping content is 5e10
19cm
-3~ 1e10
20cm
-3.
Next, described semiconductor structure forms interlayer dielectric layer 300, as shown in Figure 8.In order to carry out selective etch in subsequent technique, the material of described interlayer dielectric layer 300 is different from side wall 105.In the present embodiment, the material of described interlayer dielectric layer 300 is silica.
Next, remove described pseudo-grid structure 101, form pseudo-grid room.Wet etching and/or dry etching can be adopted to remove pseudo-grid structure 101.In one embodiment, the pseudo-grid structure 101 of using plasma etching removing.Next, as shown in Figure 9, in grid room, gate stack 200 is formed.Described gate stack 200 comprises gate dielectric layer and gate contact layer, and described gate contact layer can be only metal gates, also can be metal/Polysilicon Composite Structures grid, wherein polysilicon upper surface have silicide.
Next, remove described side wall 105, form room 106, described room 106 is positioned at the top of source and drain extension area 201.Concrete, wet selective can be adopted to etch and remove side wall 105, the etching selection ratio of corrosive liquid used to silicon nitride and silica is greater than 30:1.Semiconductor structure after completing etching as shown in Figure 10.
Next, deposit sacrificial material layer 400 on described semiconductor structure, and carry out chemico-mechanical polishing (CMP), until expose gate stack top, its object is to top, closed room 106, its top is sacrificed, and part that material layer 400 is not etched covers, and the technique after being convenient to carries out the work such as interconnected wiring, the material of described sacrificial material layer 400 is identical with the material of interlayer dielectric layer 300, and concrete technology step as shown in figure 11.After completing CMP, form cap rock 107 at top, described room 105, as shown in figure 12.
According to mos transistor structure provided by the invention, side wall is etched away after formation interlayer dielectric layer, room is formed in interlayer dielectric layer above grid and source-drain area, spacer material before replacing with air, efficiently reduce the dielectric constant of outer edge zone material, weaken the capacitance coupling effect between source-drain area and grid simultaneously, thus efficiently reduce parasitic capacitance, optimize device performance.
Although describe in detail about example embodiment and advantage thereof, being to be understood that when not departing from the protection range of spirit of the present invention and claims restriction, various change, substitutions and modifications can being carried out to these embodiments.For other examples, those of ordinary skill in the art should easy understand maintenance scope in while, the order of processing step can change.
In addition, range of application of the present invention is not limited to the technique of the specific embodiment described in specification, structure, manufacture, material composition, means, method and step.From disclosure of the present invention, will readily appreciate that as those of ordinary skill in the art, for the technique existed at present or be about to develop, structure, manufacture, material composition, means, method or step later, wherein their perform the identical function of the corresponding embodiment cardinal principle that describes with the present invention or obtain the identical result of cardinal principle, can apply according to the present invention to them.Therefore, claims of the present invention are intended to these technique, structure, manufacture, material composition, means, method or step to be included in its protection range.
Claims (13)
1. a manufacture method for MOS transistor, comprising:
A., Semiconductor substrate (100) and pseudo-gate stack (101) are provided, in the substrate of described pseudo-gate stack (102) both sides, there is source and drain extension (201);
B. the first sidewall section (102) is formed in described pseudo-gate stack both sides;
C. described first sidewall section (102) perpendicular to formation second sidewall section (103) on the surface of substrate;
D. remove described first sidewall section (102) to be positioned at pseudo-gate stack (101) top and to be positioned at the part in upper second sidewall section (103) outside, source and drain extension (201), form side wall (105);
E. in the substrate of pseudo-gate stack both sides, form source-drain area, and above described source-drain area, form interlayer dielectric layer (300);
F. remove described pseudo-gate stack (101) to form opening, and fill gate stack (200) in said opening;
G. remove described side wall (105), form room (106);
H. it is made to fill room (106) top at described interlayer dielectric layer (300) and the upper deposit sacrificial material layer (400) of described pseudo-gate stack (101), and carry out chemico-mechanical polishing, until expose described gate stack (101) top, the sacrificial material layer be not etched away is made to form cap rock (107) at described room (106) top.
2. manufacture method according to claim 1, is characterized in that, in stepb, the material of described first sidewall section (102) is silicon nitride.
3. manufacture method according to claim 1 and 2, is characterized in that, in stepb, the thickness of described first sidewall section (102) is 10 ~ 30nm.
4. manufacture method according to claim 1, is characterized in that, in step c, described second sidewall section (103) is identical with the material of the first sidewall section (102).
5. manufacture method according to claim 1, is characterized in that, in steps d, the method for described removal first sidewall section (102) is anisotropic etching.
6. manufacture method according to claim 1, is characterized in that, in steps d, the material of described interlayer dielectric layer (300) is different from the material of side wall (105).
7. the manufacture method according to claim 1 or 6, is characterized in that, in steps d, the material of described interlayer dielectric layer (300) is silica.
8. manufacture method according to claim 1, is characterized in that, in step g, the method for described removal side wall (105) is selective etch.
9. manufacture method according to claim 1, is characterized in that, in step h, the material of described sacrificial material layer (400) is identical with interlayer dielectric layer (300).
10. a mos transistor structure, comprising:
Substrate (100);
Gate stack (200), is positioned at described substrate (100) top;
Source-drain area (202), is arranged in described gate stack (200) both sides substrate;
Interlayer dielectric layer (300), covers described source-drain area (202);
Room (106), is positioned at described gate stack (200) both sides, is surrounded by described interlayer dielectric layer (300) and substrate (100); And
Cap rock (107), covers described room (106) top.
11. transistor arrangements according to claim 10, is characterized in that, described room (106) face adjacent with interlayer dielectric layer (300) is arc, and the width at its top is less than the width of bottom.
12. transistor arrangements according to claim 10, is characterized in that, the width at described room (106) top is 10 ~ 30nm, and the stand out of top and bottom is 30 ~ 60nm.
13. transistor body structures according to claim 10, is characterized in that, the thickness of described cap rock (107) is less than 5nm.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20180021210A (en) * | 2015-07-17 | 2018-02-28 | 인텔 코포레이션 | Transistor with air gap spacers |
| CN109313726A (en) * | 2015-12-30 | 2019-02-05 | 谷歌有限责任公司 | It is thinned using dielectric to reduce surface loss and the spuious coupling in quantum devices |
| CN110047741A (en) * | 2018-01-16 | 2019-07-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN113517196A (en) * | 2021-06-28 | 2021-10-19 | 上海华力集成电路制造有限公司 | Air side wall manufacturing method for reducing parasitic capacitance of FinFET device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000124454A (en) * | 1998-10-20 | 2000-04-28 | Nec Corp | Semiconductor device and its manufacture |
| US6633070B2 (en) * | 2001-05-01 | 2003-10-14 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| CN102629627A (en) * | 2012-04-16 | 2012-08-08 | 清华大学 | Heterogeneous gate tunneling transistor and forming method thereof |
| CN103390644A (en) * | 2012-05-08 | 2013-11-13 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
-
2013
- 2013-12-20 CN CN201310714649.5A patent/CN104733319A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000124454A (en) * | 1998-10-20 | 2000-04-28 | Nec Corp | Semiconductor device and its manufacture |
| US6633070B2 (en) * | 2001-05-01 | 2003-10-14 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| CN102629627A (en) * | 2012-04-16 | 2012-08-08 | 清华大学 | Heterogeneous gate tunneling transistor and forming method thereof |
| CN103390644A (en) * | 2012-05-08 | 2013-11-13 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20180021210A (en) * | 2015-07-17 | 2018-02-28 | 인텔 코포레이션 | Transistor with air gap spacers |
| CN107851659A (en) * | 2015-07-17 | 2018-03-27 | 英特尔公司 | Transistor with air gap separation body |
| US11114538B2 (en) | 2015-07-17 | 2021-09-07 | Intel Corporation | Transistor with an airgap spacer adjacent to a transistor gate |
| CN107851659B (en) * | 2015-07-17 | 2022-04-08 | 英特尔公司 | Transistor with air gap spacer |
| KR102542847B1 (en) * | 2015-07-17 | 2023-06-14 | 인텔 코포레이션 | Transistors with airgap spacers |
| CN109313726A (en) * | 2015-12-30 | 2019-02-05 | 谷歌有限责任公司 | It is thinned using dielectric to reduce surface loss and the spuious coupling in quantum devices |
| CN110047741A (en) * | 2018-01-16 | 2019-07-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110047741B (en) * | 2018-01-16 | 2021-07-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN113517196A (en) * | 2021-06-28 | 2021-10-19 | 上海华力集成电路制造有限公司 | Air side wall manufacturing method for reducing parasitic capacitance of FinFET device |
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