CN113517196A - Air side wall manufacturing method for reducing parasitic capacitance of FinFET device - Google Patents

Air side wall manufacturing method for reducing parasitic capacitance of FinFET device Download PDF

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Publication number
CN113517196A
CN113517196A CN202110720475.8A CN202110720475A CN113517196A CN 113517196 A CN113517196 A CN 113517196A CN 202110720475 A CN202110720475 A CN 202110720475A CN 113517196 A CN113517196 A CN 113517196A
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China
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side wall
parasitic capacitance
finfet
air
gate structure
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CN202110720475.8A
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Chinese (zh)
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李勇
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/515—Insulating materials associated therewith with cavities, e.g. containing a gas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides an air side wall manufacturing method for reducing parasitic capacitance of a FinFET device, which comprises a polycrystalline silicon pseudo gate structure, an inner side wall attached to the side wall of the polycrystalline silicon pseudo gate structure, and an SiN side wall attached to the inner side wall; an outer side wall is formed on the side wall of the grid structure; an interlayer dielectric layer covering the gate structure; grinding the interlayer dielectric layer to expose the top of the polysilicon pseudo gate structure; removing the SiN side wall to form an air side wall; removing the polycrystalline silicon pseudo gate structure to form a groove; forming an interface layer at the bottom and the side wall of the groove; forming a work function layer in the groove; filling metal into the groove to form a metal gate; and etching back to form the silicon nitride plug. In the manufacturing process of the FinFET, the air side wall is formed at the position of the grid side wall of the MOS structure so as to reduce the parasitic capacitance. Because the dielectric constant of air is 1, the dielectric constant is much smaller than that of a low-K dielectric layer with the dielectric constant of about 5 and SiN with the dielectric constant of about 7.4, and the capacitance between the gate and the contact hole and the parasitic capacitance between the gate and the source-drain epitaxy are favorably reduced.

Description

Air side wall manufacturing method for reducing parasitic capacitance of FinFET device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of an air side wall for reducing parasitic capacitance of a FinFET device.
Background
In the epitaxial manufacturing process of the FinFET, the SiN spacer layer is usually used as a low-K sidewall of the gate to obtain high-quality epitaxy, such as high crystal integrity, low defect count, etc., and the dielectric constant value K of the SiN spacer layer is 7.4, which may result in higher capacitance between the gate and the contact hole and capacitance between the gate and the source-drain epitaxy, and thus may generate higher parasitic capacitance.
Therefore, a new method is needed to solve the above problems.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide an air side wall manufacturing method for reducing parasitic capacitance of a FinFET device, so as to solve the problem of high parasitic capacitance in a gate of a FinFET device in the prior art.
To achieve the above and other related objects, the present invention provides a method for fabricating an air sidewall for reducing parasitic capacitance of a FinFET device, which at least includes:
step one, providing an MOS structure, wherein the MOS structure at least comprises: a substrate; a source region epitaxial region and a drain region epitaxial region on the substrate; the grid structure is positioned between the source region epitaxial region and the drain region epitaxial region; the gate structure includes at least: the gate oxide layer, a polycrystalline silicon pseudo gate structure positioned on the gate oxide layer, an inner side wall attached to the side wall of the polycrystalline silicon pseudo gate structure, and an SiN side wall attached to the inner side wall and covering the top of the polycrystalline silicon pseudo gate structure;
an outer side wall is formed on the side wall of the SiN side wall of the grid structure; an interlayer dielectric layer covering the grid structure is formed on the substrate;
grinding the interlayer dielectric layer to expose the top of the polycrystalline silicon pseudo gate structure;
removing the SiN side wall, and forming a gap between the inner side wall and the outer side wall of the polycrystalline silicon pseudo gate structure;
forming a plug for sealing the gap at the upper port of the gap, wherein the sealed gap between the inner side wall and the outer side wall forms an air side wall;
fifthly, removing the polycrystalline silicon pseudo gate structure and the gate oxide layer, and forming a groove at the removed position;
sixthly, forming interface layers at the bottom and the side wall of the groove; forming a work function layer in the groove;
filling metal in the groove, and then flattening the surface of the MOS structure to form a metal gate;
step eight, carrying out back etching on the metal gate, and then forming a silicon nitride plug in a back etching area;
and step nine, forming metal contact lines on the grid structure and the source region epitaxial region and the drain region epitaxial region.
Preferably, the inner sidewall spacer in the first step is a low-K dielectric layer.
Preferably, the outer sidewall in the first step is a low-K dielectric layer.
Preferably, the dielectric constant of the inner sidewall spacer in the first step is about 5.
Preferably, the dielectric constant of the outer wall in the first step is about 5.
Preferably, the thickness of the SiN side wall in the first step is 2-8 nm.
Preferably, the outer sidewall in the first step extends to the upper surface of the source region epitaxial region and the drain region epitaxial region.
Preferably, the method for polishing the upper surface of the gate structure in the second step is a chemical mechanical polishing method.
Preferably, the plug in step four is one of silicon nitride or silicon oxide.
Preferably, the interface layer in the sixth step extends to the upper part of the interlayer dielectric layer.
Preferably, the work function layer in the sixth step is an HfO2 layer.
As described above, the method for manufacturing the air side wall for reducing the parasitic capacitance of the FinFET device of the present invention has the following beneficial effects: in the manufacturing process of the FinFET, the air side wall is formed at the position of the grid side wall of the MOS structure so as to reduce the parasitic capacitance. Because the dielectric constant of air is 1, the dielectric constant is much smaller than that of a low-K dielectric layer with the dielectric constant of about 5 and SiN with the dielectric constant of about 7.4, and the capacitance between the gate and the contact hole and the parasitic capacitance between the gate and the source-drain epitaxy are favorably reduced.
Drawings
FIG. 1 is a schematic diagram of a MOS structure with a polysilicon dummy gate exposed after polishing according to the present invention;
FIG. 2 is a schematic structural diagram of the SiN spacer removed structure of the present invention;
FIG. 3 is a schematic view of the structure of the present invention after plugs are formed at the upper ports of the voids;
FIG. 4 is a schematic structural view of the polysilicon dummy gate structure removed in the present invention;
FIG. 5 is a schematic structural diagram of the present invention after forming an interface layer and a work function layer in a groove;
FIG. 6 is a schematic diagram of a structure of forming a metal gate in a groove according to the present invention;
FIG. 7 is a schematic diagram of the structure of the present invention after forming the silicon nitride plug;
FIG. 8 is a schematic structural diagram of metal contact lines formed on the gate structure and the epitaxial regions of the source region and the drain region in the present invention;
fig. 9 is a flowchart of a method for fabricating an air sidewall to reduce parasitic capacitance of a FinFET device according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 9. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The invention provides an air side wall manufacturing method for reducing parasitic capacitance of a FinFET device, as shown in FIG. 9, FIG. 9 is a flow chart of the air side wall manufacturing method for reducing parasitic capacitance of a FinFET device, the method at least comprises the following steps:
step one, providing an MOS structure, wherein the MOS structure at least comprises: a substrate; a source region epitaxial region and a drain region epitaxial region on the substrate; the grid structure is positioned between the source region epitaxial region and the drain region epitaxial region; the gate structure includes at least: the gate oxide layer, a polycrystalline silicon pseudo gate structure positioned on the gate oxide layer, an inner side wall attached to the side wall of the polycrystalline silicon pseudo gate structure, and an SiN side wall attached to the inner side wall and covering the top of the polycrystalline silicon pseudo gate structure; as shown in fig. 1, fig. 1 is a schematic diagram of a MOS structure of the present invention in which the top of the polysilicon dummy gate is exposed after polishing. The MOS structure in the first step at least includes: a substrate 01; a source region epitaxial region (epi)02 and a drain region epitaxial region (epi)02 (any one of the epi located on the left side and the right side of the MOS structure in fig. 1 is denoted as a source region epitaxial region or a drain region epitaxial region) on the substrate 01; a gate structure located between the source region epitaxial region (epi)02 and the drain region epitaxial region (epi) 02; the gate structure includes at least: the gate oxide layer (the gate oxide layer is not shown in fig. 1), a polycrystalline silicon dummy gate structure 03 located on the gate oxide layer, an inner side wall 04 attached to the side wall of the polycrystalline silicon dummy gate structure 03, and a SiN side wall 05 attached to the inner side wall 04 and covering the top of the polycrystalline silicon dummy gate structure 03. The SiN sidewall spacers 05 shown in fig. 1 are ground to expose the top of the polysilicon dummy gate structure.
An outer side wall is formed on the side wall of the SiN side wall of the grid structure; an interlayer dielectric layer covering the grid structure is formed on the substrate; that is to say, the outer side wall 06 is formed on the side wall of the SiN side wall 05 of the gate structure; the interlayer dielectric layer 07 covering the gate structure is formed on the substrate 01.
Further, as shown in fig. 1, the outer sidewall 06 in the first step of this embodiment extends to the upper surfaces of the source region epitaxial region (epi)02 and the drain region epitaxial region (epi) 02.
Further, in the present invention, in the first step of this embodiment, the inner sidewall spacer is a low-K dielectric layer. Still further, the dielectric constant of the inner sidewall spacer in the first step of this embodiment is about 5.
Further, in the present invention, the outer sidewall in the first step of this embodiment is a low-K dielectric layer. Still further, the dielectric constant of the outer wall in the first step of this embodiment is about 5.
Further, the thickness of the SiN sidewall in the first step of this embodiment is 2 to 8 nm.
Grinding the interlayer dielectric layer to expose the top of the polycrystalline silicon pseudo gate structure; further, the method for polishing the upper surface of the gate structure in the second step of this embodiment is a chemical mechanical polishing method.
As shown in fig. 1, in the second step, the interlayer dielectric layer 07 is polished by a chemical mechanical polishing CMP method until the top of the polysilicon dummy gate structure is exposed. Resulting in the structure shown in fig. 1.
Removing the SiN side wall; as shown in fig. 2, fig. 2 is a schematic structural view of the SiN spacer removed in the present invention. In the third step, a gap is formed between the inner side wall and the outer side wall after the SiN side wall 05 is removed.
Forming a plug for sealing the gap at the upper port of the gap, wherein the sealed gap between the inner side wall and the outer side wall forms an air side wall; as shown in fig. 3, fig. 3 is a schematic structural view of the present invention after plugs are formed at the upper ports of the voids. In the fourth step, the plug 08 is formed at the top (i.e., at the upper port) of the position (the gap) where the SiN sidewall 05 is removed, the plug 08 closes the gap at the top of the gap, and the air sidewall is formed between the inner sidewall and the outer sidewall, i.e., a space region located under the plug in fig. 3.
Further, the plug in step four of this embodiment is one of silicon nitride or silicon oxide.
Fifthly, removing the polycrystalline silicon pseudo gate structure and the gate oxide layer, and forming a groove at the removed position; as shown in fig. 4, fig. 4 is a schematic structural view of the polysilicon dummy gate structure removed in the present invention. In the fifth step, the polysilicon dummy gate structure is removed to form a groove as shown in fig. 4.
Sixthly, forming interface layers at the bottom and the side wall of the groove; forming a work function layer in the groove; as shown in fig. 5, fig. 5 is a schematic structural diagram of the present invention after forming an interface layer and a work function layer in a groove. In the sixth step, the interface layer 09 formed in the groove covers the bottom and the sidewall of the groove, and further, the interface layer in the sixth step extends to the upper side of the interlayer dielectric layer. In the sixth step, a work function layer 10 is further formed on the interface layer in the groove, and further, the work function layer in the sixth step of this embodiment is an HfO2 layer.
Filling metal in the groove, and then flattening the surface of the MOS structure to form a metal gate; as shown in fig. 6, fig. 6 is a schematic structural diagram illustrating the formation of a metal gate in a groove according to the present invention. In the seventh step, metal is filled in the groove, then the upper surface of the MOS structure is ground by using a chemical mechanical polishing method, the upper surface is planarized, and the metal in the ground groove forms a metal gate 11.
Step eight, carrying out back etching on the metal gate, and then forming a silicon nitride plug in a back etching area; as shown in fig. 7, fig. 7 is a schematic structural view after forming a silicon nitride plug according to the present invention. In the eighth step, the upper end of the metal gate 11 is etched back first, and then a silicon nitride plug 12 is formed in the etched back region.
And step nine, forming metal contact lines on the grid structure and the source region epitaxial region and the drain region epitaxial region. As shown in fig. 8, fig. 8 is a schematic structural diagram illustrating the formation of metal contact lines on the gate structure and the epitaxial regions of the source region and the drain region in the present invention. In this step nine, metal contact lines 13 are formed on the gate structure and the source region epitaxial region and the drain region epitaxial region.
In summary, in the manufacturing process of the FinFET, the air sidewall is formed at the gate sidewall of the MOS structure to reduce the parasitic capacitance. Because the dielectric constant of air is 1, the dielectric constant is much smaller than that of a low-K dielectric layer with the dielectric constant of about 5 and SiN with the dielectric constant of about 7.4, and the capacitance between the gate and the contact hole and the parasitic capacitance between the gate and the source-drain epitaxy are favorably reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (11)

1. The manufacturing method of the air side wall for reducing the parasitic capacitance of the FinFET device is characterized by at least comprising the following steps:
step one, providing an MOS structure, wherein the MOS structure at least comprises: a substrate; a source region epitaxial region and a drain region epitaxial region on the substrate; the grid structure is positioned between the source region epitaxial region and the drain region epitaxial region; the gate structure includes at least: the gate oxide layer, a polycrystalline silicon pseudo gate structure positioned on the gate oxide layer, an inner side wall attached to the side wall of the polycrystalline silicon pseudo gate structure, and an SiN side wall attached to the inner side wall and covering the top of the polycrystalline silicon pseudo gate structure;
an outer side wall is formed on the side wall of the SiN side wall of the grid structure; an interlayer dielectric layer covering the grid structure is formed on the substrate;
grinding the interlayer dielectric layer to expose the top of the polycrystalline silicon pseudo gate structure;
removing the SiN side wall, and forming a gap between the inner side wall and the outer side wall of the polycrystalline silicon pseudo gate structure;
forming a plug for sealing the gap at the upper port of the gap, wherein the sealed gap between the inner side wall and the outer side wall forms an air side wall;
fifthly, removing the polycrystalline silicon pseudo gate structure and the gate oxide layer, and forming a groove at the removed position;
sixthly, forming interface layers at the bottom and the side wall of the groove; forming a work function layer in the groove;
filling metal in the groove, and then flattening the surface of the MOS structure to form a metal gate;
step eight, carrying out back etching on the metal gate, and then forming a silicon nitride plug in a back etching area;
and step nine, forming metal contact lines on the grid structure and the source region epitaxial region and the drain region epitaxial region.
2. The method for fabricating an air sidewall spacer of a FinFET for reducing parasitic capacitance of claim 1, wherein: and the inner side wall in the first step is a low-K dielectric layer.
3. The method for fabricating an air sidewall spacer of a FinFET for reducing parasitic capacitance of claim 1, wherein: and the outer side wall in the first step is a low-K dielectric layer.
4. The method for fabricating an air sidewall spacer of a FinFET for reducing parasitic capacitance of claim 1, wherein: the dielectric constant value of the inner side wall in the first step is about 5.
5. The method for fabricating an air sidewall spacer of a FinFET for reducing parasitic capacitance of claim 1, wherein: the dielectric constant of the outer wall in step one is about 5.
6. The method for fabricating an air sidewall spacer of a FinFET for reducing parasitic capacitance of claim 1, wherein: the thickness of the SiN side wall in the first step is 2-8 nm.
7. The method for fabricating an air sidewall spacer of a FinFET for reducing parasitic capacitance of claim 1, wherein: and the outer side wall in the first step extends to the upper surfaces of the source region epitaxial region and the drain region epitaxial region.
8. The method for fabricating an air sidewall spacer of a FinFET for reducing parasitic capacitance of claim 1, wherein: and in the second step, the method for grinding the upper surface of the grid structure is a chemical mechanical grinding method.
9. The method for fabricating an air sidewall spacer of a FinFET for reducing parasitic capacitance of claim 1, wherein: the plug in the fourth step is one of silicon nitride or silicon oxide.
10. The method for manufacturing the air side wall for reducing the parasitic capacitance of the FinFET device according to claim 1, wherein: and the interface layer in the sixth step extends to the upper part of the interlayer dielectric layer.
11. The method for manufacturing the air side wall for reducing the parasitic capacitance of the FinFET device according to claim 1, wherein: and the work function layer in the sixth step is an HfO2 layer.
CN202110720475.8A 2021-06-28 2021-06-28 Air side wall manufacturing method for reducing parasitic capacitance of FinFET device Pending CN113517196A (en)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104733319A (en) * 2013-12-20 2015-06-24 中国科学院微电子研究所 MOS transistor structure and manufacturing method thereof
US20170077031A1 (en) * 2015-09-16 2017-03-16 United Microelectronics Corp. Semiconductor device and manufacturing method thereof
CN106920771A (en) * 2015-12-28 2017-07-04 中芯国际集成电路制造(北京)有限公司 The preparation method of metal gate transistor source-drain area contact plug
CN108666267A (en) * 2017-04-01 2018-10-16 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN108682652A (en) * 2018-05-21 2018-10-19 上海华力集成电路制造有限公司 The manufacturing method of metal gates
CN109216451A (en) * 2017-07-03 2019-01-15 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
US20200035804A1 (en) * 2018-07-27 2020-01-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and manufacturing method thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104733319A (en) * 2013-12-20 2015-06-24 中国科学院微电子研究所 MOS transistor structure and manufacturing method thereof
US20170077031A1 (en) * 2015-09-16 2017-03-16 United Microelectronics Corp. Semiconductor device and manufacturing method thereof
CN106920771A (en) * 2015-12-28 2017-07-04 中芯国际集成电路制造(北京)有限公司 The preparation method of metal gate transistor source-drain area contact plug
CN108666267A (en) * 2017-04-01 2018-10-16 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN109216451A (en) * 2017-07-03 2019-01-15 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN108682652A (en) * 2018-05-21 2018-10-19 上海华力集成电路制造有限公司 The manufacturing method of metal gates
US20200035804A1 (en) * 2018-07-27 2020-01-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and manufacturing method thereof

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