CN104717155A - Circuit and method for processing network flow in sampling system - Google Patents
Circuit and method for processing network flow in sampling system Download PDFInfo
- Publication number
- CN104717155A CN104717155A CN201310689708.8A CN201310689708A CN104717155A CN 104717155 A CN104717155 A CN 104717155A CN 201310689708 A CN201310689708 A CN 201310689708A CN 104717155 A CN104717155 A CN 104717155A
- Authority
- CN
- China
- Prior art keywords
- control module
- module
- team
- timing
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention relates to a circuit and method for processing network flow in a sampling system. The circuit for processing the network flow in the sampling system comprises a processor interface module (1), a queue unit module (2), an arbitration module (3), an input-output control module (4) and a memory module (5). The circuit and method control the minimum sending time interval of adjacent data frames in the same queue by utilizing parameters and achieves network flow processing, the problem of sampling data loss caused by burst flow in a high-speed network is solved, and the stability and reliability of the sampling system are ensured. The circuit and method for processing the network flow in the sampling system have the advantages of being wide in application range, good in universality and high in transferability.
Description
Technical field
The invention belongs to applications of computer network field, relate to the network traffics treatment circuit in a kind of sampling system and method.
Background technology
Along with fast development and the application of high speed real-time network technology, effective analysis of network service flow and statistical demand are increased day by day, and reliable and stable sampling system is the prerequisite ensureing traffic analysis.
Express network as (1394B, FC, ten thousand mbit ethernets etc.) because mostly its Business Stream is event trigger type; have certain sudden, and the data captured that the burst flow of high bandwidth often can cause are discontinuous, sampled data is unstable, even lose problem.The object of the invention addresses these problems exactly.
Summary of the invention
To solve prior art burst flow, goal of the invention: provide the network traffics treatment circuit in a kind of sampling system and method, loses that the data captured caused are discontinuous, sampled data is unstable, even lose problem.
Technical scheme of the present invention:
Network traffics treatment circuit in a kind of sampling system, its special character is, comprise: processor interface module (1), N number of queue unit module (2), arbitration modules (3), input/output control module (4) and memory module (5), N number of natural number for being more than or equal to 1;
Each queue unit module includes configuration register (201), timing controller (202) and the control module (203) that goes out to join the team; In each queue unit module, configuration register (201) configures the maximum of this queue unit module clocking internal controller (202), and the output of timing controller (202) is connected with the control module (203) that goes out to join the team in this queue unit module; The output of the control module (203) that goes out to join the team of each queue unit module is all connected with arbitration modules (3);
Processor interface module (1) is connected with the configuration register of queue unit module (2); Input/output control module (4) is connected with arbitration modules (3) with memory module (5), the control module (203) that goes out to join the team respectively.
A network traffics processing method in sampling system, its special character is, comprises the steps:
Step 1, processor interface module (1) are configured the configuration register (201) in N number of queue unit module (2), arrange the minimum interval GAPmin that in N number of queue unit module, adjacent data frames sends respectively;
Step 2, input/output control module (4) wait-receiving mode Frame;
Step 3, when input/output control module (4) receives the first frame data, be stored into memory module (5), and transmit into team request provide control module of joining the team (203), the control module (203) that goes out to join the team sends out team asks to arbitration modules (3), the control module (203) that goes out to join the team notifies input/output control module (4) after obtaining the mandate of arbitration modules (3), the first frame data that input/output control module (4) will be stored in memory module (5) take out and send, notify out control module (203) startup timing controller (202) of joining the team simultaneously, start timing,
Step 4, timing controller (202) timing are to minimum interval GAPmin, and input/output control module (4) does not also receive new Frame, perform step 6; Otherwise, perform step 5;
Step 5, the new Frame that input/output control module (4) receives is stored into memory module (5), input/output control module (4) sends enqueue request to the control module (203) that goes out to join the team simultaneously, wait for that timing controller (202) timing is to minimum interval GAPmin, timing controller (202) notifies out control module (203) of joining the team, the control module (203) that goes out to join the team sends out team asks to arbitration modules (3), after the control module (203) that goes out to join the team obtains the mandate of arbitration modules (3), cancel out group request signal, timing control module (202) stops timing, these frame data to take out and after sending, timing control module (202) restarts timing from memory module (5) by input/output control module (4), repeat step 4,
Step 6, timing control module (202) continue the timing t time; If subsequent data frame arrives within the t time, then perform step 5, t is by artificially setting;
If subsequent data frame does not still arrive, then timing control module (202) stops timing; Repeat step 2.
Above-mentioned minimum interval GAPmin is the integral multiple of 100us, and time range is 100us-1600ms.
Technique effect of the present invention is:
Versatility is good: this invention can be widely used in the sampling system of the multiple high-speed bus network such as 1394B, FC, ten thousand mbit ethernets, the discontinuous and data loss problem of the sampled data preventing burst flow from causing.
Flexible and efficient: this project organization is simple, completely by hardware implementing, without the need to software intervention, and transparent to upper layer application, ensure stability and the reliability of data sampling, possess higher use flexibility.
Portable strong: this design processor interface only need add bus interface logic and can hang in polytype bus; In addition, each queue have independently configuration register, the parametrization that greatly can improve this module is multiplexing; In addition, the present invention can choose the quantity N of queue unit module flexibly according to type of message; The capacity of the memory of each queue assignment can be chosen flexibly according to the frame length of various application.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of network traffics treatment circuit of the present invention;
Wherein, 1-processor interface module, 2-queue unit module, 3-arbitration modules, 4-input/output control module, 5-memory module.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
Refer to Fig. 1, it is the theory diagram of network traffics treatment circuit of the present invention.
A network traffics treatment circuit in sampling system, comprises processor interface module 1, N number of queue unit module 2, arbitration modules 3, input/output control module 4 and memory module 5;
Each queue unit module includes configuration register 201, timing controller 202 and the control module 203 that goes out to join the team; In each queue unit module, configuration register 201 configures the maximum of this queue unit module clocking internal controller 202, and the output of timing controller 202 is connected with the control module 203 that goes out to join the team in this queue unit module; The output of the control module 203 that goes out to join the team of each queue unit module is all connected with arbitration modules 3;
Processor interface module 1 is connected with the configuration register of queue unit module 2; Input/output control module 4 is connected with arbitration modules 3 with memory module 5, the control module 203 that goes out to join the team respectively.
Configuration register 201 controls in queue from a upper dataframe, and be the integral multiple of 100us to the time interval waited for needed for next dataframe, time interval scope is 100us-1600ms.
Timing controller 202 carries out timing control according to the value of configuration register to each frame data in queue unit module, when timing reaches the value of configuration register, sends out team's request to arbitration modules.
Contain IENA KEY in the frame head of the network data frame of input, the corresponding unique queue number of each IENA KEY and queue unit module, this circuit supports at most N number of IENA KEY, can choose the value of N according to practical application; The Frame of each queue adopts the principle of first in first out to access; Input/output control module 4 inside comprises frame count function, for the frame number of storage current in record storage module 5.Whenever having frame data to join the team, adding 1, subtracting 1 when there being frame data to go out group; When memory is full, forbids that new frame is joined the team, prevent memory from overflowing.
The Frame of coming in, when detecting that network data frame inputs, is stored into memory module 5 by input/output control module 4, and simultaneously according to the IENA KEY of this frame, the frame count value of queue belonging to this frame is added 1 by instruction queue unit module 2.What send from queue unit module 2 according to the priority of often kind of type of message when arbitration modules 3 goes out team's request to select optimum request, then export to input/output control module 4, this frame to take out according to IENA KEY and sends by input/output control module 4 from memory 5.
A network traffics processing method in sampling system, comprises the steps:
Step 1, processor interface module (1) are configured the configuration register (201) in N number of queue unit module (2), arrange the minimum interval GAPmin that in N number of queue unit module, adjacent data frames sends respectively; Minimum interval GAPmin is the integral multiple of 100us, and time range is 100us-1600ms;
Step 2, input/output control module (4) wait-receiving mode Frame;
Step 3, when input/output control module (4) receives the first frame data, be stored into memory module (5), and transmit into team request provide control module of joining the team (203), the control module (203) that goes out to join the team sends out team asks to arbitration modules (3), the control module (203) that goes out to join the team notifies input/output control module (4) after obtaining the mandate of arbitration modules (3), the first frame data that input/output control module (4) will be stored in memory module (5) take out and send, notify out control module (203) startup timing controller (202) of joining the team simultaneously, start timing,
Step 4, timing controller (202) timing are to minimum interval GAPmin, and input/output control module (4) does not also receive new Frame, perform step 6; Otherwise, perform step 5;
Step 5, the new Frame that input/output control module (4) receives is stored into memory module (5), input/output control module (4) sends enqueue request to the control module (203) that goes out to join the team simultaneously, wait for that timing controller (202) timing is to minimum interval GAPmin, timing controller (202) notifies out control module (203) of joining the team, the control module (203) that goes out to join the team sends out team asks to arbitration modules (3), after the control module (203) that goes out to join the team obtains the mandate of arbitration modules (3), cancel out group request signal, timing control module (202) stops timing, these frame data to take out and after sending, timing control module (202) restarts timing from memory module (5) by input/output control module (4), repeat step 4,
Step 6, timing control module (202) continue the timing t time; If subsequent data frame arrives within the t time, then perform step 5, t is by artificially setting;
If subsequent data frame does not still arrive, then timing control module (202) stops timing; Repeat step 2.
Claims (3)
1. the network traffics treatment circuit in a sampling system, it is characterized in that, comprise: processor interface module (1), N number of queue unit module (2), arbitration modules (3), input/output control module (4) and memory module (5), N number of natural number for being more than or equal to 1;
Each queue unit module includes configuration register (201), timing controller (202) and the control module (203) that goes out to join the team; In each queue unit module, configuration register (201) configures the maximum of this queue unit module clocking internal controller (202), and the output of timing controller (202) is connected with the control module (203) that goes out to join the team in this queue unit module; The output of the control module (203) that goes out to join the team of each queue unit module is all connected with arbitration modules (3);
Processor interface module (1) is connected with the configuration register of queue unit module (2); Input/output control module (4) is connected with arbitration modules (3) with memory module (5), the control module (203) that goes out to join the team respectively.
2. the network traffics processing method in sampling system, is characterized in that, comprise the steps:
Step 1, processor interface module (1) are configured the configuration register (201) in N number of queue unit module (2), arrange the minimum interval GAPmin that in N number of queue unit module, adjacent data frames sends respectively;
Step 2, input/output control module (4) wait-receiving mode Frame;
Step 3, when input/output control module (4) receives the first frame data, be stored into memory module (5), and transmit into team request provide control module of joining the team (203), the control module (203) that goes out to join the team sends out team asks to arbitration modules (3), the control module (203) that goes out to join the team notifies input/output control module (4) after obtaining the mandate of arbitration modules (3), the first frame data that input/output control module (4) will be stored in memory module (5) take out and send, notify out control module (203) startup timing controller (202) of joining the team simultaneously, start timing,
Step 4, timing controller (202) timing are to minimum interval GAPmin, and input/output control module (4) does not also receive new Frame, perform step 6; Otherwise, perform step 5;
Step 5, the new Frame that input/output control module (4) receives is stored into memory module (5), input/output control module (4) sends enqueue request to the control module (203) that goes out to join the team simultaneously, wait for that timing controller (202) timing is to minimum interval GAPmin, timing controller (202) notifies out control module (203) of joining the team, the control module (203) that goes out to join the team sends out team asks to arbitration modules (3), after the control module (203) that goes out to join the team obtains the mandate of arbitration modules (3), cancel out group request signal, timing control module (202) stops timing, these frame data to take out and after sending, timing control module (202) restarts timing from memory module (5) by input/output control module (4), repeat step 4,
Step 6, timing control module (202) continue the timing t time; If subsequent data frame arrives within the t time, then perform step 5, t is by artificially setting;
If subsequent data frame does not still arrive, then timing control module (202) stops timing; Repeat step 2.
3. the network traffics processing method in a kind of sampling system according to claim 2, is characterized in that, in step 1, minimum interval GAPmin is the integral multiple of 100us, and time range is 100us-1600ms.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310689708.8A CN104717155B (en) | 2013-12-15 | 2013-12-15 | Network traffics process circuit and method in a kind of sampling system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310689708.8A CN104717155B (en) | 2013-12-15 | 2013-12-15 | Network traffics process circuit and method in a kind of sampling system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104717155A true CN104717155A (en) | 2015-06-17 |
| CN104717155B CN104717155B (en) | 2017-10-24 |
Family
ID=53416130
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310689708.8A Active CN104717155B (en) | 2013-12-15 | 2013-12-15 | Network traffics process circuit and method in a kind of sampling system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104717155B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1466348A (en) * | 2002-06-15 | 2004-01-07 | 华为技术有限公司 | High speed link control protocol transmission processing/module and data processing/method |
| US20040103397A1 (en) * | 2002-11-22 | 2004-05-27 | Manisha Agarwala | Maintaining coherent synchronization between data streams on detection of overflow |
| US7508893B1 (en) * | 2004-06-04 | 2009-03-24 | Integrated Device Technology, Inc. | Integrated circuits and methods with statistics-based input data signal sample timing |
| CN101924931A (en) * | 2010-05-20 | 2010-12-22 | 长沙闿意电子科技有限公司 | Digital television PSI/SI information distributing system and method |
| CN102546843A (en) * | 2012-01-17 | 2012-07-04 | 厦门雅迅网络股份有限公司 | Method for achieving UART (universal asynchronous receiver/transmitter) communication interfaces through software simulation |
| CN103077147A (en) * | 2012-12-31 | 2013-05-01 | 北京石竹科技股份有限公司 | Linked list-based full-function 1553B bus IP (Internet Protocol) core |
| CN103209137A (en) * | 2013-03-21 | 2013-07-17 | 国家电网公司 | Configurable high-accuracy control system of time interval frame release Ethernet interface |
-
2013
- 2013-12-15 CN CN201310689708.8A patent/CN104717155B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1466348A (en) * | 2002-06-15 | 2004-01-07 | 华为技术有限公司 | High speed link control protocol transmission processing/module and data processing/method |
| US20040103397A1 (en) * | 2002-11-22 | 2004-05-27 | Manisha Agarwala | Maintaining coherent synchronization between data streams on detection of overflow |
| US7508893B1 (en) * | 2004-06-04 | 2009-03-24 | Integrated Device Technology, Inc. | Integrated circuits and methods with statistics-based input data signal sample timing |
| CN101924931A (en) * | 2010-05-20 | 2010-12-22 | 长沙闿意电子科技有限公司 | Digital television PSI/SI information distributing system and method |
| CN102546843A (en) * | 2012-01-17 | 2012-07-04 | 厦门雅迅网络股份有限公司 | Method for achieving UART (universal asynchronous receiver/transmitter) communication interfaces through software simulation |
| CN103077147A (en) * | 2012-12-31 | 2013-05-01 | 北京石竹科技股份有限公司 | Linked list-based full-function 1553B bus IP (Internet Protocol) core |
| CN103209137A (en) * | 2013-03-21 | 2013-07-17 | 国家电网公司 | Configurable high-accuracy control system of time interval frame release Ethernet interface |
Non-Patent Citations (1)
| Title |
|---|
| 王治； 田泽: "一种高性能AFDX监控卡的实现技术研究", 《计算机技术与发展》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104717155B (en) | 2017-10-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI480728B (en) | Squelch filtration to limit false wakeups | |
| TWI518497B (en) | Apparatus, method and system to provide link power savings with state retention | |
| US9110668B2 (en) | Enhanced buffer-batch management for energy efficient networking based on a power mode of a network interface | |
| CN111277672A (en) | Non-blocking input and output model-based energy Internet of things data acquisition method and software gateway | |
| US20170068628A1 (en) | Reducing ethernet latency in a multi-server chassis | |
| EP2963874A1 (en) | Data scheduling and switching method, apparatus, and system | |
| US10324513B2 (en) | Control of peripheral device data exchange based on CPU power state | |
| CN105677608A (en) | Multi-master RS485 bus arbitration method and system | |
| CN103136163B (en) | Protocol processor chip capable of allocating and achieving FC-AE-ASM and FC-AV protocol | |
| CN104714907B (en) | A kind of pci bus is converted to ISA and APB bus design methods | |
| JPWO2014103144A1 (en) | Interface device and memory bus system | |
| WO2019184455A1 (en) | Information transmission method and apparatus, device and storage medium | |
| TW201324175A (en) | Universal Serial Bus device and method for power management | |
| US20140006826A1 (en) | Low power low frequency squelch break protocol | |
| CN111177065A (en) | Multi-chip interconnection method and device | |
| EP4138336A1 (en) | Communication data processing method and apparatus | |
| JP2013524638A (en) | Efficient simultaneous sampling at various rates | |
| CN101299165B (en) | Method and system for implementing generalized system stutter | |
| US20160162421A1 (en) | Ltr/obff design scheme for ethernet adapter application | |
| CN204178172U (en) | A kind of universal embedded bus control equipment based on DSP and FPGA | |
| US8982757B2 (en) | Nonlinear power state transitioning | |
| US20140095752A1 (en) | Interrupt suppression strategy | |
| CN107517167B (en) | Data transmission control method and device and SoC chip | |
| CN107132903B (en) | Energy-saving management implementation method, device and network equipment | |
| CN105807886A (en) | Chip arousing system, chip arousing method and mobile terminal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20221205 Address after: Room S303, Innovation Building, No. 25, Gaoxin 1st Road, Xi'an, Shaanxi 710075 Patentee after: XI'AN XIANGTENG MICROELECTRONICS TECHNOLOGY Co.,Ltd. Address before: No.15, Jinye 2nd Road, Xi'an, Shaanxi 710119 Patentee before: 631ST Research Institute OF AVIC |
|
| TR01 | Transfer of patent right |