CN105024942B - A kind of dynamic flow monitoring method - Google Patents
A kind of dynamic flow monitoring method Download PDFInfo
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- CN105024942B CN105024942B CN201510287647.1A CN201510287647A CN105024942B CN 105024942 B CN105024942 B CN 105024942B CN 201510287647 A CN201510287647 A CN 201510287647A CN 105024942 B CN105024942 B CN 105024942B
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- token
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/20—Traffic policing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/215—Flow control; Congestion control using token-bucket
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/52—Queue scheduling by attributing bandwidth to queues
- H04L47/522—Dynamic queue service slot or variable bandwidth allocation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/52—Queue scheduling by attributing bandwidth to queues
- H04L47/527—Quantum based scheduling, e.g. credit or deficit based scheduling or token bank
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/62—Queue scheduling characterised by scheduling criteria
- H04L47/6245—Modifications to standard FIFO or LIFO
Abstract
The present invention discloses a kind of dynamic flow monitoring method, and the design takes control and forwarding separation architecture in its structure, realizes that dynamic configures hardware relevant parameter flexibly control output flow size by controller, meets design real-time and requirement on flexibility;Token bucket group possesses same time granularity under normal circumstances, that is, sends token signal from scheduler module synchronization to token bucket group;When having burst flow, hardware carries out self-adjusting by Dynamic Bandwidth Allocation, i.e. virtual bucket can be issued an order board signal dispatching to corresponding token bucket group by scheduler module in very short time, and then shorten and issue an order the board time cycle, accelerate message transferring speed, in the case of having the surge of long-time flow, by feedback signal, user makes corresponding actions by controller and handles;Designated port uninterrupted can flexibly be monitored according to the classification of different port incoming message.
Description
Technical field
The invention belongs to network data processing technique, and in particular to a kind of dynamic flow monitoring method.
Background technology
Internet becomes the most important information infrastructure of human society, as interconnection technique continues to develop, net at present
Caused a series of problems also gradually highlights in network operation, wherein prominent is by excessive the triggered net of network traffics
Network congestion;The network equipment and application also increasingly complicate at the same time, therefore network traffics are efficiently managed in people's active demand
Reason and monitoring.But conventional method is come to control of network flow quantity, be by control logic and forwarding logic be all coupling in software or
On hardware platform so that its complexity is high, flexibility is low, limits ability of the network equipment to data processing.
The content of the invention
The technical problems to be solved by the invention are that there are very flexible, complexity are high for existing network flow control methods
A kind of and problems such as data-handling efficiency is low, there is provided dynamic flow monitoring method.
To solve the above problems, the present invention is achieved by the following technical solutions:
A kind of dynamic flow monitoring method, includes following operating procedure:
Step 1, controller sends the order of parameter configuration to FPGA;
Step 2, after FPGA receives order, be identified, if the order of oneself is destined to according to communication protocol into
Row parsing, if otherwise abandoning;
Step 3, the effective information in extraction order, and the address information in effective information is sought in FPGA memory headrooms
Location, addressing are completed effective information writing address space i.e.;
Step 4, when detecting that memory headroom updates the data, then using data read-out as token bucket and token polling tune
The configuration parameter of degree;
Step 5, after the parameter configuration for completing token bucket and token polling scheduling, start to receive from different input ports
Message, and the message inputted according to different port, are different type by packet labeling, and be stored in corresponding FIFO;
Step 6, when token quantity is greater than or equal to message byte length in token bucket, then allow current message by,
Message is read from FIFO at this time to be forwarded to, and the token of corresponding message byte length quantity is reduced from token bucket;In season
When token quantity is less than message byte length in board bucket, then wait;
Step 7, when some length of buffer queue for detecting FIFO is greater than or equal to the threshold value of setting, then give token wheel
Ask scheduling and send dispatch request, while start time-out counter;
Step 8, when reaching the time of setting, if the length of buffer queue is less than the threshold value of setting, self-adjusting is illustrated
Success, then return to step 7, wait other buffer queues of FIFO to initiate scheduling;If the length of buffer queue is still more than setting
Threshold value, then illustrate self-adjusting fail, FPGA to controller send feedback signal;
Step 9, after receiving dispatch request, the board path of issuing an order for being originally directed toward virtual bucket is dispatched to this by token polling scheduling
FIFO。
Effective information in step 3 in extraction order includes address information, data message and action message.
Step 9 still further comprises Conflicts management strategy, i.e.,:
If some buffer queue is carrying out self-adjusting period, another buffer queue also sends self-adjusting request letter
Number, then by the dispatching algorithm designed, wait a upper buffer queue self-adjusting to complete to post-process the request that next queue is initiated;
In the case of single virtual bucket, if synchronization has two or more buffer queues to be dispatched to token polling
Dispatch request is initiated, then without self-adjusting, layer controller transmission feedback signal, corresponding actions are made by controller directly up
Processing.
The number of virtual bucket described in step 9 is one or more.
In step 9, if the number of scheduling is more than 1 time, token path is dispatched to initiation scheduling by current FIFO please
Seek FIFO.
In step 8, after controller receives the feedback signal of FPGA transmissions, controller can be as needed to parameter configuration
Order is modified.
Compared with prior art, the present invention has following features:
1. with the thought of SDN frameworks so that key-course is separated with forwarding, while is used as using FPGA and is realized that hardware is patrolled
Volume design and forwarding platform, make full use of FPGA processing data " parallel computation " advantage, improve processing data efficiency;
2. establishing good feedback and Conflicts management strategy, key-course receives forwarding and uploads abnormal signal, user Ke Tong
Cross regulation and control of the controller dynamic to output flow;
3. hardware realizes flexible Dynamic Bandwidth Allocation using multi-stage pipeline token bucket and the design of polling dispatching strategy, more
To successfully manage the situation of burst flow.
Brief description of the drawings
Fig. 1 is based on FPGA traffic monitoring collectivity Scheme Design figures for the present invention.
Fig. 2 (is once dispatched) for the present invention based on FPGA traffic monitoring hardware programs design flow diagram.
Fig. 3 in order to control device to hardware parameter configuration schematic diagram.
Fig. 4 is 1 token polling scheduling strategy schematic diagram.
Fig. 5 is M token polling scheduling strategy schematic diagram.
Embodiment
A kind of dynamic flow monitoring method, easily and efficiently dynamic is realized by key-course and the separated framework of forwarding
Traffic monitoring, such as Fig. 1;Hardware realizes flexible dynamic bandwidth point using FPGA platform design token bucket algorithm and dispatch circuit
Match somebody with somebody, successfully manage burst flow situation, such as Fig. 2.It specifically includes following operating procedure:
Step 1, by taking netmagic platforms as an example, by top level control device by being connected between top level control device and bottom FPGA
Communication protocol, to FPGA send parameter configuration order, such as Fig. 3.By operating in communication protocols between local host and FPGA platform
View (NMAC agreements) provides programmable interface, initiates to establish the request of connection from controller to hardware platform, by holding three times
Hand is established with bottom FPGA and connected, and the interaction control interface of close friend is realized, easy to efficient, quick access FPGA internal address spaces
With receive bottom FPGA feedback informations.
Step 2, after FPGA receives order, be identified, if the order of oneself is destined to according to communication protocol into
Row parsing, if otherwise abandoning.
Step 3, according to the form of communication protocol and rule parsing order, effective information (address, data in extraction order
With action etc.), address information in effective information is addressed in FPGA memory headrooms, finds the address space, and addressing is completed
Data message is write to the memory headroom (RAM0, RAM1 ... ..., RAMn) pointed by the address.
Step 4,3 token bucket groups in flow-control module and token polling scheduler module detection specified memory space
Whether (RAM0, RAM1..RAMn) has data update.When detecting that corresponding internal storage location updates the data, then read and specify address
Data message in memory headroom, and using data read-out as token bucket and token polling scheduling configuration parameter, complete token bucket and
Token polling scheduling parameter configures.
Designing token bucket configurable parameter includes the increased time interval T (time granularity) of token, T cycles into token bucket
Highest number of tokens (bucket depth) L that can be placed in the token number N of addition, token bucket;Polling tokens polling dispatching timing parameter
Time。
Step 5, after completing the parameter initialization to flow-control module and token scheduling module, start to receive from input
The message of control module.The message inputted according to different port, is different type by the packet labeling of input.In the present embodiment
In, three input ports port1, port2, port3 are set, while be Class1 (PR1), type 2 by corresponding packet labeling
(PR2), type 3 (PR3).As 3 ' b001 are represented by the message of a port input.According to different input ports by message
During labeled as different type, can also actual demand, be revised as the messages such as different aforementioned sources, different type.
Each type message is stored in corresponding FIFO cachings respectively, and sets the threshold value Thi (i=1,2,3) of FIFO.
In the present embodiment, FIFO buffer interfaces use dual-port design, i.e. read-write is carried out at the same time, and improves message processing speed;If FIFO
There is spilling then to abandon current message.Buffering queue length detection module exports signal usedw according to FIFO, detects FIFO's in real time
Queue length (Length).
Step 6, when token quantity meets certain condition in token bucket, i.e., token quantity is greater than or equal to message in bucket
During byte length, then allow current message by reading message forwarding from caching FIFO, and reduce respective counts in token bucket
Measure token;Otherwise wait for.
In the present embodiment, flow-control module is made of 3 token bucket groups and 1 virtual bucket, and each token bucket group is total to
With a token signal, token polling scheduling sends order with cycle T according to counter CT to 3 token bucket groups and 1 virtual bucket
Board signal.The bucket depth L of 3 token bucket groups is identical, and the T cycles are a for the token added in PR1, PR2, PR3 token bucket group to type
Number is respectively N1, N2, N3.If desired extensive token bucket group completes flow control, then sets the virtual bucket of multiple quantity, can be at the same time
Meet multiple token bucket group schedulings.
When detecting FIFO non-NULLs (empty==0), token bucket group is corresponded to by the message length extracted (byte) and group
Token quantity compares and (is incremented by downwards relatively from the 1st bucket) in interior token bucket, if k-th bucket token quantity meets, message
Sent from K barrels, while respective numbers token is reduced in K barrels;If not satisfied, then waiting there are enough tokens, report is retransmited
Text.Token bucket group realization principle is:When token polling dispatching state one (Current_state) counter is full (CT==time)
Then token signal Flag are sent to three token bucket groups, while by counter O reset (CT<=0) token group will after receiving signal
Token signal add_flag is added to put 1, bucket abandons token less than then plus token;State two (next_state) works as counter
Again count full (CT==time) and then send signal Flag to virtual bucket, next clock is by counter O reset (CT<=0) at the same time
Return state one (Current_state), that is, completing one cycle needs the 2T times.
Step 7, when detect FIFO the i-th length of buffer queue be greater than or equal to setting threshold value (length_i >=
When Thi), then dispatched to token polling and send request signal Req_i, while start time-out counter (Toc<=Toc+1);Token
After polling dispatching receives request signal, wait counters expire (CT in state two<=Sum), token letter will be sent to virtual bucket
Number path be dispatched to corresponding FIFO paths.
Step 8, after receiving dispatch request, the board path of issuing an order for being originally directed toward virtual bucket is dispatched to this by token polling scheduling
FIFO.The path that token signal will be sent to virtual bucket is dispatched to corresponding FIFO paths and keeps token polling scheduling to send order
The board signal period, T was constant.The each clock cycle count of time-out counter once, until count value is equal to stop value Sum, count by stopping
When, and reset counter and wait start next time.In the present embodiment, if M (M>1) secondary scheduling is then by token path by current FIFO
It is dispatched to and initiates dispatch request FIFO.Fig. 4 is 1 token polling scheduling strategy schematic diagram, and Fig. 5 dispatches plan for M token polling
Slightly schematic diagram.
Step 9, if being reached in the time of setting, detection caching fifo queue length is still greater than or equal to the threshold of setting
Value, then send feedback signal to controller.After controller receives feedback signal, corresponding actions are made according to actual needs.
Wait time-out counter to stop (Toc==Time), cancel request signal Req_i, while detection is current slow again
Fifo queue length Length_i and judgement and FIFO threshold value Thi sizes are rushed, if threshold value (the Length_i < less than setting
Thi), represent hardware " self-adjusting " success, when other queues are initiated to dispatch, then carry out two times scheduling, i.e., by current path tune
Degree is dispatched thereafter then to the buffer queue.If still above or equal to threshold value (Length_i >=Thi), illustrate " certainly
Adjustment " failure, while feedback signal Ret_i is sent to upper strata controller, controller receives the feedback letter that bottom FPGA is sent
After number Req_i, then respective handling action is made as needed, such as can be to hardware designated memory space (RAM0, RAM1...RAMn)
Different parameters change output bandwidth size is configured (in the case of meeting the requirements, to simplify hardware design, configure token scheduling module meter
Number device Time parameters are more convenient), or determine that controller is modification token bucket parameters or token polling scheduling meter by being actually needed
When parameter Time, adjust output bandwidth size;Still do not deal with.
Conflicts management strategy:1. during if some buffer queue is carrying out " self-adjusting ", another buffer queue
" self-adjusting " request signal is sent, then by the dispatching algorithm designed, waits a upper buffer queue " self-adjusting " to complete post processing
The request that next queue is initiated;2. if synchronization has two or more (single virtual bucket situation) buffer queues to order
Board polling dispatching initiates dispatch request, then without self-adjusting, layer controller transmission feedback signal, is done by controller directly up
Go out corresponding actions processing;3. if the multiple virtual buckets of setting, processing mode are analogized as above-mentioned.
The present invention design concept be:1. the design takes control and forwarding separation architecture in structure, simplify hardware design,
Realize that dynamic configures hardware relevant parameter flexibly control output flow size by controller according to the thought of SDN, meet to set
Count real-time and requirement on flexibility;2. token bucket group possesses same time granularity under normal circumstances, that is, same by scheduler module
One moment sent token signal to token bucket group, so not only can realize accurate and big model in the case of relatively low clock frequency
The flow control enclosed avoid the need for designing the complex situations of multiple timing logics in scheduler module at the same time so that user more
Fast to flow control, complex parameters configuration is reduced.3. have burst flow, hardware carries out self-regulated by Dynamic Bandwidth Allocation
Whole, i.e., virtual bucket can be issued an order board signal dispatching to corresponding token bucket group by scheduler module in very short time, and then is shortened and issued an order
The board time cycle, accelerates message transferring speed, and in the case of having the surge of long-time flow, by feedback signal, user passes through control
Device processed makes corresponding actions processing;4. it is big flexibly to monitor designated port flow according to the classification of different port incoming message
It is small.
Claims (6)
1. a kind of dynamic flow monitoring method, it is characterized in that, include following operating procedure:
Step 1, controller sends the order of parameter configuration to FPGA;
Step 2, after FPGA receives order, it is identified, is solved if the order of oneself is destined to according to communication protocol
Analysis, if otherwise abandoning;
Step 3, the effective information in extraction order, and the address information in effective information is addressed in FPGA memory headrooms,
Addressing is completed effective information writing address space i.e.;
Step 4, when detecting that memory headroom updates the data, then data read-out is dispatched as token bucket and token polling
Configure parameter;
Step 5, after the parameter configuration for completing token bucket and token polling scheduling, start to receive the report from different input ports
Text, and the message inputted according to different port, are different type by packet labeling, and be stored in corresponding FIFO;
Step 6, when token quantity is greater than or equal to message byte length in token bucket, then current message is allowed by this time
Message is read from FIFO to be forwarded to, and the token of corresponding message byte length quantity is reduced from token bucket;Work as token bucket
When middle token quantity is less than message byte length, then wait;
Step 7, when some length of buffer queue for detecting FIFO is greater than or equal to the threshold value of setting, then give token poll tune
Degree sends dispatch request, while starts time-out counter;
Step 8, when reaching the time of setting, if the length of buffer queue is less than the threshold value of setting, self-adjusting success is illustrated,
Then return to step 7, wait other buffer queues of FIFO to initiate scheduling;If the length of buffer queue is still more than the threshold of setting
Value, then illustrate that self-adjusting fails, FPGA sends feedback signal to controller;
Step 9, after receiving dispatch request, the board path of issuing an order for being originally directed toward virtual bucket is dispatched to this by token polling scheduling
FIFO。
2. a kind of dynamic flow monitoring method according to claim 1, it is characterized in that, having in extraction order in step 3
Effect information includes address information, data message and action message.
3. a kind of dynamic flow monitoring method according to claim 1, it is characterized in that, step 9 still further comprises conflict
Settlement mechanism, i.e.,
If some buffer queue is carrying out self-adjusting period, another buffer queue also sends self-adjusting request signal, then
By the dispatching algorithm designed, a upper buffer queue self-adjusting is waited to complete to post-process the request that next queue is initiated;
In the case of single virtual bucket, initiated if synchronization there are two or more buffer queues to be dispatched to token polling
Dispatch request, then without self-adjusting, layer controller transmission feedback signal, corresponding actions are made by controller directly up
Reason.
4. a kind of dynamic flow monitoring method according to claim 1 or 3, it is characterized in that, the virtual bucket described in step 9
Number be one or more.
5. a kind of dynamic flow monitoring method according to claim 1, it is characterized in that, in step 9, if the number of scheduling is big
When 1 time, then token path is dispatched to by current FIFO and initiates dispatch request FIFO.
6. a kind of dynamic flow monitoring method according to claim 1, it is characterized in that, in step 8, when controller receives
After the feedback signal that FPGA is sent, controller as needed can modify parameter configuration order.
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CN106453127A (en) * | 2016-11-18 | 2017-02-22 | 杭州华三通信技术有限公司 | Token processing method and device |
CN111641585B (en) * | 2016-12-29 | 2023-11-10 | 华为技术有限公司 | DDoS attack detection method and device |
CN107896197A (en) * | 2017-10-23 | 2018-04-10 | 深圳市楠菲微电子有限公司 | Method and apparatus, the storage medium of forwarding rate are measured in communication equipment |
CN107800644A (en) * | 2017-11-08 | 2018-03-13 | 中国人民解放军国防科技大学 | Dynamically configurable pipelined token bucket speed limiting method and device |
CN108399078B (en) * | 2018-03-19 | 2021-06-15 | 武汉斗鱼网络科技有限公司 | Message frequency limiting method, system, server and storage medium |
CN108768873B (en) * | 2018-05-29 | 2021-09-28 | 腾讯科技(深圳)有限公司 | Flow control method and related equipment |
CN112805971B (en) * | 2019-01-07 | 2022-07-12 | 华为技术有限公司 | Traffic shaping method and related equipment |
CN112559405B (en) * | 2020-12-11 | 2023-12-01 | 中国电子科技集团公司第四十七研究所 | Control method and device for multi-channel DMA (direct memory access) with token bucket structure |
CN113067778B (en) * | 2021-06-04 | 2021-09-17 | 新华三半导体技术有限公司 | Flow management method and flow management chip |
CN113301170B (en) * | 2021-07-27 | 2021-10-19 | 湖南三湘银行股份有限公司 | Data processing method based on communication node |
CN115174486A (en) * | 2022-06-01 | 2022-10-11 | 湖南天冠电子信息技术有限公司 | Message transmission method, system and storage medium |
CN115883472B (en) * | 2022-11-29 | 2024-05-03 | 重庆紫光华山智安科技有限公司 | Token issuing method and related device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101252789A (en) * | 2008-03-20 | 2008-08-27 | 华为技术有限公司 | Method and apparatus for allocating multi-frame dynamic band width |
CN101340393A (en) * | 2008-08-14 | 2009-01-07 | 杭州华三通信技术有限公司 | Multicast stream control method, system and field programmable gate array |
CN102301661A (en) * | 2009-01-29 | 2011-12-28 | 高通股份有限公司 | Method and apparatus for accomodating a receiver buffer to prevent data overflow |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5953998B2 (en) * | 2012-07-10 | 2016-07-20 | 富士通株式会社 | Packet processing apparatus and packet processing method |
US8930604B2 (en) * | 2012-07-17 | 2015-01-06 | Lsi Corporation | Reliable notification of interrupts in a network processor by prioritization and policing of interrupts |
-
2015
- 2015-05-29 CN CN201510287647.1A patent/CN105024942B/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101252789A (en) * | 2008-03-20 | 2008-08-27 | 华为技术有限公司 | Method and apparatus for allocating multi-frame dynamic band width |
CN101340393A (en) * | 2008-08-14 | 2009-01-07 | 杭州华三通信技术有限公司 | Multicast stream control method, system and field programmable gate array |
CN102301661A (en) * | 2009-01-29 | 2011-12-28 | 高通股份有限公司 | Method and apparatus for accomodating a receiver buffer to prevent data overflow |
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Application publication date: 20151104 Assignee: Guangxi Boyan Technology Co.,Ltd. Assignor: GUILIN University OF ELECTRONIC TECHNOLOGY Contract record no.: X2022450000542 Denomination of invention: A Dynamic Flow Monitoring Method Granted publication date: 20180508 License type: Common License Record date: 20221229 |