CN104716033A - Method for improving stability of key dimension of polycrystalline silicon grid electrode after etching chamber maintenance - Google Patents
Method for improving stability of key dimension of polycrystalline silicon grid electrode after etching chamber maintenance Download PDFInfo
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- CN104716033A CN104716033A CN201510125942.7A CN201510125942A CN104716033A CN 104716033 A CN104716033 A CN 104716033A CN 201510125942 A CN201510125942 A CN 201510125942A CN 104716033 A CN104716033 A CN 104716033A
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- etching
- polycrystalline silicon
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Abstract
A method for improving the stability of the key dimension of a polycrystalline silicon grid electrode after etching chamber maintenance comprises the steps that a plasma reacting chamber, an etching chamber and a semiconductor structure are provided; the polycrystalline silicon grid electrode is etched, the line width of the key dimension of the polycrystalline silicon grid electrode is controlled through the hard mask layer modification technology in the etching process of the polycrystalline silicon grid electrode; the plasma reacting chamber and the etching chamber are maintained, and plasma reacting and etching chamber inner wall components with the surfaces coated with Y2O3 coatings are replaced in the maintenance process; before the semiconductor structure is put into the reacting chamber to conduct polycrystalline silicon etching, silicon oxygen compounds are deposited on the surface of the inner wall component of the reacting chamber; the etching time of hard mask layer modification is adjusted according to the corresponding relation between the RF hours of the replaced etching chamber inner wall component and the processing time of the hard mask layer modification, and polycrystalline silicon grid electrode etching is conducted on the semiconductor structure in the maintained plasma reacting chamber and the etching chamber based on the adjusted etching time for the hard mask layer modification.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to a kind of method improving critical size of polycrystalline silicon grid electrode stability after etching cavity maintenance.
Background technology
Along with integrated circuit technique enters the very lagre scale integrated circuit (VLSIC) epoch, the process of integrated circuit, towards the structural development of 65nm and smaller szie, proposes higher finer technical requirement to wafer manufacturing process simultaneously.Wherein, the critical size of the polysilicon gate of wafer becomes the key parameter of etching polysilicon day by day, and described critical size of polycrystalline silicon grid electrode determines the service behaviour of device gate circuit, also more and more responsive on the impact of the yield of wafer.
In the etching technics of current widely used polysilicon gate, the size of critical size of polycrystalline silicon grid electrode is transmitted by hard mask layers (HM=hard mask) critical size size, and the critical size size adjustment of hard mask layer is decided by the modification of hard mask layer in polycrystalline silicon gate grid etching process step (Hard MaskTrim is called for short HM trim) the step time.Controlled the size of hard mask layers critical size by the etch period of adjustment HM trim processing step, thus reach the final critical size of polycrystalline silicon grid electrode size of control.
At present in mass wafer manufacture process, along with the continuous increase of wafer processing quantity, the internal environment of etching cavity can change thereupon, i.e. front a slice/batch wafer, on rear a slice/criticize the impact had to a certain degree, has memory effect.This memory effect is wherein mainly reflected in the accumulation of polymer, and namely on etch chamber wall, the type of polymer can be different according to the difference of plasma reactant and product, is mainly divided into inorganic polymer and organic polymer etc.The research of the memory effect caused in the accumulation of etch chamber wall for polymer in etching process at present has industrially given many kinds of measures and has had and well improved effect, wherein most popular as without wafer automatic dry method etch cleaned method (WaferlessAuto-Cleaning, be called for short WAC) and advanced etching cavity etching condition control (Advanced chambercondition control, be called for short AC3), the fluorine-containing NF3 gas of usual use removes mineral-type polymer, use O2 to remove organic polymer and etching cavity inwall after the cleaning precipitate the polymer of the similar silicon dioxide of one deck, these WAC-AC3 steps effectively can suppress the memory effect of cavity.
But, in order to maintain the continued reliability of wafer operation, etching operation cavity needs to carry out maintaining to etching cavity after number when carrying out etching operation certain RF, after being directed to the internal components that etching cavity more renews when maintaining, the initial stage that the RF of these WAC-AC3 technique after maintaining is shorter well can not maintain the consistency of etching cavity inwall environment.
At present, in 65nm and smaller szie industrial manufacturing process, after etching cavity maintaining, in order to test the stability of etching cavity, the stability of priority job a slice or a few wafer test etching cavity is needed before large-scale production, determine the etch period the need of adjustment HM trim according to the result of test, but (surface there is Y to the etching cavity internal wall member changed of etching cavity maintaining
2o
3the etching cavity inwall (chamber liner) of coating and etch chamber roof (top chamber)) be not brand-new parts, but the internal wall member crossed through clean unloaded after last maintenance maintenance, the internal wall member of these are different when using RF number due to the roughness on its surface different and show different difference with number during RF, this species diversity is after WAC-AC3 operation, the ability of the polymer of inwall device surface absorption is also different, during these different work RF, the difference of internal wall member on the Polymer adsorption ability that AC3 precipitates on of number makes for a slice of priority job or the impact of a few built-in testing wafer just is also different, and directly control (Advanced process control according to the advanced process used in etching polysilicon gate process at present, being called for short APC) system regulation polycrystalline silicon etching process parameter can make a slice of priority job or a few wafer have higher operating risk, be mainly manifested in the drift of critical size of polycrystalline silicon grid electrode, the electrical parameter of wafer is finally caused not reach product specification requirement, degradation problem under product yield.
Chinese patent CN103681287A discloses a kind of method controlling critical size of polycrystalline silicon grid electrode, described method be according to WAC-AC3 technical process deposited silicon-oxygen polymer thickness quantitative control etching polysilicon gate after critical size, the method overcome the impact of free particle on polysilicon etching cavity atmosphere in prior art uncontrollable, a difficult problem for critical size of polycrystalline silicon grid electrode cannot be controlled quantitatively, but for how controlling critical size of polycrystalline silicon grid electrode stability problem after each etching cavity maintaining cannot solve well.
Chinese patent CN101930921A discloses a kind of method improving grid size uniformity, and the method comprises: in wafer substrate, form grid oxic horizon successively, polysilicon layer, bottom antireflective coating and coating photoresist layer; Described photoresistance is modified (trim), for defining the position of polysilicon gate; Main etching and over etching are carried out to described bottom antireflective coating; Etch described polysilicon layer and form grid; Remove photoresistance and bottom antireflective coating; Patent core is.Adopt bias voltage in etching reaction chamber, photoresistance is modified.Adopt the method greatly can improve the uniformity of critical size of polycrystalline silicon grid electrode.
The offset problem of critical size of polycrystalline silicon grid electrode after internal wall member is changed during etching cavity maintaining in all unresolved prior art of above-mentioned two pieces patent, cannot adjust for critical size of polycrystalline silicon grid electrode after etching cavity maintaining quantitatively, be difficult to the cutting point fast finding problem accurately simultaneously when critical size of polycrystalline silicon grid electrode goes wrong, thus affect electric property and the product yield of wafer.
Summary of the invention
Technical problem to be solved by this invention is for there is above-mentioned defect in prior art, a kind of stability obviously can improving critical size of polycrystalline silicon grid electrode after etching cavity maintaining is provided, ensures the method that the electrical parameter of wafer reaches product specification and requires.
In order to realize above-mentioned technical purpose, according to the present invention, provide a kind of method improving critical size of polycrystalline silicon grid electrode stability after etching cavity maintenance, comprising: first step: be provided for the plasma reaction etching cavity of polycrystalline silicon gate grid etching process and need to carry out the semiconductor structure of etching polysilicon gate process; Second step: carry out etching polysilicon gate process to described semiconductor structure in plasma reaction etching cavity, utilizes hard mask layers modification process to control critical size of polycrystalline silicon grid electrode live width size in described etching polysilicon gate processing procedure; Third step: after described etching polysilicon gate process completes, carries out maintaining to described plasma reaction etching cavity, and there is Y on replacing surface when maintaining
2o
3the plasma reaction etching cavity internal wall member of coating; 4th step: before described semiconductor structure is placed in carries out etching polysilicon in reaction cavity, at the internal wall member surface deposition silicon oxide compound of described reaction chamber; 5th step: the corresponding relation between the processing time that during RF of etching cavity internal wall member changed according to the 4th step, number and hard mask layer are modified adjusts the etch period that hard mask layer is modified, and based in plasma reaction etching cavity after maintaining of the etch period of the hard mask layer modification after adjusting, etching polysilicon gate is carried out to second half conductor structure.
Preferably, the processing time corresponding relation that during etching cavity internal wall member RF, number and hard mask layer are modified comprises the saturation time region after linear session region and linear session region.
Preferably, in the 5th step, in linear time interval, adjust according to number during the RF of etching cavity internal wall member changed the processing time that hard mask layer modifies linearly.
Preferably, in the 5th step, in saturation time interval, the processing time of the hard mask layer modification that setting is fixing.
Preferably, plasma reaction etching cavity comprises etch chamber roof.
Preferably, plasma reaction etching cavity comprises etching cavity inwall.
Preferably, silicon oxide compound is SiO
2cl
4.
Preferably, the 4th step comprises: utilize SiCl
4with O
2carry out being obtained by reacting SiO
2cl
4, and make SiO
2cl
4on the sidewall depositing to plasma reaction etching cavity and roof.
Preferably, in linear time interval, during internal wall member RF, the pass of the processing time x that number y and hard mask layer are modified is y=0.0047x+20.512.
The invention discloses a kind of method improving critical size of polycrystalline silicon grid electrode stability after etching cavity maintaining, (there is Y on surface to change etching cavity internal wall member during to improve plasma etch chamber maintaining under existence conditions
2o
3the etching cavity inwall of coating and etch chamber roof) unsteadiness of critical size of polycrystalline silicon grid electrode that causes of the change of etching cavity environment afterwards, overcome the cutting point being difficult to find fast and accurately problem when critical size of polycrystalline silicon grid electrode goes wrong simultaneously, thus affect the problem of wafer electric property and product yield.The method realizes simple, with low cost.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily there is more complete understanding to the present invention and more easily understand its adjoint advantage and feature, wherein:
Fig. 1 schematically shows the flow chart of the method improving critical size of polycrystalline silicon grid electrode stability after etching cavity maintenance according to the preferred embodiment of the invention.
Fig. 2 schematically shows and more renews depositing silicon oxygen compound schematic diagram after internal wall member according to the preferred embodiment of the invention.
Fig. 3 schematically shows wafer according to the preferred embodiment of the invention and is more renewing operation schematic diagram in internal wall member operation cavity.
Corresponding relation between the processing time that when Fig. 4 schematically shows the RF of plasma reaction etching cavity internal wall member, number and hard mask layer are modified.
It should be noted that, accompanying drawing is for illustration of the present invention, and unrestricted the present invention.Note, represent that the accompanying drawing of structure may not be draw in proportion.Further, in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention clearly with understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
The invention discloses a kind of method improving critical size of polycrystalline silicon grid electrode stability after etching cavity maintaining, according to changing cavity inner wall parts during each etching cavity maintaining, (there is Y on surface to the method
2o
3the etching cavity inwall of coating and etch chamber roof) use RF time the number hard mask layer of determining etching technics after the maintaining of the quantitative analysis etching cavity etch period modified, reach the stability maintaining etching wafer critical size of polycrystalline silicon grid electrode.Particularly, the processing time corresponding relation that during etching cavity internal wall member RF, number and hard mask layer are modified comprises the saturation time region after linear session region and linear session region.Wherein, the processing time that the adjustment hard mask layer that when changing the RF of etching cavity internal wall member according to etching cavity in linear time interval, number is linear is modified, in saturation time interval, the processing time that the fixing hard mask layer of setting is modified.This obviously can improve the stability of critical size of polycrystalline silicon grid electrode after etching cavity maintaining, ensures that the electrical parameter of wafer reaches product specification requirement, improves wafer yield.The method realizes simple, with low cost, Be very effective.
And etch critical dimension controls after changing etching cavity internal wall member when the present invention is equally applicable to the etching cavity maintaining in the etching technics such as identical shallow trench etching.
The preferred embodiments of the present invention will be specifically described below.
Fig. 1 schematically shows the flow chart of the method improving critical size of polycrystalline silicon grid electrode stability after etching cavity maintenance according to the preferred embodiment of the invention.
As shown in Figure 1, after improving etching cavity maintenance according to the preferred embodiment of the invention, the method for critical size of polycrystalline silicon grid electrode stability comprises:
First step S1: be provided for the plasma reaction etching cavity 100 of polycrystalline silicon gate grid etching process and need to carry out the semiconductor structure of etching polysilicon gate process;
Second step S2: carry out etching polysilicon gate process to described semiconductor structure in plasma reaction etching cavity 100, utilizes hard mask layers modification process to control critical size of polycrystalline silicon grid electrode live width size in described etching polysilicon gate processing procedure;
Third step S3: after described etching polysilicon gate process completes, carries out maintaining to described plasma reaction etching cavity 100, and there is Y on replacing surface when maintaining
2o
3(such as, there is Y on surface to plasma reaction etching cavity 100 internal wall member of coating
2o
3the etching cavity inwall of coating and/or etch chamber roof);
4th step S4: before being placed in by described semiconductor structure and carrying out etching polysilicon in plasma reaction etching cavity 100, (be preferably SiO at the internal wall member surface deposition silicon oxide compound of described reaction chamber
2cl
4), as shown in Figure 2; .
In concrete example, the 4th step S4 comprises: utilize SiCl
4with O
2carry out being obtained by reacting SiO
2cl
4, and make SiO
2cl
4on the sidewall depositing to plasma reaction etching cavity 100 and roof.The silicon oxide compound of described etching cavity internal wall member adsorption can consume plasma etching gas in hard mask layers modification process step, to such an extent as to the plasma gas concentration that described semiconductor structure etches reduces.
5th step S5: the corresponding relation between the processing time that during RF of plasma reaction etching cavity 100 internal wall member changed according to the 4th step S4, number and hard mask layer are modified adjusts the etch period that hard mask layer is modified, and based in the plasma reaction etching cavity 100 of etch period after maintaining that the hard mask layer after adjustment is modified, etching polysilicon gate is carried out to second half conductor structure 200, as shown in Figure 3.
And particularly, as shown in Figure 4, the processing time corresponding relation that during etching cavity internal wall member RF, number and hard mask layer are modified comprises the saturation time region 20 after linear session region 10 and linear session region.
Wherein, preferably, in the 5th step S5, in linear time interval 10, adjust according to number during the RF of etching cavity internal wall member changed the processing time that hard mask layer modifies linearly.And, preferably, in the 5th step S5, in saturation time interval 20, the processing time of the hard mask layer modification that setting is fixing.Described, hard mask layer is modified etch period and is had a set time value.Wherein, described hard mask layer is modified etch period and is preset for realizing the etch period that required for critical size of polycrystalline silicon grid electrode score width values, hard mask layer is modified.
Before polycrystalline silicon gate grid etching process is carried out to wafer, deposit one deck silicon-oxygen polymer SiO in etching cavity inner wall surface in advance at every turn
2cl
4, during etching cavity maintaining change different RF time number internal wall member, because of its superficial roughness in RF certain number with absorption SiO
2cl
4ability has certain linear relationship, and hard mask layer modification etching process is carry out adjusting for critical size of polycrystalline silicon grid electrode live width, bias voltage is not had, SiO2Cl4 and the CHF for laterally etching polysilicon gate of etch chamber wall surface in processing step
3plasma reaction, reduces CHF
3the etching of plasma and polysilicon gate transverse direction, thus the critical size live width effectively affecting polysilicon gate.
Experiment shows, during the internal wall member RF changed during etching cavity maintaining, number during replacing inwall device R F can be divided into linear session interval (being probably 0-2300H) and saturation time interval (2300-5500H) to the impact that hard mask layer modifies the time by number.In linear session interval, now for reaching fixing polysilicon gate live width, the etching technics time that during the internal wall member RF of replacing, number and hard mask layer are modified is linear, is roughly 21S-31S; Saturation time is interval, and change internal wall member and produce enough polymer thicknesses to silicon-oxygen polymer absorption, the impact produced the etching environment in etch chamber is saturated, and now the hard mask layer modification process time is fixed, and is roughly 31S.
Experimentally data in a particular embodiment, the processing time of known hard mask layer modification becomes the linear relationship of strong correlation with number during replacing internal wall member RF, namely being presented in linear session interval, during internal wall member RF, the pass of the processing time x that number y and hard mask layer are modified is y=0.0047x+20.512.
Data in Fig. 4 are only when a certain specific etching polysilicon gate formula, modify a kind of situation of etch period according to hard mask layer when number must reach critical size of polycrystalline silicon grid electrode desired value when changing internal wall member RF during etching cavity maintaining.Under other polycrystalline silicon gate grid etching process formula, figure and Fig. 1 of display are identical, and be a linear session interval and a saturation time interval, just numerical value is different from the present embodiment.
Described on end, when the present invention passes through to change internal wall member RF when etching cavity maintaining, number difference forms the difference to silicon-oxygen polymer adsorption capacity, number and etching technics hard mask layer when changing internal wall member RF is caused to modify time proportionate relationship linear in necessarily interval, thus hard mask layer modification process etch period can be controlled quantitatively according to number when changing the RF of etching cavity internal wall member, reach the object of fixing quantity critical size of polycrystalline silicon grid electrode, simultaneously when the critical size of polysilicon gate goes wrong, also the cutting point of problem can fast be found accurately, thus improve the yield of wafer, and method technique is simple, with low cost.
Be understandable that, although the present invention with preferred embodiment disclose as above, but above-described embodiment and be not used to limit the present invention.For any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the technology contents of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1. improve a method for critical size of polycrystalline silicon grid electrode stability after etching cavity maintenance, it is characterized in that comprising:
First step: be provided for the plasma reaction etching cavity of polycrystalline silicon gate grid etching process and need to carry out the semiconductor structure of etching polysilicon gate process;
Second step: carry out etching polysilicon gate process to described semiconductor structure in plasma reaction etching cavity, utilizes hard mask layers modification process to control critical size of polycrystalline silicon grid electrode live width size in described etching polysilicon gate processing procedure;
Third step: after described etching polysilicon gate process completes, carries out maintaining to described plasma reaction etching cavity, and there is Y on replacing surface when maintaining
2o
3the plasma reaction etching cavity internal wall member of coating;
4th step: before described semiconductor structure is placed in carries out etching polysilicon in reaction cavity, at the internal wall member surface deposition silicon oxide compound of described reaction chamber;
5th step: the corresponding relation between the processing time that during RF of etching cavity internal wall member changed according to the 4th step, number and hard mask layer are modified adjusts the etch period that hard mask layer is modified, and based in plasma reaction etching cavity after maintaining of the etch period of the hard mask layer modification after adjusting, etching polysilicon gate is carried out to second half conductor structure.
2. the method improving critical size of polycrystalline silicon grid electrode stability after etching cavity maintenance according to claim 1, it is characterized in that, the processing time corresponding relation that during etching cavity internal wall member RF, number and hard mask layer are modified comprises the saturation time region after linear session region and linear session region.
3. the method improving critical size of polycrystalline silicon grid electrode stability after etching cavity maintenance according to claim 2, it is characterized in that, in the 5th step, in linear time interval, adjust according to number during the RF of etching cavity internal wall member changed the processing time that hard mask layer modifies linearly.
4. the method improving critical size of polycrystalline silicon grid electrode stability after etching cavity maintenance according to claim 2, is characterized in that, in the 5th step, in saturation time interval, and the processing time that the fixing hard mask layer of setting is modified.
5. the method improving critical size of polycrystalline silicon grid electrode stability after etching cavity maintenance according to claim 1 and 2, it is characterized in that, plasma reaction etching cavity comprises etch chamber roof.
6. the method improving critical size of polycrystalline silicon grid electrode stability after etching cavity maintenance according to claim 1 and 2, it is characterized in that, plasma reaction etching cavity comprises etching cavity inwall.
7. the method improving critical size of polycrystalline silicon grid electrode stability after etching cavity maintenance according to claim 1 and 2, it is characterized in that, silicon oxide compound is SiO
2cl
4.
8. the method improving critical size of polycrystalline silicon grid electrode stability after etching cavity maintenance according to claim 7, it is characterized in that, the 4th step comprises: utilize SiCl
4with O
2carry out being obtained by reacting SiO
2cl
4, and make SiO
2cl
4on the sidewall depositing to plasma reaction etching cavity and roof.
9. the method improving critical size of polycrystalline silicon grid electrode stability after etching cavity maintenance according to claim 1 and 2, it is characterized in that, in linear time interval, during internal wall member RF, the pass of the processing time x that number y and hard mask layer are modified is y=0.0047x+20.512.
10. the method improving critical size of polycrystalline silicon grid electrode stability after etching cavity maintenance according to claim 1 and 2, it is characterized in that, described method is for the manufacture of MOS transistor.
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Cited By (5)
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| CN105957792A (en) * | 2016-06-30 | 2016-09-21 | 上海华力微电子有限公司 | Etching method of semiconductor structure |
| CN106887381A (en) * | 2017-03-27 | 2017-06-23 | 上海华力微电子有限公司 | A kind of optimization method of etching cavity environmental stability |
| CN111524785A (en) * | 2020-06-03 | 2020-08-11 | 上海邦芯半导体设备有限公司 | Processing method of dry etching cavity |
| CN113035710A (en) * | 2021-03-15 | 2021-06-25 | 上海华力微电子有限公司 | Method for optimizing polysilicon etching defects of CIS sensor |
| US11495602B1 (en) | 2021-08-12 | 2022-11-08 | Changxin Memory Technologies, Inc. | Method and device for determining fabrication chamber |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105957792A (en) * | 2016-06-30 | 2016-09-21 | 上海华力微电子有限公司 | Etching method of semiconductor structure |
| CN106887381A (en) * | 2017-03-27 | 2017-06-23 | 上海华力微电子有限公司 | A kind of optimization method of etching cavity environmental stability |
| CN106887381B (en) * | 2017-03-27 | 2019-11-22 | 上海华力微电子有限公司 | A kind of optimization method of etching cavity environmental stability |
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| CN113035710A (en) * | 2021-03-15 | 2021-06-25 | 上海华力微电子有限公司 | Method for optimizing polysilicon etching defects of CIS sensor |
| US11495602B1 (en) | 2021-08-12 | 2022-11-08 | Changxin Memory Technologies, Inc. | Method and device for determining fabrication chamber |
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Application publication date: 20150617 |