CN104716018B - The color method and mixed solution of N traps and deep N-well - Google Patents
The color method and mixed solution of N traps and deep N-well Download PDFInfo
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- CN104716018B CN104716018B CN201310684651.2A CN201310684651A CN104716018B CN 104716018 B CN104716018 B CN 104716018B CN 201310684651 A CN201310684651 A CN 201310684651A CN 104716018 B CN104716018 B CN 104716018B
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Abstract
The invention discloses a kind of N traps in semiconductor devices and the color method and mixed solution of deep N-well.The present invention is first performed etching before being coloured to N traps and deep N-well to semiconductor structure, so that semiconductor structure becomes loose, so that subsequent mixed solution is coloured to loose N traps and deep N-well region；It is 20 that volume ratio is employed in coloring process:50:The new mixed solution of 1 deionized water, 70% concentration nitric acid and 49% concentration hydrofluoric acid so that the colouring rate to N traps and deep N-well is controllable, and good coloring effect can be reached.When the present invention solves progress FA analyses at present, the problem of difficult is coloured to N traps in the semiconductor devices less than 90nm making technologies and deep N-well.
Description
Technical field
The present invention relates to N traps and deep N-well are coloured during a kind of semiconductor analysis technology, more particularly to accident analysis
Method and the mixed solution coloured to N traps and deep N-well.
Background technology
Coloring（stain）It is FA（Failure Analysis, accident analysis）In be used for detect doping profile or structure
The conventional means of profile.For example, for the SEM of semiconductor devices（Scanning Electron Microscope, scanning electron
Microscope）Section CA（Construction Analysis, structural analysis）HF is needed in analysis（Hydrofluoric acid）Coloring, GOX
（Gate Oxide, grid oxic horizon）Detection needs etching polysilicon liquid（Poly acid）Coloring, NMOS（N-Metal-
Oxide-Semiconductor, N-type metal-oxide semiconductor (MOS)）Middle source/drain region doping detection needs n-type doping etching liquid
Color etc..
But, in FA, for N traps（N-well）And deep N-well（DNW, Deep N-well）Doping profile detection be
One difficult problem.
Fig. 1 is a kind of structural representation of semiconductor devices, and the semiconductor devices is CMOS（Complementary
Metal-Oxide-Semiconductor, complementary metal oxide semiconductor）, it includes NMOS and PMOS（P-Metal-
Oxide-Semiconductor, P-type mos）.As shown in figure 1, the structure includes substrate 1, in substrate 1
Deep N-well 2 is formed with, STI is formed with deep N-well 2（Shallow Trench Isolation, shallow trench isolation）3, position
In STI3 both sides be respectively PMOS and NMOS.Wherein PMOS includes：The N traps 41 in substrate 1 are formed at, on substrate 1
Grid 43, the source/drain region 42 positioned at the both sides of grid 43 and in the substrate 1, and positioned at the both sides of grid 43 and positioned at substrate 1 it
On side wall 44.NMOS includes：The p-well 51 in substrate 1 is formed at, the grid 53 on substrate 1, positioned at the both sides of grid 53 simultaneously
Source/drain region 52 in substrate 1, and the side wall 54 positioned at the both sides of grid 53 and on substrate 1.NMOS and PMOS knots
Be substantially the same on structure, but be due to doping ion it is different and be divided into N-type and p-type, wherein, NMOS is located on p-well 51, NMOS
Source/drain region 52 be n-type doping, PMOS is located on N traps 41, and PMOS source/drain region 42 is p-type doping.In NMOS and PMOS
On be formed with ILD（Inter Layer Dielectric, interlayer dielectric layer）6, NMOS and/or PMOS source/drain region 42,
52 and grid 43,53 according to circuit design needs, can be provided with through hole 7, for circuit connect.
As shown in figure 1, in CMOS structure, the region such as source/drain region, lightly doped drain is shallower due to position, used
Reagent is easily penetrated and reacted with relevant range to colour, still, for N traps 41 and deep N-well 2, by its institute
Locate position deeper（Positioned at PMOS bottoms）, the reagent to colour either be difficult to enter N traps 41, deep N-well 2 or hyperchromia
And influenceing other regions to cause doping profile to obscure, regional cannot be distinguished by, and then influence FA detections.
For the coloring of semiconductor devices, making technology is more advanced, and doping concentration is lower, and coloring reaction is not allowed more
Easily.In addition, it may also be noted that in MOS device, the doping concentration of N traps and deep N-well is than the other positions of MOS device
Doping concentration is low, so N traps and deep N-well are also that the part of coloring is most difficult in MOS device.
And 98% concentration acetic acid is typically used to N traps 41 and the staining reagent of deep N-well 2 at present（CH3OOH）, 70% concentration nitre
Acid（HNO3）With 49% concentration hydrofluoric acid（HF）Mixed solution, the volume ratio of acetic acid, nitric acid and hydrofluoric acid is 100:20:1, example
Such as, mixed by 49% concentration hydrofluoric acid of 100ml 98% concentration acetic acid, 20ml 70% concentration nitric acid and 1ml.Wherein acetic acid
As buffer solution to dilute the acidity of staining reagent, nitric acid is used to aoxidize element silicon, and hydrofluoric acid is used to enter with oxide
Row reacts to form the profile of painted areas.The mixed solution is in CD（Critical Dimension, critical size）For 90nm
（Nanometer）N traps 41 and deep N-well 2 can well be coloured in making technology above, for the semiconductor of 90nm techniques
For device, the time that the mixed solution is coloured is used for 19~21s（Second）, preferably 20s.It can use above-mentioned existing
The doping concentration that the mixed solution of staining reagent is coloured at least is needed 1 × 1013atoms/cm2（Atom/square centimeter）
The doping concentration of N traps under magnitude, such as 90nm techniques is about 2.8 × 1013atoms/cm2, the doping concentration of deep N-well is about
1.1×1013atoms/cm2, the doping concentration of the two is all 1 × 1013atoms/cm2Magnitude, therefore existing mixed solution pair
The N traps of 90nm techniques and the coloring of deep N-well can reach good effect.But it is smaller for CD（Such as 65nm, 45nm,
32nm）The advanced semiconductor devices being made under technique for, the doping concentration of N traps therein and deep N-well is lower, less than 1 ×
1013atoms/cm2Magnitude, so coloring is more difficult, carrying out coloring using the existing mixed solution is difficult to control to.If
The color time is slightly long, then is easily destroyed whole well structure, as shown in black region in Fig. 2, in Fig. 2, due to hyperchromia so that grid
Pole 43,53, source/drain region 42,52, N traps 41, p-well 51 and deep N-well 2 are all coloured and are difficult to differentiate between by transition.If during coloring
Between it is slightly shorter, then be unable to reach coloring effect, as shown in Fig. 3 mesh-like areas, grid 53, the quilt of source/drain region 52 in only shallower region
Coloring.Therefore, existing mixed solution and color method are dfficult to apply to partly leading under advanced process techniques of the CD less than 90nm
Body device.
The content of the invention
In view of this, the present invention provides the color method of a kind of N traps and deep N-well, is less than the smaller of 90nm in CD to realize
Advanced technologies under N traps to semiconductor devices and the coloring of deep N-well so that the region contour after coloring is clear, is examined beneficial to FA
Survey.
What the technical scheme of the application was realized in：
A kind of color method of N traps and deep N-well, including：
Semiconductor structure is performed etching, so that the semiconductor structure is loose；
Loose semiconductor structure is reacted using the mixed solution of deionized water, nitric acid and hydrofluoric acid, so that institute
State the N traps in semiconductor structure and deep N-well coloring.
Further, semiconductor structure is performed etching including：
Using XeF2Gas is performed etching to the semiconductor structure so that F ion therein etches the semiconductor junction
Silicon materials in structure, and then make it that the semiconductor structure is loose.
Further, during etching, XeF2Gas flow can be controlled in 3 × 106~8 × 106nm3/ s, the etching reaction time is 1
~5s.
Further, the mixed solution is mixed using deionized water, 70% concentration nitric acid and 49% concentration hydrofluoric acid, institute
The volume ratio for stating deionized water, 70% concentration nitric acid and 49% concentration hydrofluoric acid is 20:50:1.
Further, loose semiconductor structure is reacted using the mixed solution of deionized water, nitric acid and hydrofluoric acid
Duration be 24~36s.
Further, the semiconductor structure includes：
Substrate；
It is formed at the deep N-well in substrate；
It is located at the N traps on deep N-well in substrate；
Grid on substrate；
Source/drain region positioned at grid both sides and in substrate；And
Positioned at grid both sides and positioned at the side wall of substrate.
Further, the mixed solution is mixed by deionized water, 70% concentration nitric acid and 49% concentration hydrofluoric acid, described
The volume ratio of deionized water, 70% concentration nitric acid and 49% concentration hydrofluoric acid is 20:50:1.
From such scheme as can be seen that the color method and mixed solution of N traps provided by the present invention and deep N-well,
First semiconductor structure is performed etching before color, so that semiconductor structure becomes loose, so that subsequent mixed solution is to loose
N traps and deep N-well region coloured, volume ratio is employed in coloring process for 20:50:1 deionized water, 70% concentration
The new mixed solution of nitric acid and 49% concentration hydrofluoric acid so that the colouring rate to N traps and deep N-well is controllable, and can reach
Good coloring effect.When the present invention solves progress FA analyses at present, to N in the semiconductor devices less than 90nm making technologies
The problem of trap and difficult deep N-well coloring.
Brief description of the drawings
Fig. 1 is the structural representation of semiconductor devices；
Fig. 2 is the signal that existing method colours failure to N traps and deep N-well that the semiconductor devices of technique is made less than 90nm
One of figure；
Fig. 3 is the signal that existing method colours failure to N traps and deep N-well that the semiconductor devices of technique is made less than 90nm
Two figures；
Fig. 4 is the N traps of the present invention and the color method embodiment flow chart of deep N-well；
Fig. 5 is embodiment schematic diagram of the semiconductor structure after over etching in the method for the present invention；
Embodiment signal after mixed solution colorings of the Fig. 6 for semiconductor structure in the method for the present invention by the present invention
Figure.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, develop simultaneously embodiment referring to the drawings,
The present invention is described in further detail.
It is referred to tie shown in Fig. 1 using the semiconductor structure embodiment of the color method of N traps and deep N-well of the invention
Structure, the structure includes：Substrate 1, is formed at the N traps 41 being located in the deep N-well 2 in substrate 1, substrate 1 on deep N-well 2, positioned at lining
Grid 43 on bottom 1, the source/drain region 42 positioned at the both sides of grid 43 and in substrate 1, and positioned at the both sides of grid 43 and position
Side wall 44 on substrate 1, the wherein material of substrate 1 are silicon.The structure is PMOS structures common in this area, in CMOS
In, in addition to PMOS structure identical NMOS, here is omitted.
As shown in figure 4, the N traps and the color method of deep N-well of the present invention, including：
Semiconductor structure is performed etching, so that the semiconductor structure is loose；
Loose semiconductor structure is reacted using the mixed solution of deionized water, nitric acid and hydrofluoric acid, so that institute
State the N traps in semiconductor structure and deep N-well coloring.
The N traps of the present invention and the color method of deep N-well are described in detail below in conjunction with Fig. 5, Fig. 6.
Step 1, semiconductor structure is performed etching, so that the semiconductor structure is loose.
In this step 1, using XeF2（Xenon difluoride）Gas is performed etching to the semiconductor structure so that fluorine therein
Silicon materials in semiconductor structure described in ion etching.It is used as a specific embodiment, during etching, XeF2Gas flow can control
3 × 106~8 × 106nm3/s（Cubic nanometer/second）, preferably 6.9 × 106nm3/ s, etching reaction time control is in 1~5s
（Second）, preferably 3s.Semiconductor structure after this step 1 can be found in shown in Fig. 5, wherein, by XeF2The quarter of gas
After erosion, the grid 43,53 in the semiconductor structure, source/drain region 42,52, N traps 41, the structure of p-well 51 and deep N-well 2 becomes
Loosely, when next step is coloured, the loose structure enable to colour used in mixed solution easily penetrate, with these
Loose region carries out fully contact, otherwise, then can be due to N traps 41 and the relatively low doping concentration of deep N-well 2 in favor of reaction so that
Mixed solution is difficult to react with painted areas.It should be noted that using XeF in this step 12Gas is to the semiconductor structure
The process performed etching will not destroy the doping concentration in semiconductor structure.
Step 2, using the mixed solution of deionized water, nitric acid and hydrofluoric acid loose semiconductor structure is reacted,
So that N traps and deep N-well coloring in the semiconductor structure.
In this step 2, the mixed solution used is by deionized water（DI water）, 70% concentration nitric acid（HNO3）With 49%
Concentration hydrofluoric acid is mixed, and the volume ratio of deionized water, 70% concentration nitric acid and 49% concentration hydrofluoric acid is 20:50:1, for example,
Mixed by 49% concentration hydrofluoric acid of 20ml deionized water, 50ml 70% concentration nitric acid and 1ml and manufactured in the present invention
Mixed solution.In the mixed solution, deionized water is as buffer solution to dilute the acidity of mixed solution, and nitric acid is used for silicon member
Element is aoxidized, and hydrofluoric acid is used to be reacted to form the profile of painted areas with oxide.In this step 2, using described
The duration that the mixed solution of deionized water, nitric acid and hydrofluoric acid is reacted loose semiconductor structure is 24~36s,
Preferably 30s.
The mixed solution is used in this step 2, can be to doping concentration scope 1 × 1012~1 × 1013atoms/cm2's
（Experimental verification, the doping concentration that the mixed solution is applicable may diminish to 1 × 1012atoms/cm2）N traps and deep N-well are carried out
Color, should be less than 1 × 1012~1 × 1013atoms/cm2N traps and the doping concentration concentration range of deep N-well be less than suitable for CD
N traps and deep N-well in 90nm sophisticated semiconductor manufacturing process, the N traps and deep N-well of such as 65nm, 55nm, 45nm technique are adapted to
Detection to well area profile.
Compared with mixed solution used in the prior art, in mixed solution provided by the present invention：Using deionization
Water substitutes acidity of the acetic acid to dilute staining reagent as buffer solution, reduces H in mixed solution+Ion（Hydrogen ion）Contain
Amount, and then the acidity of mixed solution is reduced, weaken the influence of coloring；Using the nitric acid of most ratios, mixing is enhanced molten
The oxidation of liquid, it is contemplated that the doping concentration of nitric acid oxidation and relatively low N traps and deep N-well, it is necessary to more nitric acid so that
Element silicon is aoxidized；The ratio of hydrofluoric acid is slightly increased, colouring rate can be accelerated, and course of reaction is controllable.
The actual coloring experimental result of the above method to semiconductor devices by the present invention, observes N traps and depth in the secure execution mode (sem
The profile of N traps, can reach gem-pure effect.
The color method and mixed solution of N traps provided by the present invention and deep N-well, first to semiconductor structure before coloring
Perform etching, so that semiconductor structure becomes loose, so that subsequent mixed solution is carried out to loose N traps and deep N-well region
Coloring, it is 20 that volume ratio is employed in coloring process:50:1 deionized water, 70% concentration nitric acid and 49% concentration hydrofluoric acid
New mixed solution so that the colouring rate to N traps and deep N-well is controllable, and good coloring effect can be reached.The present invention
When solving progress FA analyses at present, difficult ask is coloured to N traps in the semiconductor devices less than 90nm making technologies and deep N-well
Topic.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
God is with principle, and any modification, equivalent substitution and improvements done etc. should be included within the scope of protection of the invention.
Claims (7)
1. the color method of a kind of N traps and deep N-well, including：
Semiconductor structure is performed etching, so that the semiconductor structure is loose；
Loose semiconductor structure is reacted using the mixed solution of deionized water, nitric acid and hydrofluoric acid, so that described half
N traps and deep N-well coloring in conductor structure；Wherein,
The N traps and deep N-well are the N traps and deep N-well that critical size CD is less than in 90nm sophisticated semiconductor manufacturing process.
2. the color method of N traps according to claim 1 and deep N-well, it is characterised in that performed etching to semiconductor structure
Including：
Using XeF2Gas is performed etching to the semiconductor structure so that F ion therein is etched in the semiconductor structure
Silicon materials, and then make it that the semiconductor structure is loose.
3. the color method of N traps according to claim 2 and deep N-well, it is characterised in that：
During etching, XeF2Gas flow can be controlled in 3 × 106~8 × 106nm3/ s, the etching reaction time is 1~5s.
4. the color method of N traps according to claim 1 and deep N-well, it is characterised in that the mixed solution using go from
Sub- water, 70% concentration nitric acid and 49% concentration hydrofluoric acid are mixed, the deionized water, 70% concentration nitric acid and 49% concentration
The volume ratio of hydrofluoric acid is 20:50:1.
5. the color method of N traps according to claim 4 and deep N-well, it is characterised in that using deionized water, nitric acid and
The duration that the mixed solution of hydrofluoric acid is reacted loose semiconductor structure is 24~36s.
6. the color method of the N traps and deep N-well according to any one of claim 1 to 5, it is characterised in that the semiconductor
Structure includes：
Substrate；
It is formed at the deep N-well in substrate；
It is located at the N traps on deep N-well in substrate；
Grid on substrate；
Source/drain region positioned at grid both sides and in substrate；And
Positioned at grid both sides and positioned at the side wall of substrate.
7. a kind of N traps and the mixed solution of deep N-well coloring, it is characterised in that：The mixed solution is by deionized water, 70% concentration
Nitric acid and 49% concentration hydrofluoric acid are mixed, the volume of the deionized water, 70% concentration nitric acid and 49% concentration hydrofluoric acid
Than for 20:50:1；Wherein,
The N traps and deep N-well are the N traps and deep N-well that critical size CD is less than in 90nm sophisticated semiconductor manufacturing process.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5421958A (en) * | 1993-06-07 | 1995-06-06 | The United States Of America As Represented By The Administrator Of The United States National Aeronautics And Space Administration | Selective formation of porous silicon |
| CN101996880A (en) * | 2009-08-14 | 2011-03-30 | 中芯国际集成电路制造(上海)有限公司 | Method for exposing semiconductor substrate and invalidation analysis method |
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| CN102115024A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院微电子研究所 | System and method for releasing micro-electromechanical system (MEMS) structure by etching silicon sacrificial layer |
| CN202815008U (en) * | 2012-09-21 | 2013-03-20 | 中国科学院地质与地球物理研究所 | Accelerometer |
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