CN104715723B - Display device and its image element circuit and driving method - Google Patents
Display device and its image element circuit and driving method Download PDFInfo
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- CN104715723B CN104715723B CN201510122622.6A CN201510122622A CN104715723B CN 104715723 B CN104715723 B CN 104715723B CN 201510122622 A CN201510122622 A CN 201510122622A CN 104715723 B CN104715723 B CN 104715723B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
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Abstract
A kind of image element circuit, including：For the driving transistor and light-emitting component being connected between the first level terminal and second electrical level end, first pole of driving transistor is connected to the first end of light-emitting component, and second transistor and storage capacitance are connected between the control pole of driving transistor and a conduction electrode.In initial phase, second transistor conducting initializes the current potential at storage capacitance two ends and the current potential of driving transistor control pole respectively；In the valve value compensation stage, reference potential is provided using to driving transistor control pole, read the threshold voltage of driving transistor and be stored in storage capacitance, it is achieved thereby that the compensation to drive transistor threshold voltage, then compensate for the inhomogeneities that image element circuit is shown.
Description
Technical field
The application is related to display device field, and in particular to a kind of display device and its image element circuit and driving method.
Background technology
Organic Light Emitting Diode (Organic Light-Emitting Diode, OLED) display is because with high brightness, height
It is the advantages of luminous efficiency, wide viewing angle and low-power consumption, widely studied by people in recent years, and be applied to rapidly a new generation display work as
In.The type of drive that OLED is shown can be passive waked-up (Passive MatrixOLED, PMOLED) and active matrix
Two kinds of driving (Active Matrix OLED, AMOLED).Passive waked-up is although with low cost, but there is cross-talk
Phenomenon can not realize high-resolution display, and passive waked-up electric current is big, reduces OLED service life.Compared to it
Under, driven with active matrix mode sets the different transistor of number as current source on each pixel, it is to avoid cross-talk,
Required driving current is smaller, and power consumption is relatively low, makes OLED life-span and increases, it is possible to achieve high-resolution display, meanwhile, active square
The need for battle array driving is easier to meet large area and high grade grey level is shown.
Traditional AMOLED image element circuit be simple two TFT (Thin Film Transistor,
TFT) structure, this circuit is although simple in construction, but be unable to compensation for drive transistor T1 and OLED threshold voltage shift or because
TFT devices are made of polycrystalline material and cause the threshold voltage inhomogeneities of panel TFT devices everywhere.As driving transistor T1
When drift or inconsistent value on panel everywhere occur for threshold voltage, OLED threshold voltages, driving current IDSIt will change, and
And on panel different pixel because the different drift situations of bias voltage it is also different, so will result in the inequality of Display panel
Even property.
The content of the invention
The application provides a kind of display device and its image element circuit and driving method, with the threshold value electricity of compensation for drive transistor
The inhomogeneities or threshold voltage shift of pressure.
According in a first aspect, provide a kind of image element circuit in a kind of embodiment, including：
For the driving transistor and light-emitting component being connected between the first level terminal and second electrical level end, and the second crystalline substance
Body pipe, third transistor and storage capacitance；First pole of driving transistor is connected to Section three of the first end formation of light-emitting component
Point, the second pole of driving transistor and the second end of light-emitting component are respectively used to be connected to the first level terminal and second electrical level end；
The first pole that the control pole of driving transistor is connected to second transistor forms first node, the second pole connection of second transistor
Section Point is formed to the first pole of third transistor, the control pole of second transistor is used to input LED control signal；3rd
Second pole of transistor is used to be connected to the data wire for providing data-signal or reference potential, the control of third transistor
Pole is used to input scanning signal；Storage capacitance is connected between Section Point and the 3rd node.
According to second aspect, a kind of image element circuit is provided in a kind of embodiment, including：
For the driving transistor and light-emitting component being connected between the first level terminal and second electrical level end, and the second crystalline substance
Body pipe, third transistor, the 4th transistor, the 5th transistor and storage capacitance；First pole of driving transistor is connected to luminous
First end the 3rd node of formation of element, the second pole of driving transistor and the second end of light-emitting component are respectively used to be connected to the
One level terminal and second electrical level end；The first pole that the control pole of driving transistor is connected to second transistor forms first node,
The first pole that second pole of second transistor is connected to third transistor forms Section Point, and the control pole of second transistor is used for
Input LED control signal；Second pole of third transistor is used to be connected to the data wire for providing data-signal, and the 3rd is brilliant
The control pole of body pipe is used to input scanning signal；First pole of the 5th transistor is connected to first node, the of the 5th transistor
Two poles are used to input reference potential, and the control pole of the 5th transistor is connected to the control pole of third transistor；4th transistor
First pole is connected to the 3rd node, and the second pole of the 4th transistor is used for input initialization current potential, the control pole of the 4th transistor
For input initialization control signal；Storage capacitance is connected between Section Point and the 3rd node.
According to the third aspect, a kind of display device is provided in a kind of embodiment, including：
Image element circuit matrix, the image element circuit matrix includes the above-mentioned image element circuit for being arranged in n row m column matrix, its
In, n and m are the integer more than 0；Gate driving circuit, for producing scanning pulse signal, and by being formed in the first direction
Each horizontal scanning line provides required control signal to image element circuit；Data drive circuit, the number of half-tone information is represented for producing
According to voltage signal, and by each data wire for being formed in a second direction data-signal is provided to image element circuit；Controller, for
Gate driving circuit and data drive circuit provide control sequential.
According to fourth aspect, a kind of pixel circuit drive method, each driving of image element circuit are provided in a kind of embodiment
Cycle includes initial phase, valve value compensation stage, data write phase and glow phase, and driving method includes：
In initial phase, second transistor conducting initializes the current potential and driving transistor at storage capacitance two ends respectively
The current potential of control pole；In the valve value compensation stage, third transistor and/or the 5th transistor turns, to driving transistor control pole
Reference potential is provided, the threshold voltage information of driving transistor is read and is stored by storage capacitance；In data write phase,
Three transistor turns transmit data voltage and are stored in storage capacitance；In glow phase, the first transistor is according to storage capacitance two
The pressure differential at end produces driving current, and drives light-emitting component to light.
According to the image element circuit of above-described embodiment, by connecting second between the control pole of driving transistor and the first pole
Transistor and storage capacitance, and the control of matching timing, driving is read using reference potential is provided to driving transistor control pole
The threshold voltage of transistor is simultaneously stored in storage capacitance, it is achieved thereby that the compensation to drive transistor threshold voltage, is then mended
The inhomogeneities that image element circuit is shown is repaid.
Brief description of the drawings
Fig. 1 a are a kind of image element circuit structure figure disclosed in embodiment one；
Fig. 1 b are another image element circuit structure figure disclosed in embodiment one；
Fig. 2 is a kind of image element circuit driver' s timing figure disclosed in embodiment one；
Fig. 3 a are a kind of image element circuit structure figure disclosed in embodiment two；
Fig. 3 b are another image element circuit structure figure disclosed in embodiment two；
Fig. 4 is a kind of image element circuit driver' s timing figure disclosed in embodiment two；
Fig. 5 a are a kind of disclosed in embodiment two to provide initialization deformed potential scheme；
Fig. 5 b are that another provide initializes deformed potential scheme disclosed in embodiment two；
Fig. 6 a are a kind of image element circuit structure figure disclosed in embodiment three；
Fig. 6 b are another image element circuit structure figure disclosed in embodiment three；
Fig. 7 is a kind of image element circuit driver' s timing figure disclosed in embodiment three；
Fig. 8 a are a kind of image element circuit structure figure disclosed in example IV；
Fig. 8 b are another image element circuit structure figure disclosed in example IV；
Fig. 9 is a kind of image element circuit driver' s timing figure disclosed in example IV；
Figure 10 a are a kind of image element circuit structure figure disclosed in embodiment five；
Figure 10 b are another image element circuit structure figure disclosed in embodiment five；
Figure 11 is a kind of image element circuit driver' s timing figure disclosed in embodiment five；
Figure 12 is a kind of display device structure schematic diagram disclosed in embodiment six.
Embodiment
The present invention is described in further detail below by embodiment combination accompanying drawing.
Some terms are illustrated first：Transistor in the application can be the transistor of any structure, such as double
Bipolar transistor (BJT) or field-effect transistor (FET).When transistor is bipolar transistor, its control pole refers to double
The base stage of bipolar transistor, first extremely can be the colelctor electrode or emitter stage of bipolar transistor, and corresponding second extremely can be
The emitter stage or colelctor electrode of bipolar transistor, in actual application, " emitter stage " and " colelctor electrode " can be with basis signal
Flow to and exchange；When transistor is field-effect transistor, its control pole refers to the grid of field-effect transistor, and the first pole can be with
Drain electrode or source electrode for field-effect transistor, corresponding second extremely can be source electrode or the drain electrode of field-effect transistor, in reality
In application process, " source electrode " and " drain electrode " can be so that basis signal is flowed to and is exchanged.Transistor in display is usually a kind of field
Effect transistor：Thin film transistor (TFT) (TFT).The application is done specifically so that transistor is field-effect transistor as an example below
Bright, transistor can also be bipolar transistor in other embodiments.
Light-emitting component is Organic Light Emitting Diode (Organic Light-Emitting Diode, OLED), in other realities
Apply in example or other light-emitting components.The first end of light-emitting component can be negative electrode or anode, and correspondingly, then light member
Second end of part is male or female.It should be understood by those skilled in the art that：Electric current should flow to negative electrode from the anode of light-emitting component,
Therefore, the flow direction based on electric current, it may be determined that the anode and negative electrode of light-emitting component.
Significant level can be high level or low level, can be realized and adapted to according to the function of specific component
Replace to property.
First level terminal and second electrical level end are the both ends of power provided that worked by image element circuit.In a kind of embodiment
In, the first level terminal can be high level end VDD, second electrical level end is low level end VSSOr ground wire, in other embodiments,
Can adaptively it replace.It should be noted that：For image element circuit, the first level terminal (such as high level end VDD) and
Second electrical level end (such as low level end VSS) not the application image element circuit a part, in order that those skilled in the art are more preferable
Ground understands the technical scheme of the application, and is specifically incorporated the first level terminal and second electrical level end is described by.
It should be noted that for convenience, being more clearly understood that the application's also for those skilled in the art are made
First node A, Section Point B and the 3rd node C is introduced in technical scheme, present specification to carry out circuit structure relevant portion
Mark, it is impossible to regard as the terminal additionally introduced in circuit.
For convenience of description, high level uses VHCharacterize, low level uses VLCharacterize.
Embodiment one：
Fig. 1 a and Fig. 1 b are refer to, are a kind of image element circuit structure figure disclosed in the present embodiment, including：For being connected on
Driving transistor T1 and light-emitting component OLED between one level terminal VDD and second electrical level end VSS, and second transistor T2,
Third transistor T3 and storage capacitance C1.Wherein, in the image element circuit shown in Fig. 1 a, each transistor (driving transistor T1, second
Transistor T2 and third transistor T3) it is N-type TFT；In image element circuit shown in Fig. 1 b, each transistor (driving crystal
Pipe T1, second transistor T2 and third transistor T3) it is P-type TFT.
Driving transistor T1 the first pole is connected to light-emitting component OLED first end the 3rd node C of formation, drives crystal
Pipe T1 the second pole and light-emitting component OLED the second end are respectively used to be connected to the first level terminal VDD and second electrical level end VSS.
In one embodiment, Fig. 1 a are refer to, light-emitting component OLED first end is anode, and light-emitting component OLED the second end is the moon
Pole；Driving transistor T1 the second pole is used to be connected to the first level terminal VDD, and light-emitting component OLED the second end is used to be connected to
Second electrical level end VSS.In another embodiment, Fig. 1 b are refer to, light-emitting component OLED first end is negative electrode, light-emitting component
OLED the second end is anode；Driving transistor T1 the second pole is used to be connected to second electrical level end VSS, light-emitting component OLED's
Second end is used to be connected to the first level terminal VDD.
The first pole that driving transistor T1 control pole is connected to second transistor T2 forms first node A, the second crystal
The first pole that pipe T2 the second pole is connected to third transistor T3 forms Section Point B, and second transistor T2 control pole is used for
Input LED control signal VEM。
Third transistor T3 the second pole is used to be connected to data wire DATA, in a particular embodiment, and data wire DATA is used
In offer data-signal VDATAOr reference potential VREF, in other embodiments, data wire DATA can be also used for providing initial
Change current potential, to initialize the current potential of each node；Third transistor T3 control pole is used to input scanning signal VScan。
Storage capacitance C1 is connected between Section Point B and the 3rd node C.
In a particular embodiment, image element circuit works in first stage, second stage and phase III successively.In this implementation
In example, the first stage can include initial phase and valve value compensation stage successively, and second stage is data write phase, the 3rd
Stage is glow phase.
In the first stage, second transistor T2 and third transistor T3 respond LED control signal V respectivelyEMIt is first effective
Level and scanning signal VScanThe conducting of the first significant level, transmit reference potential V to first node A and Section Point BREFJust
Beginningization first node A and Section Point B current potential, and initialization current potential is provided to the 3rd node C by corresponding signal source, with
The 3rd node C current potential is initialized, in the present embodiment, the 3rd node C initialization current potential is by the first level terminal VDD by leading
Logical driving transistor T1 is provided, and reads driving transistor T1 threshold voltage VTH.In one embodiment, it refer to figure
1a, in initial phase, the initialization current potential that driving transistor T1 the second pole the first level terminal VDD of transmission is provided is (such as low
Level) initialization the 3rd node C current potential；In the valve value compensation stage, the first level terminal is transmitted in driving transistor T1 the second pole
VDD significant level (such as high level), then, the 3rd node C current potential change and (for example raised), until node electricity
Untill when position differs driving transistor T1 threshold voltage with driving transistor T1 control pole, storage capacitance C1 is according to drive
The current potential and the pressure difference between the 3rd node C of dynamic transistor T1 control pole (i.e. Section Point B or first node A) are obtained
Driving transistor T1 threshold voltage VTH.In another embodiment, Fig. 1 b are refer to, in initial phase, the 3rd node C's
Initialize current potential to be provided by second electrical level end VSS, i.e. the first of second electrical level end VSS offers is transmitted in the second pole of driving transistor T1
Beginningization current potential (such as high level) initializes the 3rd node C current potential；In valve value compensation stage, driving transistor T1 the second pole
Second electrical level end VSS significant level (such as low level) is transmitted, then, the 3rd node C current potential changes (such as under
Drop), untill when the node potential differs driving transistor T1 threshold voltage with driving transistor T1 control pole,
Storage capacitance C1 according to the current potential of driving transistor T1 control pole (i.e. Section Point B or first node A) and with Section three
Pressure difference between point C obtains driving transistor T1 threshold voltage VTH。
In second stage, second transistor T2 is by LED control signal VEMControl rings in cut-off state, third transistor T3
Answer scanning signal VScanThe second significant level turn on to Section Point B transmission data-signal VDATA；
In the phase III, third transistor T3 is by scanning signal VScanControl is in cut-off state, second transistor T2 responses
LED control signal VEMThe conducting of the second significant level, driving transistor T1 responses first node A current potential conducting driving is luminous
Element OLED lights.
It should be noted that in one embodiment, refer to Fig. 1 a, LED control signal VEMSignificant level (including the
One significant level and the second significant level) and scanning signal VScanSignificant level (including the first significant level and second effective
Level) it is high level；In another embodiment, Fig. 1 b, LED control signal V refer toEMSignificant level (including first
Significant level and the second significant level) and scanning signal VScanSignificant level (including the first significant level and second effectively electricity
It is flat) it is low level.
In the present embodiment, scanning signal VScanThe second significant level lag behind the scanning signal VScanFirst have
Imitate level and LED control signal VEMThe first significant level, LED control signal VEMThe second significant level lag behind scanning
Signal VScanThe second significant level.
Hereafter image element circuit driving process disclosed in the present embodiment is explained by taking Fig. 1 a as an example.The pixel of the present embodiment
Circuit drives process is divided into initial phase, valve value compensation stage, data write phase and glow phase, is illustrated in figure 2 this
The signal sequence of embodiment, the driving process of the present embodiment is specifically described with reference to Fig. 2 and Fig. 1 a.
In initial phase：The scanning signal V provided to third transistor T3ScanFor high level VH, as first is effectively electric
It is flat；LED control signal VEMFor high level VH, as the first significant level.Then, third transistor T3 and second transistor T2
Conducting.Data wire DATA transmits reference potential V to third transistor T3REF, reference potential VREFPass through the transistor T3 of conducting
First node A is input to T2 so that first node A current potential is VREF, because first node A and Section Point B passes through second
Transistor T2 is connected, so two node voltages are identical.At the same time, driving transistor T1 is in the conduction state, the first level
VDD outputs one are held to initialize current potential low level signal VL, the level signal is simultaneously input to the 3rd node by switching transistor T1
C so that the 3rd node C level is changed into VL.So as to complete at the beginning of first node A, Section Point B and the 3rd node C current potential
Beginningization.
In the valve value compensation stage：Scanning signal VScanWith LED control signal VEMContinue to the first significant level, high electricity
Flat VH, data wire DATA, which remains unchanged, transmits reference potential VREF.The signal that first level terminal VDD is provided is by low level VLBecome high level again
VH, and charged by driving transistor T1 to the 3rd node C.Therefore 3rd node C current potential can slowly raise, until the node
It is increased to VREF-VTHWhen, driving transistor T1 can enter cut-off state, and the 3rd node C current potential is maintained VREF-VTH.Wherein VTH
For driving transistor T1 threshold voltage.After the valve value compensation stage terminates, driving transistor T1 threshold voltage information is by depositing
Storing up electricity is held C1 and is stored on node C.It should be noted that VREF-VTHLess than light-emitting component OLED threshold voltage.
Data write phase：LED control signal VEMIt is changed into low level, scanning signal VScanIt is changed into the second significant level, such as
High level VH.Now, second transistor T2 is in cut-off state, and third transistor T3 is in the conduction state, and data wire DATA is carried
For data voltage VDATAAnd be written to by the third transistor T3 of conducting in Section Point B.It should be noted that in other realities
Apply in example, when there is multirow image element circuit and using while when by the way of luminous, then in the stage, each line scan signals VScan's
Second significant level arrives successively, to complete Section Point B data voltage V line by lineDATAWrite-in.In Section Point B current potential
By VREFIt is charged to VDATADuring, data voltage VDATACan be by storage capacitance C1 and light-emitting component OLED intrinsic capacity C2
Coupling be coupled in node C so that node C potential change is：
Wherein, VnodeC represents the 3rd node C current potential, and C1 and C2 are then storage capacitance C1 and light-emitting component OLED respectively
Intrinsic capacity capacitance.
Glow phase：LED control signal VEMSecond significant level such as high electricity VHIt is flat to arrive, scanning signal VScanIt is maintained
Low level.Now, second transistor T2 is in the conduction state, and light-emitting component OLED starts to light, and the 3rd node C current potential
Also it is changed into VOLED。VOLEDFor the current potential of light-emitting component OLED anodes when lighting.Now, due to Section Point B and first node A
Coupled by second transistor T2, two node potentials are identical, node A (B) is changed into due to storage capacitance C1 coupling：
It can be drawn by (1-2), the electric current that glow phase flows through light-emitting component OLED is：
Wherein, μn、Cox, W, L be respectively driving transistor T1 effective mobility, unit area gate capacitance, channel width
And channel length.From (1-3) as can be seen that finally flowing through light-emitting component OLED electric current and driving transistor T1 threshold voltage
And the threshold voltages of OLED in itself are all unrelated, so that the image element circuit of this example can be very good the uneven of compensation display
Property.
It should be noted that in other embodiments, when there is multirow image element circuit and using while when by the way of luminous,
Then should each row Section Point B data voltage VDATAAfter the completion of write-in, LED control signal VEMSecond significant level just arrives.
Advantage of this embodiment is that, circuit structure is simple, and only three transistors and a storage capacitance can increase picture
Plain aperture opening ratio, can reduce light-emitting component OLED current density, improve light-emitting component OLED service lifes；Circuit is using charging
The threshold value extracting mode of formula, i.e. source follower structure, have compensating action, institute is in this way for using for positive negative threshold value
The transistor of depletion type is equally effective；Also, in other embodiments, when circuit is using simultaneously luminous drive pattern,
It is possible to prevente effectively from the influence of crosstalk during 3D is shown, in addition, during initialization and valve value compensation, circuit is in light-emitting component
OLED anode inputs a low level, and this low level can effectively extend light-emitting component OLED service life.
It should be noted that when each transistor uses P-type TFT, refer to Fig. 1 b, it drives process and figure
1a driving process is identical, and difference is：The significant level of each transistor turns is low level VL；In initial phase,
Second electrical level end VSS provides high level, and high level is charged to the 3rd node C (light-emitting component OLED negative electrode).
Embodiment two：
In embodiment one, the 3rd node C initialization current potential is provided by the first level terminal VDD or second electrical level end VSS,
The present embodiment part unlike the embodiments above is, the 4th transistor T4 is also included in image element circuit disclosed in the present embodiment,
To provide corresponding current potential to the 3rd node C.Fig. 3 a and Fig. 3 b are refer to, are a kind of image element circuit structure disclosed in the present embodiment
Figure.
4th transistor T4 the first pole is connected to the 3rd node C, and the 4th transistor T4 the second pole is used to input initially
Change current potential, the 4th transistor T4 control pole is used for input initialization control signal VIni.In initial phase, the 4th transistor
T4 response initialization control signals VIniSignificant level conducting, the 4th transistor T4 the second pole transmits the 4th to the 3rd node C
The initialization current potential of transistor T4 the second pole input.
It should be noted that when driving transistor T1, second transistor T2, third transistor T3 and the 4th transistor T4 are
During N-type TFT, Fig. 3 a are refer to, the initialization current potential of the 4th transistor T4 the second pole input is low level VL, just
Beginningization control signal VIniSignificant level be high level VH.As driving transistor T1, second transistor T2, third transistor T3
During with the 4th transistor T4 for P-type TFT, Fig. 3 b, the initialization electricity of the 4th transistor T4 the second pole input refer to
Position is high level VH, initialization control signal VIniSignificant level be low level VL。
By taking Fig. 3 a as an example, Fig. 4 is refer to, is the timing diagram that image element circuit shown in Fig. 3 a drives process.The image element circuit
Driving process is roughly the same with the driving process of embodiment one, includes successively：Initial phase, valve value compensation stage, data are write
Enter stage and glow phase, difference is initial phase, the 3rd node C low level VLBy the of the 4th transistor T4
Two poles provide rather than provided by the first level terminal VDD, and remaining all drives process identical with the driving process of embodiment one, herein
Repeat no more.
It should be noted that because the 3rd node C initialization current potential is low level VL, therefore, the 4th transistor T4's
Second can extremely be connected to second electrical level end VSS, refer to Fig. 5 a, from second electrical level end VSS to the second of the 4th transistor T4
Pole provides low level VLInitialization current potential.
Certainly, when using i.e. each transistor of the image element circuit shown in Fig. 3 b for P-type TFT, initialization control letter
Number VIniSignificant level be low level VL, the initialization current potential that the 4th transistor T4 the second pole is provided is high level VH.Now,
The second of 4th transistor T4 can extremely be connected to the first level terminal VDD, refer to Fig. 5 b, from the first level terminal VDD to the 4th
Transistor T4 the second pole provides high level VHInitialization current potential.
Compared to embodiment one, advantage of this embodiment is that the first level terminal VDD or second electrical level end VSS is constant
High level VHOr low level VL, it is not necessary to output initialization current potential.When the first level terminal VDD or second electrical level end VSS is perseverance
When determining current potential, SECO is more easy to realize.
Embodiment three：
Fig. 6 a and Fig. 6 b are refer to, are image element circuit structure figure disclosed in the present embodiment, part unlike the embodiments above
It is, the 4th transistor T4 the second pole is used to be coupled to data wire DATA, the initialization current potential of the 4th the second poles of transistor T4
There is provided by data wire DATA.
Fig. 7 is refer to, is the driver' s timing figure of image element circuit shown in the present embodiment Fig. 6 a, the drive of the present embodiment image element circuit
The driving process of dynamic process and embodiment two is substantially the same, and difference is, in initial phase, the 3rd node C's is initial
Change current potential (such as low level VL) provided by data wire DATA, in valve value compensation stage and data write phase, data wire DATA
Then reference potential V is provided respectively to third transistor T3REFWith data voltage VDATA。
Specific work process shown in Fig. 6 a is：
In initial phase, initialization control signal VIniIt is changed into significant level high level, the 4th transistor T4 is placed in
Conducting state, scanning signal VScanWith LED control signal VEMAlso simultaneously at significant level high level, transistor T2 and T3
In the initialization current potential low level V in conducting state, data wire DATALIt is written to simultaneously by transistor T4 in the 3rd node C,
It is written to by transistor T3 and T2 in first node A and Section Point B, three nodes A, B and C current potential is in low electricity together
Flat VL。
At the valve value compensation stage, initialization control signal VIniIt is changed into low level VL, the 4th transistor T4 is in cut-off
State.Scanning signal VScanWith LED control signal VEMSignificant level high level is kept, data wire DATA outputs are with reference to electricity
Position VREF, this reference potential is input to node A and B by transistor T3 and T2 so that node A and B level are VREF.First level
VDD is held to be charged by driving transistor T1 to node C.Remaining driving process and embodiment two are identical, and here is omitted.
Compared to embodiment two, the advantage of this implementation example is that lacked one provides just to the 4th the second poles of transistor T4
The power line of beginningization current potential, reduces process complexity, simplifies structure.
It should be noted that for the image element circuit shown in Fig. 6 b, it drives process and Fig. 6 a driving Principle of Process phase
Seemingly, difference is, the significant level of image element circuit shown in Fig. 6 b is low level, and initialization current potential is high level.Herein not
Repeat again.
Example IV：
Fig. 8 a and Fig. 8 b are refer to, are image element circuit structure figure disclosed in the present embodiment, part unlike the embodiments above
It is, the 4th transistor T4 control pole is connected to the 4th transistor T4 the first pole；In initial phase, the 4th transistor T4
The initialization control signal V that is inputted of control poleIniSignificant level by the 4th transistor T4 the first pole provide.
Fig. 9 is refer to, is the driving process timing diagram of circuit shown in the present embodiment Fig. 8 a, the drive of the present embodiment image element circuit
Dynamic process is roughly the same with the driving process of embodiment two, and difference is the offer of the node C current potentials of initial phase the 3rd
The closing mode of mode and the transistor T4 of valve value compensation stage the 4th.
Specific work process is：In initial phase, the current potential Vx of the 4th the second poles of transistor T4 input is initialization electricity
Position such as low level, now, because the 4th transistor T4 control pole is connected to its first pole, then passes through diode connection side
4th transistor T4 of formula discharges the 3rd node C, so that the 3rd node C current potentials be dragged down, completes the 3rd node C current potentials
Initialization.In valve value compensation stage and follow-up phase, the current potential Vx of the 4th the second poles of transistor T4 input is changed into high level, made
4th transistor T4 is in cut-off state.Remaining driving process and embodiment two are identical, and here is omitted.
Compared to embodiment two, the advantage of this implementation example is to have lacked a power line, reduces process complexity, letter
Structure is changed.
It should be noted that for the image element circuit shown in Fig. 8 b, it drives process and Fig. 8 a driving Principle of Process phase
Seemingly, difference is, the significant level of image element circuit shown in Fig. 8 b is low level, and initialization current potential is high level.Herein not
Repeat again.
Embodiment five：
Figure 10 a and Figure 10 b are refer to, are a kind of image element circuit structure figure disclosed in the present embodiment, with above-described embodiment not
It is with part, the 5th transistor T5, the reference potential needed for first node A is also included in image element circuit disclosed in the present embodiment
VREFTransmitted by the 5th transistor T5, data wire DATA then only provides data-signal VDATA, so that simplify data wire DATA when
Sequence is controlled.Specifically, image element circuit includes：Driving for being connected between the first level terminal VDD and second electrical level end VSS is brilliant
Body pipe T1 and light-emitting component OLED, and second transistor T2, third transistor T3, the 4th transistor T4, the 5th transistor T5
With storage capacitance C1.Wherein, in the image element circuit shown in Figure 10 a, each transistor (driving transistor T1, second transistor T2,
Three transistor T3, the 4th transistor T4 and the 5th transistor T5) it is N-type TFT；In image element circuit shown in Figure 10 b,
Each transistor (driving transistor T1, second transistor T2, third transistor T3, the 4th transistor T4 and the 5th transistor T5) is
P-type TFT.
Driving transistor T1 the first pole is connected to light-emitting component OLED first end the 3rd node C of formation, drives crystal
Pipe T1 the second pole and light-emitting component OLED the second end are respectively used to be connected to the first level terminal VDD and second electrical level end VSS.
In one embodiment, Figure 10 a are refer to, light-emitting component OLED first end is anode, and light-emitting component OLED the second end is
Negative electrode；Driving transistor T1 the second pole is used to be connected to the first level terminal VDD, and light-emitting component OLED the second end is used to connect
To second electrical level end VSS.In another embodiment, Figure 10 b are refer to, light-emitting component OLED first end is negative electrode, is lighted
Element OLED the second end is anode；Driving transistor T1 the second pole is used to be connected to second electrical level end VSS, light-emitting component
OLED the second end is used to be connected to the first level terminal VDD.
The first pole that driving transistor T1 control pole is connected to second transistor T2 forms first node A, the second crystal
The first pole that pipe T2 the second pole is connected to third transistor T3 forms Section Point B, and second transistor T2 control pole is used for
Input LED control signal VEM。
Third transistor T3 the second pole is used to be connected to data wire DATA, in a particular embodiment, and data wire DATA is used
In offer data-signal VDATA, third transistor T3 control pole is for inputting scanning signal VScan。
5th transistor T5 the first pole is connected to first node A, and the 5th transistor T5 the second pole, which is used to input, to be referred to
Current potential VREF, the 5th transistor T5 control pole is connected to third transistor T3 control pole.
4th transistor T4 the first pole is connected to the 3rd node C, and the 4th transistor T4 the second pole is used to input initially
Change current potential, the 4th transistor T4 control pole is used for input initialization control signal VIni。
Storage capacitance C1 is connected between Section Point B and the 3rd node C.
In a particular embodiment, image element circuit works in first stage, second stage and phase III successively.In this implementation
In example, the first stage is initial phase, and second stage can include valve value compensation stage and data write phase, the 3rd successively
Stage is glow phase.
In the first stage, the 4th transistor T4 responds initialization control signal VIniSignificant level conducting initialization the 3rd
Node C current potential；Or, it is preferable that in the first stage, second transistor T2 is also responsive to LED control signal VEMIt is first effective
Level conducting initialization first node A and Section Point B current potential, also, LED control signal VEMThe first significant level knot
The beam time is earlier than initialization control signal VIniThe significant level end time.
In second stage, the 5th transistor T5 and third transistor T3 responding scanning signals VScanSignificant level conducting,
5th transistor T5 of conducting transmits reference potential V to first node AREF, the third transistor T3 of conducting passes to Section Point B
Transmission of data signal VDATA；Driving transistor T1 controls electrode potential (such as grid potential, correspondence first node A current potential) at it
VREFIn the presence of turn on, the driving transistor T1 of conducting can transmit the first level terminal VDD or second electrical level end VSS telecommunications
Number with adjust (can be charging or electric discharge) the 3rd node C current potential, until node C current potential is adjusted to VREF-
VTHWhen, driving transistor T1 then enters cut-off state, and now, the 3rd node C current potential will be maintained VREF-VTH, the current potential
Stored by storage capacitance C1, wherein, VTHFor driving transistor T1 threshold voltage.In the phase III, second transistor T2 rings
Answer LED control signal VEMThe conducting of the second significant level, driving transistor T1 responses first node A current potential conducting driving hair
Optical element OLED lights.
It should be noted that in one embodiment, refer to Figure 10 a, LED control signal VEMSignificant level (including the
One significant level and the second significant level), initialization control signal VIniSignificant level and scanning signal VScanSignificant level
It is high level；In another embodiment, Figure 10 b, LED control signal V refer toEMSignificant level (including first is effective
Level and the second significant level), initialization control signal VIniSignificant level and scanning signal VScanSignificant level be low
Level.
In the present embodiment, initialization control signal VIni, scanning signal VScanSignificant level and LED control signal VEM
The second significant level arrive successively.
Due to initialization control signal VIniSignificant level be ahead of scanning signal VScanSignificant level arrive the time,
Therefore, when there is multirow image element circuit, and light line by line, the initialization control signal that the 4th transistor T4 control poles are inputted
VIniCan be preferably by the scanning signal V of upper level image element circuitScanThere is provided, i.e. the transistor T4 of one's own profession image element circuit the 4th controls
Lastrow image element circuit third transistor T3 control pole can be extremely preferably coupled to.
Hereafter image element circuit driving process disclosed in the present embodiment is explained by taking Figure 10 a as an example.The picture of the present embodiment
Plain circuit drives process is divided into initial phase, valve value compensation stage, data write phase and glow phase, is as shown in figure 11
The signal sequence of the present embodiment, the driving process of the present embodiment is specifically described with reference to Figure 11 and Figure 10 a.
In initial phase：Initialization control signal VIniFor significant level high level, the 4th transistor T4 is placed in conducting
State, the 4th transistor T4 the second pole input initialization current potential low level VL, and write by the 4th transistor T4 of conducting
Into the 3rd node C.Then, the 3rd node C current potential is reduced to initialization current potential low level VL, in storage capacitance C1 coupling
Under, Section Point B current potential is also dragged down.In a preferred embodiment, when having just enter into initial phase, LED control signal VEM
Can be significant level high level, after a period of time is postponed into initial phase, LED control signal VEMIt is changed into low electricity
It is flat.In LED control signal VEMDuring for significant level high level, the 3rd node C can be incited somebody to action by storage capacitance C1 coupling
First node A and Section Point B current potential are dragged down, and dragging down first node A current potential can prevent high current from flowing through luminous member
Part OLED.
In data write-in and valve value compensation stage：Initialization control signal VIniIt is changed into low level, makes at the 4th transistor T4
In cut-off state；Scanning signal VScanIt is changed into significant level high level, makes transistor T3 and T5 in the conduction state, the 5th crystal
The reference potential V of the poles of pipe T5 second inputREFIt is written to by the 5th transistor T5 of conducting in first node A, data wire DATA
The data voltage V of offerDATAIt is written to by third transistor T3 in Section Point B.At the same time, driving transistor T1 is in
Conducting state, the first level terminal VDD is charged by driving transistor T1 to the 3rd node C, therefore, the 3rd node C current potential meeting
Slowly raise, until it is increased to VREF-VTHWhen, driving transistor T1 can enter cut-off state, the 3rd node C current potential
V will be maintainedREF-VTH.Wherein VTHFor driving transistor T1 threshold voltage.Data input and valve value compensation stage terminate
Afterwards, driving transistor T1 threshold voltage information is just stored on node C by storage capacitance C1.It should be noted that
VREF-VTHLess than light-emitting component OLED threshold voltage, to ensure that light-emitting component OLED does not light in two stages.
In glow phase：Scanning signal VScanIt is changed into low level, transistor T3 and T5 is in cut-off state；Light emitting control
Signal VEMIt is changed into significant level high level so that second transistor T2 is in the conduction state, now, light-emitting component OLED starts hair
Light, and the 3rd node C current potential is also changed into VOLED。VOLEDFor the current potential of light-emitting component OLED anodes when lighting.Now, by
It is of coupled connections in Section Point B and first node A by second transistor T2, two node potentials are identical, node A (B) is due to depositing
Storing up electricity is held C1 coupling and is changed into：
VnodeA=VOLED+VDATA-VREF+VTH …(4-1)
It can be drawn by (4-1), the electric current that glow phase flows through OLED is：
Wherein, μn、Cox, W, L be respectively driving transistor T1 effective mobility, unit area gate capacitance, channel width
And channel length.From (4-2) as can be seen that finally flowing through light-emitting component OLED electric current and driving transistor T1 threshold voltage
And the threshold voltages of light-emitting component OLED in itself are all unrelated, so that the image element circuit of this example can be very good compensation display
Inhomogeneities.
For traditional progressive scan light-emitting mode, first in the example with multirow image element circuit, can be preferred to use
Level terminal VDD is a constant potential, the scanning signal V of each rowScanNeed not at a time simultaneously export high level or
Low level pulse.
It should be noted that when each transistor uses P-type TFT, refer to Figure 10 b, it drives process and figure
10a driving process is identical, and difference is：The significant level of each transistor turns is low level VL；In initial phase,
4th transistor T4 the second pole provides high level, and high level V is charged to the 3rd node C (light-emitting component OLED negative electrode)H。
Relative to above-described embodiment, embodiment adds signal wire required during image element circuit driving, be conducive to sequential
Control.
The present embodiment also discloses a kind of display circuit driving method, and display circuit is electric using the pixel of above-described embodiment
Road, each drive cycle of image element circuit includes initial phase, valve value compensation stage, data write phase and glow phase,
Driving method includes：
In initial phase, second transistor T2 conductings, current potential and the driving that storage capacitance C1 two ends are initialized respectively are brilliant
The current potential of body pipe T1 control poles.In other embodiments, the 4th transistor T4, auxiliary initialization storage capacitance C1 can also be turned on
The current potential at two ends.
In the valve value compensation stage, third transistor T3 and/or the 5th transistor T5 conductings, to driving transistor T1 control poles
Reference potential is provided, driving transistor T1 threshold voltage information is read and is stored by storage capacitance C1.In a kind of embodiment
In, reference potential can be provided by third transistor T3；In another embodiment, it can also be carried by the 5th transistor T5
Current potential for reference.
In data write phase, third transistor T3 conducting transmission data voltages VDATAAnd it is stored in storage capacitance C1.
It should be noted that in a particular embodiment, valve value compensation stage and data write phase can also be carried out simultaneously,
Third transistor T3 and the 5th transistor T5 are for example simultaneously turned on, reference potential is provided by the 5th transistor T5, by the 3rd crystal
Pipe T3 transmission data voltages VDATA, it is achieved thereby that driving transistor T1 threshold voltage compensations and data voltage VDATAWhat is write is same
Shi Jinhang.
In glow phase, the first transistor T1 produces driving current according to the pressure differential at storage capacitance C1 two ends, and drives
Dynamic light-emitting component OLED lights.
Embodiment six：
The present embodiment also discloses a kind of display device, refer to Figure 12, is the also disclosed display device knot of the present embodiment
Structure schematic diagram, the display device includes：
Display panel 100, display panel 100 includes being arranged in the image element circuit that above-described embodiment of n row m column matrix is provided
Pixel [1] [1] ... Pixel [n] [m], wherein, n and m are the integer more than 0, and Pixel [n] [m] characterizes the picture of line n m row
Plain circuit；The multi-strip scanning line Gate [1] ... Gate [n] for the first direction (such as horizontal) being connected with each pixel, wherein,
Gate [n] represents the corresponding scan line of line n image element circuit, for providing scan control letter to offer to one's own profession image element circuit
Number, such as initialization control signal VIni, scanning signal VScan, LED control signal VEMDeng；With second direction (such as longitudinal)
A plurality of data lines Data [1] ... Data [m], wherein, Data [m] represents the corresponding data wire of m row image element circuits, for carrying
For the data voltage V of each image element circuitDATA.Display panel can be liquid crystal display panel, organic electroluminescence display panel, Electronic Paper
Display panel etc., and corresponding display device can be liquid crystal display, OLED, electric paper display etc..Need
It is noted that in other embodiments, some scan control signals needed for image element circuit can also be by the sides of global lines
Formula is provided, such as power line, initialization control signal V needed for the first level terminalIniRequired initialization control line, threshold value
Control line and light emitting control line etc. are extracted, those skilled in the art can adjust according to the demand of specific image element circuit.
Gate driving circuit 200, for producing scanning pulse signal, and each horizontal scanning line by being formed in the first direction
Gate [1] ... Gate [n] provide required control signal to image element circuit.
Data drive circuit 300, it is right with it in display panel 100 that the signal output part of data drive circuit 300 is coupled to
On the data wire Data [1] ... Data [m] answered, the data voltage signal V that data drive circuit 300 is producedDATAPass through data
Line Data [1] ... Data [m] are transferred in corresponding pixel cell to realize gradation of image.
Controller 400, controller 400 is used to provide control sequential to gate driving circuit and data drive circuit.
Use above specific case is illustrated to the present invention, is only intended to help and is understood the present invention, not to limit
The system present invention.For those skilled in the art, according to the thought of the present invention, it can also make some simple
Deduce, deform or replace.
Claims (8)
1. a kind of image element circuit, it is characterised in that including：
For driving transistor (T1) and the light-emitting component being connected between the first level terminal (VDD) and second electrical level end (VSS)
, and second transistor (T2), third transistor (T3) and storage capacitance (C1) (OLED)；
First pole of driving transistor (T1) is connected to first end the 3rd node (C) of formation of light-emitting component (OLED), and driving is brilliant
Second pole of body pipe (T1) and the second end of light-emitting component (OLED) are respectively used to be connected to the first level terminal (VDD) and the second electricity
Flush end (VSS)；
The first pole that the control pole of driving transistor (T1) is connected to second transistor (T2) forms first node (A), and second is brilliant
The first pole that second pole of body pipe (T2) is connected to third transistor (T3) forms Section Point (B), second transistor (T2)
Control pole is used to input LED control signal (VEM)；
Second pole of third transistor (T3) is used to be connected to for providing data-signal (VDATA) or reference potential (VREF)
Data wire (DATA), the control pole of third transistor (T3) is used to input scanning signal (VScan)；
Storage capacitance (C1) is connected between Section Point (B) and the 3rd node (C)；
In the first stage, second transistor (T2) and third transistor (T3) respond LED control signal (V respectivelyEM) first have
Imitate level and scanning signal (VScan) the conducting of the first significant level, to first node (A) and Section Point (B) transmission with reference to electric
Position (VREF) initialization first node (A) and Section Point (B) current potential, provided by corresponding signal source to the 3rd node (C)
Current potential is initialized, and reads the threshold voltage (V of driving transistor (T1)TH)；
In second stage, second transistor (T2) is by LED control signal (VEM) control in cut-off state, third transistor (T3)
Responding scanning signal (VScan) the second significant level turn on to Section Point (B) transmission data-signal (VDATA)；
In the phase III, third transistor (T3) is by scanning signal (VScan) control is in cut-off state, second transistor (T2) is responded
LED control signal (VEM) the second significant level conducting, driving transistor (T1) response first node (A) current potential conducting drive
Dynamic light-emitting component (OLED) lights.
2. image element circuit as claimed in claim 1, it is characterised in that the first stage includes successively：Initial phase and
The valve value compensation stage；
Second pole of driving transistor (T1) is used to be connected to the first level terminal (VDD), and the second end of light-emitting component (OLED) is used
In being connected to second electrical level end (VSS)；In initial phase, the first level terminal is transmitted in the second pole of driving transistor (T1)
(VDD) initialization current potential initializes the current potential of the 3rd node (C)；In valve value compensation stage, the second of driving transistor (T1)
The significant level of the first level terminal (VDD) is transmitted in pole, and storage capacitance (C1) is according to the current potential and the 3rd node of Section Point (B)
(C) current potential reads the threshold voltage (V of driving transistor (T1)TH)；Or,
Second pole of driving transistor (T1) is used to be connected to second electrical level end (VSS), and the second end of light-emitting component (OLED) is used
In being connected to the first level terminal (VDD)；In initial phase, the second pole transmission second electrical level end of driving transistor (T1)
(VSS) initialization current potential initializes the current potential of the 3rd node (C)；In valve value compensation stage, the second of driving transistor (T1)
The significant level of pole transmission second electrical level end (VSS), storage capacitance (C1) is according to the current potential and the 3rd node of Section Point (B)
(C) current potential reads the threshold voltage (V of driving transistor (T1)TH)。
3. image element circuit as claimed in claim 1, it is characterised in that also including the 4th transistor (T4), the first stage
Include successively：Initial phase and valve value compensation stage；
First pole of the 4th transistor (T4) is connected to the 3rd node (C), and the second pole of the 4th transistor (T4) is used to input just
Beginningization current potential, the control pole of the 4th transistor (T4) is used for input initialization control signal (VIni)；
In initial phase, the 4th transistor (T4) response initialization control signal (VIni) significant level conducting, to Section three
Point (C) transmits the initialization current potential of the second pole input of the 4th transistor (T4).
4. image element circuit as claimed in claim 3, it is characterised in that driving transistor (T1), second transistor (T2), the 3rd
Transistor (T3) and the 4th transistor (T4) are N-type TFT；
Second pole of driving transistor (T1) is used to be connected to the first level terminal (VDD), and the second end of light-emitting component (OLED) is used
In being connected to second electrical level end (VSS)；
Second pole of the 4th transistor (T4) is connected to second electrical level end (VSS), in initial phase, the 4th transistor (T4)
The initialization current potential of second pole input is provided by second electrical level end (VSS)；Or,
Second pole of the 4th transistor (T4) is used to be connected to data wire (DATA), in initial phase, the 4th transistor (T4)
The second pole input initialization current potential by data wire (DATA) provide.
5. image element circuit as claimed in claim 3, it is characterised in that driving transistor (T1), second transistor (T2), the 3rd
Transistor (T3) and the 4th transistor (T4) are P-type TFT；
Second pole of driving transistor (T1) is used to be connected to second electrical level end (VSS), and the second end of light-emitting component (OLED) is used
In being connected to the first level terminal (VDD)；
Second pole of the 4th transistor (T4) is connected to the first level terminal (VDD), in initial phase, the 4th transistor (T4)
The initialization current potential of second pole input is provided by the first level terminal (VDD)；Or,
Second pole of the 4th transistor (T4) is used to be connected to data wire (DATA), in initial phase, the 4th transistor (T4)
The second pole input initialization current potential by data wire (DATA) provide.
6. the image element circuit as described in claim 3-5 any one, it is characterised in that the control pole of the 4th transistor (T4) connects
It is connected to the first pole of the 4th transistor (T4)；In initial phase, the initialization that the control pole of the 4th transistor (T4) is inputted
Control signal (VIni) significant level by the 4th transistor (T4) the first pole provide.
7. a kind of display device, it is characterised in that including：
Image element circuit matrix, the image element circuit matrix include be arranged in n row m column matrix such as claim 1-6 any one
Described image element circuit, the n and m are the integer more than 0；
Gate driving circuit, for producing scanning pulse signal, and by each horizontal scanning line for being formed in the first direction to pixel
Circuit provides required control signal；
Data drive circuit, the data voltage signal of half-tone information is represented for producing, and each by what is formed in a second direction
Data wire provides data-signal to image element circuit；
Controller, for providing control sequential to gate driving circuit and data drive circuit.
8. a kind of pixel circuit drive method, it is characterised in that it is any that the pixel circuit drive method is used for claim 1-6
Image element circuit described in one, each drive cycle of the image element circuit includes initial phase, valve value compensation stage, data
Write phase and glow phase, the driving method include：
In the initial phase, second transistor (T2) conducting initializes current potential and the drive at storage capacitance (C1) two ends respectively
The current potential of dynamic transistor (T1) control pole；
In the valve value compensation stage, third transistor (T3) and/or the conducting of the 5th transistor (T5), to driving transistor (T1)
Control pole provides reference potential, reads the threshold voltage information of driving transistor (T1) and is stored by storage capacitance (C1)；
In the data write phase, third transistor (T3) conducting transmission data voltage VDATAAnd it is stored in storage capacitance (C1)；
In the glow phase, the first transistor (T1) produces driving current according to the pressure differential at storage capacitance (C1) two ends,
And drive light-emitting component (OLED) to light.
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| CN201510122622.6A CN104715723B (en) | 2015-03-19 | 2015-03-19 | Display device and its image element circuit and driving method |
| PCT/CN2016/076344 WO2016146053A1 (en) | 2015-03-19 | 2016-03-15 | Display device, and pixel circuit and driving method thereof |
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| CN104715723A (en) | 2015-06-17 |
| WO2016146053A1 (en) | 2016-09-22 |
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