CN104702280A - Foreground automatic calibration system for time interleaving ADC (analog to digital converter) - Google Patents
Foreground automatic calibration system for time interleaving ADC (analog to digital converter) Download PDFInfo
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Abstract
The invention discloses a foreground automatic calibration system for a time interleaving ADC (analog to digital converter). The foreground automatic calibration system for the time interleaving ADC comprises multiple paths of subsidiary ADCs, wherein input ends of all the subsidiary ADCs are connected with an input signal or calibrating signal generator through an arranged multiplexer, output ends of all the subsidiary ADCs are connected with an input end of a calibration DLC (digital logic circuit), calibration signals generated by the calibration DLC are correspondingly connected with calibration control ends of all the subsidiary ADCs through a first output end, gating signals generated by the calibration DLC are connected with a control input end of the multiplexer through a second output end, and calibration mode signals generated by the calibration DLC are connected with a calibration mode control input end of the calibrating signal generator. The foreground automatic calibration system for the time interleaving ADC can achieve clock offset automatic calibration which can not be achieved through a traditional foreground calibration technology, and simultaneously does not significantly enlarge a scale or increase complexity of the circuit.
Description
Technical field
The present invention relates to a kind of foreground automated calibration system for time-interleaved analog to digital converter.
Background technology
At present, analog to digital converter (ADC) is circuit analog signal being converted to digital signal.In broadband data transmission, wireless telecommunications and all kinds of instrument system, ADC plays key player.In recent years, along with deepening continuously of digitlization process and improving constantly of communication system bandwidth, requirements at the higher level are proposed to the sampling rate of adc circuit and precision.But be limited to semiconductor process technology, the performance of single analog to digital converter ADC reaches bottleneck, be difficult to improve.
Time-interleaved technology is one of most effective method improving ADC sample rate further, its core concept utilizes the sub-ADC of multichannel alternately to sample to input signal in the different moment respectively, the ADC whole-sample rate 1/N that the sampling rate of every sub-ADC is only, wherein N is the number of sub-ADC.Adopt time-interleaved technology, can increase substantially sampling rate, the design difficulty of every way ADC also decreases simultaneously.
The main weakness of time-interleaved technology is: due to the impact of the non-ideal factor such as asymmetry of process deviation, Temperature Distribution, domain, the each way ADC participating in interweaving may show different characteristics, and the deviation of sub-ADC characteristic will have a strong impact on the overall performance of time-interleaved ADC.These errors mainly comprise: gain error, offset error and clock jitter.
In order to eliminate or reduce the impact of all kinds of error, usual clock intertexture ADC can introduce automated calibration system.Different according to the implementation of collimation technique, background calibration techniques and Foreground calibration technology can be divided into.Wherein, background calibration techniques directly carries out Digital Signal Processing to output data, therefrom extracts the value of three class errors, and to the technology that digital signal is revised.Foreground calibration technology, usually need a reference signal accurately, each way ADC samples to reference signal, by comparing the value exporting data and reference signal, obtaining the value of all kinds of error, and carrying out adjusting to eliminate error accordingly to circuit.
The shortcoming of background calibration techniques is, this technical requirement error calibration circuit carries out Digital Signal Processing to the mass data that ADC continuous sampling obtains, this speed to error calibration circuit, scale propose very high requirement, for the high-speed ADC of sampling rate to more than GSPS, area shared by error calibration circuit is large, power consumption is high.The benefit of Foreground calibration technology is the partial data of the just ADC sampling for calibrating, do not need continuous sampling, therefore the data volume of error calibration circuit process is few, shared area is little, low in energy consumption, be suitable for the adc circuit of high sampling rate, but adopt the intertexture adc circuit of traditional Foreground calibration technology, can only realize the automatic calibration of gain error and offset error, clock jitter then needs artificial adjustment.In the process of carrying out clock jitter calibration, traditional mode is the sine wave source of the precision input of intertexture ADC being connected to an ADC outside, by carrying out computational analysis to the output of each way ADC, calculate sampling clock deviation and to corresponding calibration, this mode needs the input of manual switching ADC, accurate sine wave source, complicated process of calculation analysis, be difficult to this clock jitter calibration process is changed into circuit and is integrated in ADC chip internal, automatic calibration on sheet cannot be realized.
Summary of the invention
The defect that the present invention seeks to exist for prior art provides a kind of foreground automated calibration system for time-interleaved analog to digital converter, it not only can realize the automatic calibration of gain and imbalance, also the automatic calibration of clock jitter can be realized, all circuit are all integrated on ADC chip, and the chip area shared by error calibration circuit is little, consumed power is low.
The present invention for achieving the above object, adopt following technical scheme: a kind of foreground automated calibration system for time-interleaved analog to digital converter, comprise the multichannel sub-adc converter ADC of setting, the input of sub-adc converter ADC described in every road is all connected to input signal or calibration signal generator by the multiplexer arranged, and the output of sub-adc converter ADC described in every road is all connected to the input of calibration Digital Logical Circuits; The calibrating signal that described calibration Digital Logical Circuits produces is connected with the calibration control end of sub-adc converter ADC described in corresponding every road by the first output, its gating signal produced is connected with the control input end of multiplexer by the second output, and its calibration mode signal produced is connected with the calibration mode control input end of calibration signal generator by the 3rd output.
Further, described calibration signal generator has three kinds of mode of operations, is mistuning calibration function pattern, gain calibration pattern and clock jitter calibration mode respectively.
Further, under mistuning calibration function pattern, it is the fixed level of 0 that described calibration signal generator produces differential output voltage.
Further, under gain calibration pattern, described calibration signal generator produces the fixed level that differential output voltage is the fixed level of a particular value.
Further, under clock jitter calibration mode, described calibration signal generator produces triangular signal or ramp signal, the frequency of this triangular signal or ramp signal is the 1/4-1/100 of intertexture analog to digital converter ADC clock frequency, and described triangular signal or ramp signal and intertexture analog to digital converter ADC clock irrelevant.
Preferably, the frequency of described triangular signal or ramp signal is 1/20 of intertexture analog to digital converter ADC clock frequency.Beneficial effect of the present invention: all error calibration circuits can be integrated in ADC chip internal by foreground of the present invention automated calibration system, it not only can realize the automatic calibration of gain and imbalance, also the automatic calibration of clock jitter can be realized, owing to only needing addition and displacement in calibration process, and the data volume of calibration circuit process only needs 1/4 ~ 1/200 of ADC actual samples data volume, the chip area therefore shared by calibration circuit is little, consumed power is low.
Relative to traditional background calibration techniques, technical scheme proposed by the invention does not need complicated high-speed digital video camera unit.For the high speed time intertexture ADC of sampling rate to more than GSPS, the throughput of its data is very large, and digital signal processing unit is difficult to realize.This programme is more suitable for high speed time intertexture ADC.
Compared with traditional Foreground calibration technology, technical scheme proposed by the invention can realize the clock jitter automatic calibration that traditional Foreground calibration technology cannot realize, and does not significantly increase scale and the complexity of circuit simultaneously.
Accompanying drawing explanation
Fig. 1 is the overall structure schematic diagram of foreground of the present invention automated calibration system.
Fig. 2 is the schematic diagram of every way analog to digital converter ADC of the present invention sampling instant.
Fig. 3 is the automatic calibration process flow diagram of foreground of the present invention automated calibration system.
Embodiment
Fig. 1 relates to a kind of foreground automated calibration system for time-interleaved analog to digital converter, comprise the multichannel sub-adc converter ADC of setting, the input of every way analog to digital converter ADC is all connected to input signal or calibration signal generator by the multiplexer arranged, and the output of every way analog to digital converter ADC is all connected to the input of calibration Digital Logical Circuits; The calibrating signal that calibration Digital Logical Circuits produces is connected with the calibration control end of corresponding every way analog to digital converter ADC by the first output, its gating signal produced is connected with the control input end of multiplexer by the second output, and its calibration mode signal produced is connected with the calibration mode control input end of calibration signal generator by the 3rd output.Known in figure, ADC1-ADCN represents the sub-adc converter ADC with 1-N road, the input of the sub-adc converter ADC on each road both can be connected to input signal, also can be connected to calibration signal generator, the gating signal produced by calibration Digital Logical Circuits controls multiplexer to realize the automatic switchover to input signal and calibration signal generator by its second output.Under calibration signal generator of the present invention can be operated in Three models, be mistuning calibration function pattern, gain calibration pattern and clock jitter calibration mode respectively.The calibration mode signal that above-mentioned three kinds of mode of operations produce by calibration Digital Logical Circuits controls calibration signal generator by its 3rd output.Under mistuning calibration function pattern, it is the fixed level of 0 that calibration signal generator produces differential output voltage.Under gain calibration pattern, calibration signal generator produces the fixed level that differential output voltage is a particular value.Under clock jitter calibration mode, calibration signal generator produces triangular wave or ramp signal, and the frequency of this triangular wave or ramp signal is the 1/4-1/100 of intertexture analog to digital converter ADC clock frequency, and this signal and intertexture analog to digital converter ADC clock irrelevant.Wherein, optimum clock frequency is 1/20.
After calibration process starts, calibration Digital Logical Circuits controls multiplexer gating calibration signal generator by gating signal, and be operated in mistuning calibration function pattern by calibration mode signal controlling calibration signal generator, it is the signal of 0 that calibration signal generator produces differential voltage, respective output and reference voltage level compare by each way analog to digital converter ADC respectively, according to the calibration control end of comparative result adjustment sub-adc converter ADC, until the output of each way analog to digital converter ADC is all identical with the reference voltage level preset.
Then calibrate Digital Logical Circuits and be operated in gain calibration pattern by calibration mode signal controlling calibration signal generator, it is the signal of particular value that calibration signal generator produces differential voltage, respective output and reference voltage level compare by each way ADC respectively, the calibration control end of sub-ADC is adjusted, until the output of each way ADC is all identical with the reference voltage level preset according to comparative result.
After the calibration completing offset error and gain error, start to calibrate clock jitter.Now calibration signal generator is operated in clock jitter calibration mode, and produce triangular signal or ramp signal, each way analog to digital converter ADC alternately sampled to triangular signal in the different moment.Usually the frequency of this triangular signal or ramp signal is far below the sample rate of intertexture analog to digital converter ADC.Give the schematic diagram of the sub-adc converter ADC sampling instant on every road in Fig. 2, wherein Si-1, Si, Si+1 represent the sampling instant of the i-th-1 tunnel, i road, i+1 way analog to digital converter ADC respectively.Change linearly over time because input signal has, the data that each way analog to digital converter ADC gathers are also with sampling instant linear change.By judging the size of the absolute value of the difference of adjacency channel sub-adc converter ADC image data, the whether advanced or delayed information of sampling instant just can be obtained.Such as, in Fig. 2 | Si-Si-1|>|Si+1-Si|, the sampling instant namely representing i way analog to digital converter ADC is delayed.In order to the impact that noise decrease judges sampling instant, repeatedly cumulative mode is have employed in the present invention, the absolute value of the difference of adjacency channel sub-adc converter ADC image data is repeatedly added up, is then judged by calibration Digital Logical Circuits, thus improve the reliability of system.
Good linear in order to ensure that accumulated data have, we need to screen data.As shown in Figure 2, when only having each sampled point to be all arranged in the effective coverage of figure in one group of data, these group data are just considered to effective.This is because the circuit for generating triangular wave of reality has certain non-linear, especially signal reach or close to maximum, minimum value time, non-linear comparatively obvious.Can problems be avoided by delimiting effective coverage, improving the precision of calibration system judgement.Similar principle is also applicable to ramp signal.
In addition, the order of the mistuning calibration function pattern of foreground of the present invention automated calibration system, gain calibration pattern and clock jitter calibration mode is not limited to the last clock jitter calibration of gain calibration again of first mistuning calibration function.See Fig. 3, it is the automatic calibration process flow diagram of foreground of the present invention automated calibration system.The order of these three kinds of calibration modes can change arbitrarily or carries out separately, namely also first can calibrate a certain class error that clock jitter is calibrated offset error, gain error again or calibrated separately in this three classes error.
These are only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. the foreground automated calibration system for time-interleaved analog to digital converter, it is characterized in that, comprise the multichannel sub-adc converter ADC of setting, the input of sub-adc converter ADC described in every road is all connected to input signal or calibration signal generator by the multiplexer arranged, and the output of sub-adc converter ADC described in every road is all connected to the input of calibration Digital Logical Circuits; The calibrating signal that described calibration Digital Logical Circuits produces is connected with the calibration control end of sub-adc converter ADC described in corresponding every road by the first output, its gating signal produced is connected with the control input end of multiplexer by the second output, and its calibration mode signal produced is connected with the calibration mode control input end of calibration signal generator by the 3rd output.
2. a kind of foreground automated calibration system for time-interleaved analog to digital converter as claimed in claim 1, it is characterized in that, described calibration signal generator has three kinds of mode of operations, is mistuning calibration function pattern, gain calibration pattern and clock jitter calibration mode respectively.
3. a kind of foreground automated calibration system for time-interleaved analog to digital converter as claimed in claim 2, is characterized in that, under mistuning calibration function pattern, it is the fixed level of 0 that described calibration signal generator produces differential output voltage.
4. a kind of foreground automated calibration system for time-interleaved analog to digital converter as claimed in claim 2, it is characterized in that, under gain calibration pattern, described calibration signal generator produces the fixed level that differential output voltage is the fixed level of a particular value.
5. a kind of foreground automated calibration system for time-interleaved analog to digital converter as claimed in claim 2, it is characterized in that, under clock jitter calibration mode, described calibration signal generator produces triangular signal or ramp signal, the frequency of this triangular signal or ramp signal is the 1/4-1/100 of intertexture analog to digital converter ADC clock frequency, and described triangular signal or ramp signal and intertexture analog to digital converter ADC clock irrelevant.
6. a kind of foreground automated calibration system for time-interleaved analog to digital converter as claimed in claim 5, it is characterized in that, the frequency of described triangular signal or ramp signal is 1/20 of intertexture analog to digital converter ADC clock frequency.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106341132A (en) * | 2016-08-08 | 2017-01-18 | 中国工程物理研究院电子工程研究所 | Error blind correction method for time interleaved sampling ADC (Analog-to-Digital Converter) |
| CN108011636A (en) * | 2017-12-20 | 2018-05-08 | 武汉邮电科学研究院 | A kind of dc-couple passage for time-interleaved ADC calibrates circuit |
| US10312927B1 (en) | 2018-03-26 | 2019-06-04 | Qualcomm Incorporated | Calibration for time-interleaved analog-to-digital converters and signal generators therefor |
| CN110048717A (en) * | 2019-03-20 | 2019-07-23 | 新岸线(北京)科技集团有限公司 | It is a kind of to realize the time-interleaved self-alignment method and device of analog-digital converter |
| CN111130546A (en) * | 2019-12-31 | 2020-05-08 | 无锡矽杰微电子有限公司 | ADC automatic calibration method based on hardware dichotomy |
| CN114244359A (en) * | 2021-12-22 | 2022-03-25 | 厦门半导体工业技术研发有限公司 | Calibration method and calibration module of analog-to-digital converter and analog-to-digital converter |
| CN116488650A (en) * | 2023-03-28 | 2023-07-25 | 江苏谷泰微电子有限公司 | Time skew error detection method for time domain interleaving analog-to-digital converter |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106341132A (en) * | 2016-08-08 | 2017-01-18 | 中国工程物理研究院电子工程研究所 | Error blind correction method for time interleaved sampling ADC (Analog-to-Digital Converter) |
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| CN108011636A (en) * | 2017-12-20 | 2018-05-08 | 武汉邮电科学研究院 | A kind of dc-couple passage for time-interleaved ADC calibrates circuit |
| CN108011636B (en) * | 2017-12-20 | 2020-06-09 | 武汉邮电科学研究院 | Direct-current coupling channel calibration circuit for time-interleaved ADC (analog to digital converter) |
| US10312927B1 (en) | 2018-03-26 | 2019-06-04 | Qualcomm Incorporated | Calibration for time-interleaved analog-to-digital converters and signal generators therefor |
| CN110048717A (en) * | 2019-03-20 | 2019-07-23 | 新岸线(北京)科技集团有限公司 | It is a kind of to realize the time-interleaved self-alignment method and device of analog-digital converter |
| CN111130546A (en) * | 2019-12-31 | 2020-05-08 | 无锡矽杰微电子有限公司 | ADC automatic calibration method based on hardware dichotomy |
| CN111130546B (en) * | 2019-12-31 | 2023-04-07 | 无锡矽杰微电子有限公司 | ADC automatic calibration method based on hardware dichotomy |
| CN114244359A (en) * | 2021-12-22 | 2022-03-25 | 厦门半导体工业技术研发有限公司 | Calibration method and calibration module of analog-to-digital converter and analog-to-digital converter |
| CN114244359B (en) * | 2021-12-22 | 2023-01-10 | 厦门半导体工业技术研发有限公司 | Calibration method and calibration module of analog-to-digital converter and analog-to-digital converter |
| CN116488650A (en) * | 2023-03-28 | 2023-07-25 | 江苏谷泰微电子有限公司 | Time skew error detection method for time domain interleaving analog-to-digital converter |
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Address after: Room 708-1, Building 1, Northwest District, Suzhou Nanocity, No. 99 Jinjihu Avenue, Suzhou Industrial Park, Suzhou Area, China (Jiangsu) Free Trade Pilot Zone, Suzhou City, Jiangsu Province, 215124 Patentee after: Xunxin Microelectronics (Suzhou) Co.,Ltd. Address before: Unit A4-110 C, No. 218 Xinghu Street, Suzhou Industrial Park, Suzhou City, Jiangsu Province, 215000 Patentee before: ACELA MICRO CO.,LTD. |