CN104701305A - Double-chip flip chip structure - Google Patents
Double-chip flip chip structure Download PDFInfo
- Publication number
- CN104701305A CN104701305A CN201310650385.1A CN201310650385A CN104701305A CN 104701305 A CN104701305 A CN 104701305A CN 201310650385 A CN201310650385 A CN 201310650385A CN 104701305 A CN104701305 A CN 104701305A
- Authority
- CN
- China
- Prior art keywords
- chip
- substrate
- fin
- double
- filler
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15158—Shape the die mounting substrate being other than a cuboid
Abstract
The invention provides a double-chip flip chip structure by taking a flip chip structure as a starting point. The double-chip flip chip structure is characterized in that a substrate with a central partition plate is provided with two chip slots in certain gradients, and a plurality of semispherical grooves are formed at contact positions of the slot slopes and chip conducting projections; each chip is provided with a plurality of cylindrical conducting projections with semispherical tops; an upper cooling fin is fastened to the top of the substrate. The double-chip flip chip structure has the advantages of realization of self-alignment chip bonding, realization of integral packaging of double chips, high integration level, reduction of chip packaging area and improvement of a heat radiation function.
Description
Technical field
The present invention relates to semiconductor device packaging technique field, be specially a twin lamella composite packing structure.
Background technology
Flip chip bonding techniques (Flip Chip Interconnect Technology), also claiming " crystalline substance that falls encapsulates " or " brilliant package method ", is the one of chip encapsulation technology.This encapsulation technology is that chip bonding, on substrate, makes chip can be connected with electrical property of substrate via conductive projection by configuration and the conductive projection on the active surface of chip, and is electrically connected to outside electronic installation via the internal wiring of substrate.Flip chip bonding techniques is applicable to the chip-packaging structure of high pin number, and has simultaneously and reduce chip package area and shorten the advantage such as signal transmission path, and flip chip bonding techniques has been widely used in chip package field at present.
Early stage flip chip packaging body by a slice chip package with cover in crystal, even if volume is little again, and can only and be placed on circuit board, be limited to board area, more cover crystal so cannot place.Afterwards, in order to reduce the spatial placement of circuit board, onesize circuit board being arranged and more covers crystal.What propose current Stackable covers crystal, but this structural disadvantages is a lot, and be unfavorable for heat radiation, consumable material does not also reduce, and cost is also very high.
And in society now, if product is wanted to win the market, just must constantly follow after progress, not only technological progress, also will reduce price, energy savings.
Summary of the invention
The object of this invention is to provide a kind of cost low, take the Double-wafer crystal encryption structure that circuit board space is little, thermal diffusivity is good.
For achieving the above object, the invention provides a kind of Double-wafer crystal encryption structure, comprise: substrate, chip, fill heat-conducting glue, fin.
Described substrate is insulator, has central baffle, forms two chip pocket, has a plurality ofly to merge with chip conductive projection the lead end be connected.
Described chip by conductive projection merge be connected with slot inner lead end, described chip with contact bottom substrate center dividing plate with stablize.
Described substrate and slot that its central baffle is formed are convenient to inject filler, inject and fill heat-conducting glue to reduce the stress of chip and substrate junction, avoid chip and substrate junction conductive projection to be damaged, strengthen the heat dispersion of chip.
Described fin and substrate top and central baffle top bond with elargol, and mutual buckle stabilisation system, with protect IC, strengthens heat radiation.
Adopt Double-wafer crystal encryption structure of the present invention, compared with covering crystal with stack, achieve chip autoregistration, prevent chip chamber from influencing each other, enhance the reliability of system.Compared with single-chip composite packing structure, achieve twin lamella integrative packaging, integrated level is high, and reduce chip package area, energy savings, reduces costs.
Accompanying drawing explanation
Fig. 1 is Double-wafer crystal encryption structure profile in the present invention.
In above accompanying drawing:
1, substrate;
2, chip;
3, fin;
4, conductive projection;
5, lead end;
6, central baffle;
7, substrate top;
8, filler heat-conducting glue;
9, elargol.
Embodiment
For enabling above-mentioned feature of the present invention, object and advantage more become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Because the present invention focuses on interpretation principle, therefore, chart not in scale.
Embodiment: a kind of twin lamella chip package encapsulating structure.
A kind of Double-wafer crystal encryption structure, with reference to shown in accompanying drawing 1: comprise 1. substrate 2. chip 3. fin 4. conductive projection 5. lead end 6. central baffle 7. substrate top 8. filler heat-conducting glue 9. elargol.It is characterized in that: substrate 1 is isolation material; there is central baffle 6; chip 2 is placed in the slot that central baffle 6 is formed with substrate top 7; by being electrically connected after recess lead end 5 melting of 4 conductive projections and slot bottom ramp; heat-conducting glue 8 injects in slot afterwards, and covering chip is with protect IC and pass to heat.Fin 3 is bondd by elargol 9 and central baffle 6 and substrate top 7, forms Double-wafer crystal encryption structure.
Above-described embodiment, only for make a detailed explanation content of the present invention, its object is to allow those skilled in the art are afamiliar with particular content of the present invention and implementing according to this.Allly do not depart from any equivalence change that Spirit Essence of the present invention does or modify, all should belong within protection scope of the present invention.
Claims (9)
1. a Double-wafer crystal encryption structure comprises: substrate, chip, filler, fin; It is characterized in that, described substrate has central baffle, and has two symmetrical chip pocket, and described substrate chip slot has certain slope, a plurality of hemispherical depression of docking with conductive projection bottom described slot.
2. substrate as claimed in claim 1, is characterized in that, vertical with tool acclive slot face bottom described substrate center dividing plate.
3. chip as claimed in claim 1, it is characterized in that, described chip active surface has a plurality of cylindrical conductive projection, and projection top has hemispherical projections.
4. Double-wafer crystal encryption structure as claimed in claim 1, it is characterized in that, described fin and substrate interlock.
5. substrate and fin as claimed in claim 1, it is characterized in that, fin propped by described substrate center dividing plate.
6. substrate and fin as claimed in claim 1, it is characterized in that, be a filler in the space that described substrate center and fin are formed respectively.
7. filler as claimed in claim 6, it is characterized in that, described filler is a heat-conducting glue.
8. fin as claimed in claim 6, it is characterized in that, described fin is metal.
9. substrate and fin as described in claims 5,6, it is characterized in that, described substrate and fin are bondd by elargol.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310650385.1A CN104701305A (en) | 2013-12-06 | 2013-12-06 | Double-chip flip chip structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310650385.1A CN104701305A (en) | 2013-12-06 | 2013-12-06 | Double-chip flip chip structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104701305A true CN104701305A (en) | 2015-06-10 |
Family
ID=53348260
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310650385.1A Pending CN104701305A (en) | 2013-12-06 | 2013-12-06 | Double-chip flip chip structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104701305A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108831838A (en) * | 2018-06-26 | 2018-11-16 | 张军 | A kind of IPM encapsulating structure and preparation method thereof |
| CN108847409A (en) * | 2018-06-25 | 2018-11-20 | 张军 | A kind of intelligent power module and preparation method thereof |
| CN108878383A (en) * | 2018-06-26 | 2018-11-23 | 张军 | A kind of High Performance IP M package module and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1197616A (en) * | 1997-09-25 | 1999-04-09 | Hitachi Ltd | Multi-chip module and manufacture thereof |
| KR20040090660A (en) * | 2003-04-18 | 2004-10-26 | 한국전자통신연구원 | Method of flip chip bonding utilizing slanted groove for optical passive alignment and optical module |
| CN202013882U (en) * | 2011-02-15 | 2011-10-19 | 晶诚（郑州）科技有限公司 | Packaging structure capable of enhancing LED brightness |
| CN103281858A (en) * | 2013-05-28 | 2013-09-04 | 三星半导体(中国)研究开发有限公司 | Printed circuit board and manufacturing method thereof, and flip-chip packaging member and manufacturing method thereof |
-
2013
- 2013-12-06 CN CN201310650385.1A patent/CN104701305A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1197616A (en) * | 1997-09-25 | 1999-04-09 | Hitachi Ltd | Multi-chip module and manufacture thereof |
| KR20040090660A (en) * | 2003-04-18 | 2004-10-26 | 한국전자통신연구원 | Method of flip chip bonding utilizing slanted groove for optical passive alignment and optical module |
| CN202013882U (en) * | 2011-02-15 | 2011-10-19 | 晶诚（郑州）科技有限公司 | Packaging structure capable of enhancing LED brightness |
| CN103281858A (en) * | 2013-05-28 | 2013-09-04 | 三星半导体(中国)研究开发有限公司 | Printed circuit board and manufacturing method thereof, and flip-chip packaging member and manufacturing method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108847409A (en) * | 2018-06-25 | 2018-11-20 | 张军 | A kind of intelligent power module and preparation method thereof |
| CN108831838A (en) * | 2018-06-26 | 2018-11-16 | 张军 | A kind of IPM encapsulating structure and preparation method thereof |
| CN108878383A (en) * | 2018-06-26 | 2018-11-23 | 张军 | A kind of High Performance IP M package module and preparation method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150610 |