CN104682953A - Error calibration method and device of tuning circuit - Google Patents
Error calibration method and device of tuning circuit Download PDFInfo
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- CN104682953A CN104682953A CN201510083243.0A CN201510083243A CN104682953A CN 104682953 A CN104682953 A CN 104682953A CN 201510083243 A CN201510083243 A CN 201510083243A CN 104682953 A CN104682953 A CN 104682953A
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Abstract
The embodiment of the invention provides an error calibration method and a device of a tuning circuit. The method comprises the steps of acquiring testing tuning frequency, tuning voltage and a preset sensitivity coefficient of the tuning circuit, obtaining a resistance error value via the testing tuning frequency, the tuning voltage and the preset sensitivity coefficient, obtaining corrected tuning frequency via the resistance error value, the tuning voltage and the preset sensitivity coefficient, and configuring the tuning circuit via the corrected tuning frequency. The method is used for simplifying a calibration flow of the tuning circuit, reducing artificial participation and getting rid of a method of compensating the circuit by changing hardware resistance; the error amount of the tuning circuit is compensated by changing a software computation parameter; the cost is lowered; and the method has higher operability and expandability.
Description
Technical field
The present invention relates to mobile communication technology field, particularly relate to a kind of error calibrating method of tuning circuit and a kind of device that calibrates for error of tuning circuit.
Background technology
For analog receiver, frequently the heart that source is it is combined, which determine the spectral purity of analog receiver to such an extent as to determine the error vector magnitude (EVM of analog receiver, Error Vector Magnitude), neighboring trace leakage power ratio (ACPR, Adjacent Channel Power Ratio), the indexs such as the error rate (BER, Bit Error Rate).
Frequently the spectral purity combining source is weighed by phase noise and spuious index usually.Phase-locked loop (PLL, Phase Locked Loop) is one of main technology realizing high again and again comprehensive source, and along with the frequency of application is more and more higher, bandwidth is more and more wider, and the phase noise specifications that the very large challenge brought has been exactly is more and more difficult to be realized.General, the phase noise near-end of pll output signal depends on reference and phase-locked loop chip itself, and far-end depends on voltage controlled oscillator (VCO, voltage controlled oscillator).But, because the VCO phase noise specifications in broadband is all poor, be difficult to meet high-end application requirement.
Summary of the invention
Embodiment of the present invention technical problem to be solved is to provide a kind of error calibrating method of tuning circuit, in order to simplify the calibration flow process of tuning circuit, reduce artificial participation, break away from and change the method that hardware resistance removes compensating circuit, by changing software calculating parameter thus compensating the tuning circuit margin of error, not only reduce cost, and there is stronger operability and extensibility.
Accordingly, the embodiment of the present invention additionally provides a kind of device that calibrates for error of tuning circuit, in order to ensure the implementation and application of said method.
In order to solve the problem, the invention discloses a kind of error calibrating method of tuning circuit, comprising:
Obtain the test tuned frequency of tuning circuit, tuning voltage and preset sensitivity coefficient;
Described test tuned frequency, tuning voltage and preset sensitivity coefficient is adopted to obtain resistance error value;
Adopt described resistance error value, tuning voltage and preset sensitivity coefficient to obtain and revise tuned frequency;
Described correction tuned frequency is adopted to configure described tuning circuit.
Preferably, the described step adopting test tuned frequency, tuning voltage and preset sensitivity coefficient to obtain resistance error value comprises:
Default frequency place in the band limits of specifying carries out test and obtains test tuned frequency;
Obtain the tuning voltage at described default frequency place;
Adopt described test tuned frequency, tuning voltage and preset sensitivity coefficient, according to the formulae discovery resistance value preset;
Adopt described resistance value to carry out mean value computation and obtain resistance error value.
Preferably, after described employing resistance error value, tuning voltage and preset sensitivity coefficient obtain the step optimizing tuned frequency, also comprise:
Preset compensation tuned frequency is added and revises tuned frequency, obtain new correction tuned frequency.
Preferably, the step of described employing resistance error value, tuning voltage and preset sensitivity coefficient acquisition correction tuned frequency comprises:
By described resistance error value, tuning voltage and preset sensitivity coefficient, according to the formulae discovery correction tuned frequency preset.
Preferably, described tuning circuit is the main tuning circuit of YIG-tuned oscillator YTO.
The embodiment of the present invention additionally provides a kind of device that calibrates for error of tuning circuit, comprising:
Tuning numerical value acquisition module, for obtaining the test tuned frequency of tuning circuit, tuning voltage and preset sensitivity coefficient;
Resistance error value obtains module, obtains resistance error value for adopting described test tuned frequency, tuning voltage and preset sensitivity coefficient;
Revise tuned frequency and obtain module, obtain for adopting described resistance error value, tuning voltage and preset sensitivity coefficient and revise tuned frequency;
Tuning circuit configuration module, configures described tuning circuit for adopting described correction tuned frequency.
Preferably, described resistance error value acquisition module comprises:
Tuned frequency test submodule, carries out test for the default frequency place in the band limits of specifying and obtains test tuned frequency;
Tuning voltage obtains submodule, for obtaining the tuning voltage at described default frequency place;
Resistance value calculating sub module, for adopting described test tuned frequency, tuning voltage and preset sensitivity coefficient, according to the formulae discovery resistance value preset;
Resistance error value obtains submodule, carries out mean value computation obtain resistance error value for adopting described resistance value.
Preferably, described device also comprises:
Tuned frequency compensating module, revising tuned frequency for being added by preset compensation tuned frequency, obtaining new correction tuned frequency.
Preferably, described correction tuned frequency acquisition module comprises:
Revise tuned frequency calculating sub module, for by described resistance error value, tuning voltage and preset sensitivity coefficient, according to the formulae discovery correction tuned frequency preset.
Preferably, described tuning circuit is the main tuning circuit of YIG-tuned oscillator YTO.
Compared with prior art, the embodiment of the present invention comprises following advantage:
According to the error law of tuning circuit in the embodiment of the present invention, ignore the error of each part in tuning circuit, replace all errors with independent resistance error value and compensated.Be specially the test tuned frequency obtained according to reality test, and tuning voltage and preset sensitivity coefficient obtain resistance error value, then adopt this resistance error value to calculate and revise tuned frequency.The embodiment of the present invention simplifies at present for the calibration flow process of tuning circuit, the participation that no longer too much needs are artificial, the mode of software automatic test can be adopted to carry out test analysis and to obtain resistance error value, compared to the way needing the hardware resistance changed in tuning circuit, the embodiment of the present invention can adopt resistance error value go to calculate correction tuned frequency as modifying factor and do not change actual hardware resistance, not only reduce cost, and there is stronger operability and extensibility.
Accompanying drawing explanation
Fig. 1 be a kind of there is the main tuning circuit of calibration function realize block diagram;
Fig. 2 is the schematic diagram that a kind of main tuning circuit error eliminates implementation;
Fig. 3 is a kind of test data schematic diagram of YIG tuning circuit open loop frequency-voltage tester table;
Fig. 4 is the flow chart of steps of the error calibrating method embodiment of a kind of tuning circuit of the present invention;
Fig. 5 is the schematic diagram 1 of a kind of YIG tuning circuit open-loop compensation test of the present invention;
Fig. 6 is the schematic diagram 2 of a kind of YIG tuning circuit open-loop compensation test of the present invention;
Fig. 7 is the structured flowchart of the device embodiment that calibrates for error of a kind of tuning circuit of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
All poor in order to solve traditional VCO phase noise specifications, be difficult to meet the problem that high-end application requires, yttrium iron garnet (YIG, yttrium iron garnet) tuned oscillator (YTO, YIG-tuned oscillator) arises at the historic moment.
It is tuning that YTO utilizes the size changing resonance bead bias magnetic field to realize in wide range, and it has very high Q value (Q value is also the quality factor of inductance, is the major parameter of measurement inductance component simultaneously.When referring to that inductor works under the alternating voltage of a certain frequency, the ratio of the induction reactance presented loss resistance equivalent with it.Q value is higher, and loss is less, and efficiency is higher), good phase noise and spurious performance can be realized.YIG tuning circuit has good index, but its Application comparison is complicated.Be different from the voltage-controlled voltage-controlled mode of list of traditional VCO, YIG tuning circuit by Current Control, and is divided into main tuning electric current and auxiliary tuning current.Only have by after difference correct configuration main tuning electric current and auxiliary tuning current, the locking of loop could be realized.
General, the slope of the YIG tuning circuit main tuning of 4 ~ 8GHz is about 18MHz/mA, auxiliary tuning slope is about 300KHz/mA, can find that YIG tuning circuit is very responsive for main tuning electric current by slope value, and the change of main tuning electric current 1mA can cause frequency change 18MHz.General auxiliary tuning lock-in range only has positive and negative tens megahertzes, and therefore the several milliampere of main tuning curent change just may cause phase-locked loop to lock.Therefore the required precision for main tuning circuit is very strict, needs output current value very accurately (differing <1mA with theoretical value).Main tuning circuit implementing scheme is generally by a high-precision DAC (Digital-to-Analog Converter, digital analog converter) export high-precision voltage, then become electric current to export to YIG tuning circuit the voltage transitions that DAC exports by amplifier with triode.Wherein, main tuning circuit can a built-in calibration circuit for calibrating the error of whole circuit.It realizes circuit block diagram specifically can with reference to Fig. 1.
In specific implementation, have a lot of part can introduce error, such as resistance R1 in main tuning circuit, although two resistance are all R1, resistance is the same.But can not there are two identical resistance of resistance in reality, the error therefore between resistance can cause the change of the follower output voltage of the first order.R3 for another example, the realization of electric current relies on voltage to obtain divided by resistance usually, and R3 is exactly the high-power resistor that voltage transitions becomes electric current.The accuracy of this resistance value just directly has influence on the accuracy of output current.Also have amplifier open-loop gain in circuit, the Leakage Current of triode, all can have influence on final output current accuracy.And from engineering viewpoint, these errors are all normal and inevitably.Fortunately, these errors discussed herein are all also fixing, so them can be gone to eliminate by a calibration steps.Calibration circuit role in Here it is Fig. 1.
With reference to Fig. 2, be depicted as tradition at present and eliminate the structural representation of a kind of implementation method of error, traditional implementation method specifically:
1: arranging control voltage is minimum voltage (such as 0V), regulate the starting point of the resistance calibration YIG tuning circuit of slide rheostat R1, such as 4GHz, obtains the resistance sizes that starting point is corresponding.
2: arranging control voltage is maximum voltage (such as 10V), regulate the terminal of the resistance calibration YIG tuning circuit of slide rheostat R2, such as 8GHz, obtains the resistance sizes that terminal is corresponding.
3: use fixed resistance to replace slide rheostat.Due to the resistance of general resistance usually cannot be obtained, the mode of multiple resistant series or parallel connection is therefore usually used to realize the resistance of slide rheostat.
4: repetition measurement one time.Last all frequency changes between 4GHz and 8GHz, think linear.Theory calculate is relied on to complete configuration.
Above-mentioned traditional implementation method goes to obtain circuit error by slide rheostat calibration minimum frequency and highest frequency, and then substitute slip resistance with fixed resistance, the frequency finally between minimum frequency and peak frequency is defaulted as linear condition and is configured.
Existing YIG tuning circuit calibration arrangements mode, it thinking is the error by calibrating initial frequency and cut-off frequency, realize the correct configuration to whole frequency range, concrete calibrating mode employing is slide rheostat calibration, re-uses the mode that fixed resistance is replaced simultaneously.Due to the incompleteness of fixed resistance resistance, therefore need by multiple resistance and connect to make up.Following three shortcomings can be there are in such way:
1: linear problem, this calibration arrangements strategy thinks at initial frequency and the frequency stopped between frequency it is all the relation of linear change.Therefore just by calibrating two points to realize the configuration of whole frequency range.But measured result shows, even if be considered to the YIG tuning circuit of the good 4 ~ 8GHz of linear degree, its linear degree neither be desirable especially.Specifically can with reference to the test data schematic diagram of the YIG tuning circuit open loop frequency-voltage tester table shown in Fig. 3.
The open-loop test that the test result of the table shown in Fig. 3 is done based on 3 YIG MLTM-50308, measured result shows, and linearity error is maximum reaches about 10MHz.Due to the restriction of measuring instrument accuracy of instrument and variations in temperature, cannot confirm that this error information must be accurately.But at least from current data rule linearity difference problem be exist.
2: utilize slide rheostat to calibrate, then use the mode of fixed resistance collocation to realize hardware circuit, this method is also inconvenient, after first needing to finish calibration on board, also needs to change hardware, changes resistance value.Artificial reforming machine pasting board card this be unfavorable for the consistency of performance of Control card.The resistance that simultaneously may finally mix up due to slide rheostat is not general, therefore needs to use fixed resistance collocation to realize.If slide rheostat characterizes the resistance of 1.711Kohm, and reality does not exist the resistance of this resistance, the resistor coupled in parallel of a 1.8Kohm resistance and a 34.7Kohm is so just needed to realize.Sometimes also need to add a series resistance.General, a series resistance can be used to add, and two parallel resistances are to represent the value of slide rheostat.From also seeing here, operation is pretty troublesome like this.Hardware not only to prepare the resistance of different resistance, and also need the calibration testing that tries again after replacement.
3: owing to employing more resistance to carry out the calibration of precision, the resistance so used itself also can introduce error.This error is divided into two aspects, a trueness error, and one is temperature stabilization error.Ensure the accurate of frequency calibration, so just need the calibrating resistance resistance ensureing to substitute slide rheostat to stablize.If for YIG MLTM-50308, produce the signal of 4G-8GHz, triode so in main tuning circuit can bear the power consumption of the highest 1.6W, precision resister can bear the power consumption of maximum 2.1W, YIG chip can bear the power consumption of maximum 1.8W, and when YIG tuning circuit frequency change, can there is certain change in power consumption.This just means that the temperature of the main tuning circuit of whole YIG tuning circuit can exist certain fluctuating.Temperature can affect the resistance of resistance, and we calibrate the higher temperature stability of the substitutional resistance demand fulfillment of YIG tuning circuit in other words.And the cost of high stability resistance is very high.From this angle, this method is also uneconomical.
Certain existing YIG tuning circuit calibration arrangements strategy also has its advantage, uses little calibration point to simulate the state of whole frequency range exactly, needs to sacrifice hardware resource and tolerate that certain error is for cost is to decrease the workload of calibration.
Inventor herein is based on above-mentioned situation just, the strategy that calibrates for error of a kind of tuning circuit that the embodiment of the present invention proposes, for completing in independent frequency configuration with frequency sweep layoutprocedure, ignore the error of each part in YIG tuning circuit, replace all errors with independent resistance error value and calibration arrangements is carried out to YIG tuning circuit, the final stability ensureing closed loop phase lock.
With reference to Fig. 4, show the flow chart of steps of the error calibrating method embodiment of a kind of tuning circuit of the present invention, specifically can comprise the steps:
Step 101, obtains the test tuned frequency of tuning circuit, tuning voltage and preset sensitivity coefficient;
Step 102, adopts described test tuned frequency, tuning voltage and preset sensitivity coefficient to obtain resistance error value;
In one preferred embodiment of the invention, described step 102 can comprise following sub-step:
Sub-step S11, the default frequency place in the band limits of specifying carries out test and obtains test tuned frequency;
Sub-step S12, obtains the tuning voltage at described default frequency place;
Sub-step S13, adopts described test tuned frequency, tuning voltage and preset sensitivity coefficient, according to the formulae discovery resistance value preset;
Sub-step S14, adopts described resistance value to carry out mean value computation and obtains resistance error value.
In embodiments of the present invention, the error law for tuning circuit carries out testing and analysis.The voltage-frequency characteristic of tuning circuit is obtained by actual measurement, and the voltage-frequency characteristic of the tuning circuit of contrast theory calculate, analyze and show that tuning circuit error can become greatly and gradually large trend, the consistency of this trend and theory analysis simultaneously along with main tuning voltage becomes.The embodiment of the present invention, according to the error law of tuning circuit, ignores the error of each part in tuning circuit, replaces all errors compensated with independent resistance error value, needs the calculating carrying out resistance error value thus.
In order to make those skilled in the art the present invention may be better understood embodiment, below for YIG tuning circuit, concrete example is adopted to be described for the process obtaining resistance error value.
In specific implementation, perfect along with board software automatic test function, the work of artificial calibration slowly all by instrument automatically test replace, this also brings workload and temporally greatly to reduce.The main thought of the embodiment of the present invention is the mode adopting software automatic test, by test voltage-frequency corresponding relation, analyzes its error law.Calculate error compensation to fall eventually through software merit rating.
First start with from the output frequency computing formula of YIG main tuning circuit:
Wherein, Vtune is the magnitude of voltage of main tuning circuit, and scope is from 0V-5V, and frequency is higher, and voltage is larger.R value is high steady resistance (namely voltage the turns current resistor) value of high accuracy, and nominal value is 10 Europe.K value is the main tuning sensitivity of YIG, and nominal value is 18MHz/V.
These three parameters all have error.The intrinsic error of Vtune comes from any one device on main tuning circuit, (remarks: do not inquire into the dynamic error because temperature causes here), R value comes from self error of precision resister, general can service precision be the resistance of 0.1%, and that is resistance value error is 0.01 Europe.The error of K value comes from the of YIG tuning circuit own.
Three kinds of errors all can be measured in practice, then compensate one by one.But the realizability of this method is very poor, because test instrumentation also all has precision, the precision of test instrumentation also can bring error, if test compensation respectively, so test three times or more times, the error that test instrumentation causes can be a cumulative relation.
Can be seen by above-mentioned formula, the error of K value and R can be thought relatively-stationary, can not change along with the change of output frequency.Vtune can become large along with the rising of frequency.Also just mean, K value change 1MHz/V, the frequency change that high frequency causes is large, and the frequency change that low frequency causes is little.R value change 0.1 Europe, be equally also high frequency can change larger, it is less that low frequency can change.Test with the YIG under this rule divided ring condition, concrete test data can with reference to Fig. 5.
In Figure 5, E is classified as the frequency values calculated according to theoretical value, and B is classified as the actual frequency values tested out, and F is classified as both error, can find, the error of F row is the processes increased progressively gradually.Error size reaches 178.48MHz.This error and resistance value bring the rule of error consistent, and this error just can reduce by the size therefore by changing resistance value.Suppose that all errors are all on resistance, can utilize above-mentioned formula, according to the test tuned frequency of reality test, and relevant tuning factor, the anti-resistance value releasing each frequency, then averages for this resistance data, can obtain resistance error value.
Such as, according to the data in Fig. 5, resistance value can be optimized for 9.758 Europe according to the resistance error value calculated.Calculate tuned frequency according to the resistance value after optimizing, such error information just there occurs change, and concrete test data can with reference to Fig. 6.Can find from figure, test and theory error scope reduce greatly.
In one preferred embodiment of the invention, after described step 103, can also comprise the steps:
Preset compensation tuned frequency is added and revises tuned frequency, obtain new correction tuned frequency.
Can find from the test data of Fig. 6, test and theory error scope have narrowed down to 12.6MHz, and if use the compensation tuned frequency of-66MHz to go to compensate, the worst error of so each Frequency point is greatly about about 7MHz, and this value is still much smaller than lock-in range.
That is, as long as be fixed compensation to the compensation tuned frequency that theory calculate frequency is-66MHz, and in computational process, use the correction resistance value in 9.758 Europe, theoretical configuration frequency and theory calculate frequency maximum disparity just can be allowed to control at about 7MHz.Meet the requirement of closed loop locking.
It should be noted that, the actual value of resistance is not substantially 9.758 Europe, therefore thinks that resistance value is here actually a modifying factor.And the numerical value testing the modifying factor of acquisition in different tuning circuits is different.
The embodiment of the present invention can calculate tuned frequency value by software by revised theory, and by modifying factor revised theory resistance value, then configure the tuned frequency of YIG tuning circuit, can minimum error be reached.
In a kind of preferred exemplary of the present invention, calibration can be gone once every 0.1V, such as, in the frequency range of 4G ~ 8G, do a test every about 400MHz frequency, do altogether 20 times and tested whole calibration process, so also greatly can improve the linearity between calibration point.
In addition, if YIG tuning circuit uses frequency range very wide, also can improve calibration number of times and improve linearity level further, extensibility is stronger.And due to software automated testing, even if calibration number of times increases, also obvious raising can not be caused to workload and time.
Step 103, adopts described resistance error value, tuning voltage and preset sensitivity coefficient to obtain and revises tuned frequency;
In one preferred embodiment of the invention, described step 103 can comprise following sub-step:
Sub-step S21, by described resistance error value, tuning voltage and preset sensitivity coefficient, according to the formulae discovery correction tuned frequency preset.
After getting resistance error value, can calculate according to the output frequency of YIG main tuning circuit and revise tuned frequency, the embodiment of the present invention is according to the error law of YIG tuning circuit, thus by revised resistance error value, by the error correction of wide-band in hardware tolerance interval, change simple resistance value into modifying factor, can minimum error be obtained.
Step 104, adopts described correction tuned frequency to configure described tuning circuit.
In sum: the principle of the embodiment of the present invention is, consider and cause the factor of error may have a lot, according to the error law of YIG tuning circuit, can suppose that all errors are all because resistance precision causes, by compensating resistance precision, just can the error of compensating frequency.And this compensation is not by change hardware resistance, only change our calculating resistance value size when configuring main tuning circuit, tuned frequency computational accuracy is improved on the basis can reducing cost.Simultaneously owing to adopting software automated testing, obvious raising can not be caused to workload and time.
At least tool that calibrates for error adopting the embodiment of the present invention to carry out YIG tuning circuit has the following advantages:
1: simplify the current calibration flow process for YIG tuning circuit, the participation that no longer too much needs are artificial, method by software automatic test tests out the margin of error of frequency, ignore the error of each part in YIG tuning circuit, replace with independent resistance error value that all errors are compensated, then resistance error value can be found by analysis.
2: broken away from and changed the method that hardware resistance removes to compensate tuning circuit, the embodiment of the present invention goes compensating error amount by changing software calculating parameter, on cost and in operability, all improves a lot.
3: effectively reduce the problem may brought because device linearity degree is poor, and be with good expansibility, improve pendulous frequency and can improve linearity index, and obvious raising can not be caused to workload and time due to software automated testing, reduce actual cost.
It should be noted that, for embodiment of the method, in order to simple description, therefore it is all expressed as a series of combination of actions, but those skilled in the art should know, the embodiment of the present invention is not by the restriction of described sequence of movement, because according to the embodiment of the present invention, some step can adopt other orders or carry out simultaneously.Secondly, those skilled in the art also should know, the embodiment described in specification all belongs to preferred embodiment, and involved action might not be that the embodiment of the present invention is necessary.
With reference to Fig. 7, show the structured flowchart of the device embodiment that calibrates for error of a kind of tuning circuit of the present invention, specifically can comprise as lower module:
Tuning numerical value acquisition module 201, for obtaining the test tuned frequency of tuning circuit, tuning voltage and preset sensitivity coefficient;
Resistance error value obtains module 202, obtains resistance error value for adopting described test tuned frequency, tuning voltage and preset sensitivity coefficient;
In one preferred embodiment of the invention, described resistance error value acquisition module 202 can comprise following submodule:
Tuned frequency test submodule, carries out test for the default frequency place in the band limits of specifying and obtains test tuned frequency;
Tuning voltage obtains submodule, for obtaining the tuning voltage at described default frequency place;
Resistance value calculating sub module, for adopting described test tuned frequency, tuning voltage and preset sensitivity coefficient, according to the formulae discovery resistance value preset;
Resistance error value obtains submodule, carries out mean value computation obtain resistance error value for adopting described resistance value.
Revise tuned frequency and obtain module 203, obtain for adopting described resistance error value, tuning voltage and preset sensitivity coefficient and revise tuned frequency;
In one preferred embodiment of the invention, described correction tuned frequency acquisition module 203 can comprise following submodule:
Revise tuned frequency calculating sub module, for by described resistance error value, tuning voltage and preset sensitivity coefficient, according to the formulae discovery correction tuned frequency preset.
Tuning circuit configuration module 204, configures described tuning circuit for adopting described correction tuned frequency.
In one preferred embodiment of the invention, described device can also comprise as lower module:
Tuned frequency compensating module, revising tuned frequency for being added by preset compensation tuned frequency, obtaining new correction tuned frequency.
In one preferred embodiment of the invention, described tuning circuit can be the main tuning circuit of YIG-tuned oscillator YTO.
For device embodiment, due to itself and embodiment of the method basic simlarity, so description is fairly simple, relevant part illustrates see the part of embodiment of the method.
Each embodiment in this specification all adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar part mutually see.
Those skilled in the art should understand, the embodiment of the embodiment of the present invention can be provided as method, device or computer program.Therefore, the embodiment of the present invention can adopt the form of complete hardware embodiment, completely software implementation or the embodiment in conjunction with software and hardware aspect.And the embodiment of the present invention can adopt in one or more form wherein including the upper computer program implemented of computer-usable storage medium (including but not limited to magnetic disc store, CD-ROM, optical memory etc.) of computer usable program code.
The embodiment of the present invention describes with reference to according to the flow chart of the method for the embodiment of the present invention, terminal equipment (system) and computer program and/or block diagram.Should understand can by the combination of the flow process in each flow process in computer program instructions realization flow figure and/or block diagram and/or square frame and flow chart and/or block diagram and/or square frame.These computer program instructions can being provided to the processor of all-purpose computer, special-purpose computer, Embedded Processor or other programmable data processing terminal equipment to produce a machine, making the instruction performed by the processor of computer or other programmable data processing terminal equipment produce device for realizing the function of specifying in flow chart flow process or multiple flow process and/or block diagram square frame or multiple square frame.
These computer program instructions also can be stored in can in the computer-readable memory that works in a specific way of vectoring computer or other programmable data processing terminal equipment, the instruction making to be stored in this computer-readable memory produces the manufacture comprising command device, and this command device realizes the function of specifying in flow chart flow process or multiple flow process and/or block diagram square frame or multiple square frame.
These computer program instructions also can be loaded on computer or other programmable data processing terminal equipment, make to perform sequence of operations step to produce computer implemented process on computer or other programmable terminal equipment, thus the instruction performed on computer or other programmable terminal equipment is provided for the step realizing the function of specifying in flow chart flow process or multiple flow process and/or block diagram square frame or multiple square frame.
Although described the preferred embodiment of the embodiment of the present invention, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of embodiment of the present invention scope.
Finally, also it should be noted that, in this article, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operating space, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or terminal equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or terminal equipment.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the terminal equipment comprising described key element and also there is other identical element.
Above to the error calibrating method of a kind of tuning circuit provided by the present invention and a kind of device that calibrates for error of tuning circuit, be described in detail, apply specific case herein to set forth principle of the present invention and execution mode, the explanation of above embodiment just understands method of the present invention and core concept thereof for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (10)
1. an error calibrating method for tuning circuit, is characterized in that, comprising:
Obtain the test tuned frequency of tuning circuit, tuning voltage and preset sensitivity coefficient;
Described test tuned frequency, tuning voltage and preset sensitivity coefficient is adopted to obtain resistance error value;
Adopt described resistance error value, tuning voltage and preset sensitivity coefficient to obtain and revise tuned frequency;
Described correction tuned frequency is adopted to configure described tuning circuit.
2. method according to claim 1, is characterized in that, the described step adopting test tuned frequency, tuning voltage and preset sensitivity coefficient to obtain resistance error value comprises:
Default frequency place in the band limits of specifying carries out test and obtains test tuned frequency;
Obtain the tuning voltage at described default frequency place;
Adopt described test tuned frequency, tuning voltage and preset sensitivity coefficient, according to the formulae discovery resistance value preset;
Adopt described resistance value to carry out mean value computation and obtain resistance error value.
3. method according to claim 1, is characterized in that, after described employing resistance error value, tuning voltage and preset sensitivity coefficient obtain the step optimizing tuned frequency, also comprises:
Preset compensation tuned frequency is added and revises tuned frequency, obtain new correction tuned frequency.
4. the method according to claim 1 or 2 or 3, is characterized in that, described employing resistance error value, tuning voltage and preset sensitivity coefficient obtain the step revising tuned frequency and comprise:
By described resistance error value, tuning voltage and preset sensitivity coefficient, according to the formulae discovery correction tuned frequency preset.
5. method according to claim 1, is characterized in that, described tuning circuit is the main tuning circuit of YIG-tuned oscillator YTO.
6. the device that calibrates for error of tuning circuit, is characterized in that, comprising:
Tuning numerical value acquisition module, for obtaining the test tuned frequency of tuning circuit, tuning voltage and preset sensitivity coefficient;
Resistance error value obtains module, obtains resistance error value for adopting described test tuned frequency, tuning voltage and preset sensitivity coefficient;
Revise tuned frequency and obtain module, obtain for adopting described resistance error value, tuning voltage and preset sensitivity coefficient and revise tuned frequency;
Tuning circuit configuration module, configures described tuning circuit for adopting described correction tuned frequency.
7. device according to claim 6, is characterized in that, described resistance error value obtains module and comprises:
Tuned frequency test submodule, carries out test for the default frequency place in the band limits of specifying and obtains test tuned frequency;
Tuning voltage obtains submodule, for obtaining the tuning voltage at described default frequency place;
Resistance value calculating sub module, for adopting described test tuned frequency, tuning voltage and preset sensitivity coefficient, according to the formulae discovery resistance value preset;
Resistance error value obtains submodule, carries out mean value computation obtain resistance error value for adopting described resistance value.
8. device according to claim 6, is characterized in that, also comprises:
Tuned frequency compensating module, revising tuned frequency for being added by preset compensation tuned frequency, obtaining new correction tuned frequency.
9. the device according to claim 6 or 7 or 8, is characterized in that, described correction tuned frequency obtains module and comprises:
Revise tuned frequency calculating sub module, for by described resistance error value, tuning voltage and preset sensitivity coefficient, according to the formulae discovery correction tuned frequency preset.
10. device according to claim 6, is characterized in that, described tuning circuit is the main tuning circuit of YIG-tuned oscillator YTO.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510083243.0A CN104682953B (en) | 2015-02-15 | 2015-02-15 | A kind of error calibrating method and device of tuning circuit |
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| CN113203520A (en) * | 2021-05-27 | 2021-08-03 | 北京京城清达电子设备有限公司 | Pressure sensor debugging system and method |
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| CN104682953B (en) | 2018-08-03 |
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