CN104681481A - Semiconductor device and method for manufacturing semiconductor device - Google Patents
Semiconductor device and method for manufacturing semiconductor device Download PDFInfo
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- CN104681481A CN104681481A CN201310637611.2A CN201310637611A CN104681481A CN 104681481 A CN104681481 A CN 104681481A CN 201310637611 A CN201310637611 A CN 201310637611A CN 104681481 A CN104681481 A CN 104681481A
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Abstract
The invention discloses a semiconductor device and a method for manufacturing the semiconductor device. According to the method which is provided by the invention and is used for carrying out back etching on an isolation material layer in an STI area, the cross section of the top surface of an STI (Shallow Trench Isolation) structure which is formed according to the method is of an inverted trapezoidal groove structure, and thus a formed NVM (Nonvolatile Memory) has a higher grid coupling ratio; polycrystalline silicon of a floating gate is protected by the side wall of an STI when the back etching is carried out on the isolation material layer in the STI area, and thus the consumption of the floating gate is avoided; a suitable shallow trench structure is formed in the NVM, and thus the NVM is enabled to have a higher erasing speed; appropriate distance between the edge of the STI and a stacked grid is beneficial for enhancing the reliability of a flash memory and is beneficial for increasing the cycle performance of the semiconductor device.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly relate to a kind of manufacture method of the isolation structure for NOR Flash.
Background technology
Memory is for storing a large amount of digital information, show according to investigations recently, worldwide, memory chip approximately account for 30% of semiconductor transaction, for many years, the progress of technology and the market demand expedite the emergence of more and more highdensity all kinds memory, as RAM (random asccess memory), SRAM(static random access memory), DRAM (dynamic random access memory) and FRAM (ferroelectric memory) etc.
Random asccess memory, such as DRAM and SRAM in use deposits the problem storing loss of data after a power failure.In order to overcome this problem, people have designed and have developed multiple nonvolatile memory.Recently, based on the flash memory of floating grid concept, due to it, there is little cell size and good service behaviour has become the most general nonvolatile memory (NVM, Nonvolatile memories).
Along with semiconductor integrated circuit industrial technology maturation day by day, developing rapidly of ultra-large integrated circuit, there is the component density that more high-performance and more powerful integrated circuit requirement are larger, and all parts, between element or the size of each element self, size and space also need to reduce further, for the nonvolatile memory with autoregistration floating boom (self aligned floating gate), the coupling ratio (coupling ratio) of memory can be improved in the trapezoid cross section of the shallow trench in nonvolatile memory, wherein, coupling ratio is one of important parameter affecting performance of non-volatile memory.Therefore, the key factor that high coupling ratio is the development of non-volatile flash memory technology is increased.
The method of fleet plough groove isolation structure (STI) is formed as shown in Figure 1A-1E at present in nonvolatile flash memory technology, the method that STI traditional in the prior art eat-backs is, as shown in 1A, form the mask layer of definition active area and isolated area on a semiconductor substrate 100, according to hard mask layer etch semiconductor substrates 100 to form groove, pad oxide layer 101 in the trench.As shown in Figure 1B, the active area performing oxidation technology Semiconductor substrate in unit area forms tunnel oxidation layer 102.As shown in Figure 1 C, form floating gate polysilicon layer 103 on a semiconductor substrate, polysilicon layer covers the oxide skin(coating) 101 in tunnel oxidation layer 102 and sti region.As shown in figure ip, perform cmp (CMP) technique to remove unnecessary polysilicon layer, flush to make the top of the oxide skin(coating) 102 in floating boom 104 and sti region.As referring to figure 1e, perform back oxide in the sti region of etching technics removal part to form fleet plough groove isolation structure 105 and increase the coupling ratio of device to expose the sidepiece of floating boom.
In the prior art, wet-etching technology is adopted to perform described time etch step.According to prior art in the process of returning the oxide in etching sti region, loss is created to the sidewall of floating boom, meanwhile, have impact on the coupling ratio of formed nonvolatile memory.
Therefore, need a kind of manufacture method of new semiconductor device, to increase the gate coupling ratio rate of nonvolatile memory, and, to avoid producing loss to the floating boom of nonvolatile memory, the final performance of entirety and the yields of nonvolatile memory improving nonvolatile memory.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
In order to solve problems of the prior art, the present invention proposes a kind of method making semiconductor device, comprise: provide Semiconductor substrate, be formed with hard mask layer on the semiconductor substrate, described hard mask layer comprises the oxide skin(coating) and nitride layer that stack gradually; Etch described hard mask layer and described Semiconductor substrate, to form shallow trench; In described shallow trench, fill spacer material layer, the surface of described spacer material layer is concordant with the surface of described hard mask; Remove described nitride layer; Form spacer material layer on the semiconductor substrate; Etch described spacer material layer, form side wall in the both sides of the described spacer material layer higher than described oxide layer surface; Form floating gate material layer on the semiconductor substrate; Flatening process is performed, till the top of exposing described spacer material layer, to form floating gate structure to described floating gate material layer; The described spacer material layer that etching removal part is exposed, to form fleet plough groove isolation structure, the cross section of the top surface of described fleet plough groove isolation structure is groove type structure; Remove described side wall.
Preferably, the cross section of the top surface of described fleet plough groove isolation structure is inverted trapezoidal.
Preferably, the step of described oxide skin(coating) is removed after being also included in the described side wall of formation.
Preferably, on described semiconductor substrate surface, form the step of tunnel oxidation layer after being also included in the described oxide skin(coating) of removal.
Preferably, the material of described spacer material layer is silicon nitride, adopts spacer material layer described in dry etching to form described side wall.
Preferably, wet etching is adopted to remove described oxide skin(coating).
Preferably, wet etching is adopted to remove described side wall.
Preferably, the step of the described spacer material layer that described etching removal part is exposed comprises: after first carrying out an isotropic etch step, then carry out an anisotropic etching step.
Preferably, adopt wet etching to perform described isotropic etch step, adopt dry etching to perform described anisotropic etching step.
Preferably, described fleet plough groove isolation structure top surface peek higher than described floating gate structure bottom surface residing for plane.
The invention allows for a kind of semiconductor device, comprising: Semiconductor substrate; Be arranged in the fleet plough groove isolation structure of described Semiconductor substrate, the cross section of the top surface of described fleet plough groove isolation structure is groove type structure; Tunnel oxidation layer between described fleet plough groove isolation structure in described Semiconductor substrate; Be positioned at the floating gate structure on described tunnel oxidation layer.
Preferably, the cross section of the top surface of described fleet plough groove isolation structure is inverted trapezoidal.
Preferably, described fleet plough groove isolation structure top surface peek higher than described floating gate structure bottom surface residing for plane.
In sum, according to the groove type structure that the cross section of the top surface of the fleet plough groove isolation structure of the method formation of the spacer material layer in time etching sti region that the present invention proposes is inverted trapezoidal, to make the nonvolatile memory of formation, there is higher gate coupling ratio rate; When returning the spacer material layer in etching sti region, the side wall protection floating gate polysilicon of STI is to avoid the loss to floating boom; Form applicable shallow ditch groove structure in the nonvolatile memory, nonvolatile memory can be made to have very fast erasing speed; Distance suitable between STI edge and piled grids will be conducive to the reliability strengthening flash memories; Also help the cycle performance improving device.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A-1E returns the cross-sectional view of the spacer material layer in the sti region of etching nonvolatile memory according to prior art;
The cross-sectional view of the device that Fig. 2 A-2I obtains for the correlation step of returning the spacer material layer in the sti region of etching nonvolatile memory according to one embodiment of the present invention;
Fig. 3 is the process chart returning the spacer material layer in the sti region of etching nonvolatile memory according to one embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it will be apparent to one skilled in the art that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to illustrate how the present invention solves current Problems existing.Detailed being described below of obvious preferred embodiment of the present invention, but remove outside these detailed descriptions, the present invention can also have other execution modes.
Should give it is noted that term used here is only to describe specific embodiment, and be not intended to restricted root according to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative be also intended to comprise plural form.In addition, it is to be further understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.Should be understood that, providing these embodiments to be of the present inventionly disclose thorough and complete to make, and the design of these exemplary embodiments fully being conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, exaggerate the thickness in layer and region, and use the element that identical Reference numeral represents identical, thus will omit description of them.
The manufacture method of the oxide skin(coating) returned in the sti region of etching nonvolatile memory the present invention below in conjunction with Fig. 2 A-2I is described in detail, and Fig. 2 A-2I is the structural section figure returning memory in the process of the oxide skin(coating) in the sti region of etching nonvolatile memory according to the present embodiment.
As shown in Figure 2 A, provide Semiconductor substrate 200, in the substrate 200 of described semiconductor, be formed with trap.
Described Semiconductor substrate can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.Exemplarily, in the present embodiment, the constituent material of Semiconductor substrate selects monocrystalline silicon.
In an example of the present invention, define memory cell region, peripheral logic circuit region in the semiconductor substrate.Only be described memory cell region in the present invention, other regions are just not described in detail at this.As shown in Figure 2 A for having the Semiconductor substrate 200 of memory cell region.Semiconductor substrate 200 has active area.
Form hard mask layer on semiconductor substrate 200, described hard mask layer comprises the oxide skin(coating) 201 and nitride layer that stack gradually, concrete, and oxide skin(coating) 201 forms nitride layer.Shallow trench and active area is defined on semiconductor substrate 200 by STI photoetching process.Oxide skin(coating) 201 can pass through thermal oxidation, chemical vapor deposition (CVD) or oxynitridation process and be formed.Oxide skin(coating) can comprise following any conventional dielectric: SiO
2, SiON, SiON
2, and comprise other similar oxide of perofskite type oxide.Wherein, the material of oxide skin(coating) preferably uses silica, and generation type adopts thermal oxidation method.
In a specific embodiment of the present invention, the method for definition shallow trench is: at semiconductor substrate surface coating photoresist, expose and develop, by predefined graph transfer printing on photoresist to photoresist.Then with remaining photoresist for mask etches, Semiconductor substrate part not covered by photoresist is etched successively, etching hard mask layer (nitride layer and oxide skin(coating) 201) and Semiconductor substrate, form shallow trench, the bottom of this shallow trench is arranged in Semiconductor substrate.
Then, the filling of shallow trench is carried out, depositing isolation material layer in described shallow trench and on silicon nitride layer, spacer material layer preferential oxidation nitride layer.In an embodiment of the present invention, adopting HDP(high-density plasma) depositing operation forms oxide skin(coating) in described shallow trench and on nitride layer, the material of oxide skin(coating) is preferably silicon dioxide, adopt HDP-CVD(high density plasma chemical vapor deposition) form oxide skin(coating), HDP-CVD technique synchronously carries out depositing in same reaction chamber and sputter reacting, and the reacting gas that HDP-CVD technique adopts comprises SiH
4and O
2, and sputtering gas hydrogen and helium.Because deposition and sputtering technology are carried out simultaneously, by adjustment SiH
4and O
2and the content of hydrogen and helium is to make sputtering sedimentation ratio for 1:1.
Planarization is carried out to the spacer material layer of Semiconductor substrate, the surface of described spacer material layer is concordant with the surface of described hard mask, concrete, remove the spacer material layer be positioned on nitride layer, then nitride layer is removed, define room in the position at original nitride layer place, make the surface of the spacer material layer 202 of filling shallow trench far away higher than other positions, after removal nitride layer, expose oxide skin(coating) 201 simultaneously.
Then, form spacer material layer 203 on semiconductor substrate 200, spacer material layer 203 is capping oxidation nitride layer 201 and the spacer material layer 202 being arranged in shallow trench completely.The material preferred nitrogen SiClx of spacer material layer 203.The method forming spacer material layer includes but not limited to use: process for chemical vapor deposition of materials with via and physical vapor deposition methods, any applicable the present invention can form the method for spacer material layer.
As shown in Figure 2 B, described spacer material layer 203 is etched to form side wall 204 in the both sides of the spacer material layer 202 exceeding oxide skin(coating) 201 surface.Side wall 204 to be positioned on oxide skin(coating) 201 and to be positioned at the both sides of the spacer material layer 202 higher than described oxide skin(coating) 201 surface.Dry etch process can be adopted to etch spacer material layer 203 to form described side wall 204.Wherein, the side wall 204 being positioned at spacer material layer 202 both sides can guarantee the width of floating gate polysilicon layer, simultaneously, the side wall 204 being positioned at spacer material layer 202 both sides can avoid the loss to polysilicon layer, to be conducive to the filling (fill-in) of oxide/nitride/oxide (oxide-nitride-oxide, ONO) lamination and to avoid the problem of floating gate polysilicon layer loss.
Dry method etch technology includes but not limited to: reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.Such as using plasma etching, etching gas can adopt based on fluorine-containing gas.Concrete, adopt lower radio-frequency (RF) energy also can produce low pressure and highdensity plasma gas to realize dry etching.As an example, the range of flow of the etching gas of using plasma etching can be 50 cc/min (sccm) ~ 150 cc/min (sccm), and reative cell internal pressure can be 5 millitorrs (mTorr) ~ 20 millitorr (mTorr).Wherein, the etching gas of dry etching can be bromize hydrogen gas, carbon tetrafluoride gas or gas of nitrogen trifluoride, can also pass into some and add gas, as nitrogen, helium or oxygen etc.
It should be noted that, the method for above-mentioned formation side wall is exemplary, is not limited to described method, as long as this area additive method can realize described object, all can be applied to the present invention, not repeat them here.
As shown in Figure 2 C, remove the oxide skin(coating) 201 be positioned in Semiconductor substrate 200, wet etching oxide skin(coating) 201 can be adopted to expose Semiconductor substrate 200.Wherein, described wet etching has lower etching selection ratio to oxide skin(coating), has higher etching selection ratio to side wall, can not cause loss to side wall.
The solution of described wet-cleaned can adopt one in the hydrofluoric acid of dilution or hot phosphoric acid or two kinds.In a specific embodiment of the present invention, form photoresist layer on a semiconductor substrate, the light shield with setting tunnel oxidation layer window is adopted to expose photoresist layer, again to the photoresist layer development after exposure, obtain the photoresist layer with tunnel oxidation layer window, then, there is the photoresist layer of tunnel oxidation layer window for mask, wet etching is carried out to oxide skin(coating) 201 and exposes Semiconductor substrate 200.Wet etch method can adopt hydrofluoric acid solution, such as buffer oxide etch agent (BOE) or hydrofluoric acid cushioning liquid (BHF).
As shown in Figure 2 D, with the photoresist layer with tunnel oxidation layer window for mask wet etching oxide skin(coating) 201 after on semiconductor substrate 200 formed tunnel oxidation layer 205, the material of described tunnel oxidation layer can be silica, silicon oxynitride, silicon rich oxide, silicon nitride.The effect of described tunnel oxidation layer is floating gate polysilicon layer and Semiconductor substrate isolation, and thickness is set in 10 dust to 150 dusts.The technology of deposit those tunnel oxidation layer is prior art well known to those skilled in the art, forms silicon oxide layer as adopted thermal oxidation technology.
As shown in Figure 2 E, deposition forms floating gate material layer 206 on semiconductor substrate 200, and the preferred polysilicon of material of floating gate material layer, described floating gate material layer 206 covers spacer material layer 202, side wall 204 and tunnel oxidation layer 205 completely.
The formation method forming floating gate material layer in the present invention can select low-pressure chemical vapor phase deposition (LPCVD) technique.The process conditions forming described polysilicon layer comprise: reacting gas is silane (SiH4), and the range of flow of described silane can be 100 ~ 200 cc/min (sccm), as 150sccm; In reaction chamber, temperature range can be 700 ~ 750 degrees Celsius; Reaction chamber internal pressure can be 250 ~ 350 millis millimetres of mercury (mTorr), as 300mTorr; Also can comprise buffer gas in described reacting gas, described buffer gas can be helium (He) or nitrogen, and the range of flow of described helium and nitrogen can be 5 ~ 20 liters/min (slm), as 8slm, 10slm or 15slm.
It should be noted that, the method for above-mentioned formation floating gate material layer is exemplary, is not limited to described method, as long as this area additive method can realize described object, all can be applied to the present invention, not repeat them here.
As shown in Figure 2 F, flatening process is performed to floating gate material layer 206, till the top of exposing described spacer material layer 202, to form floating gate structure 207.Alternatively, after the top of the spacer material layer 202 exposed in shallow plough groove isolation area, carry out a certain amount of polishing excessively to ensure that process window then stops flatening process, to form floating gate structure.Separated from one another by the floating gate structure 207 making filling be formed in tunnel oxide 205 between spacer material layer 202 after flatening process process floating gate material layer.
Flattening method conventional in field of semiconductor manufacture can be used to realize the planarization on surface.The limiting examples of this flattening method comprises mechanical planarization method and chemico-mechanical polishing flattening method.Chemico-mechanical polishing flattening method is more conventional.
As shown in Figure 2 G, the spacer material layer 202 that the first step performing back etching technics exposes with removal part, the first step of described time etching technics is isotropic etching spacer material layer 202, concrete, the spacer material layer 202 being arranged in fleet plough groove isolation structure region first adopting wet etching removal part to expose, etches rear remaining spacer material layer 202 ' lower than floating gate structure 207 higher than tunnel oxide 205.
In a specific embodiment of the present invention, after spacer material layer 202 described in employing wet etching, spacer material layer 202 ' the surface formed is smooth, the structure of the spacer material layer 202 ' formed after wet etching is identical with the structure of the spacer material layer in the isolation shallow ditch groove structure that prior art is formed, in an embodiment of the present invention, subsequent process steps etches based on the spacer material layer 202 ' with flat surfaces
Wet etch method can adopt hydrofluoric acid solution, such as buffer oxide etch agent or hydrofluoric acid cushioning liquid.Wet-cleaned adopts the hydrofluoric acid of dilution and hot phosphoric acid to remove described oxide skin(coating).
As illustrated in figure 2h, the spacer material layer 202 ' that the second step performing back etching technics exposes with removal part, the second step of described time etching technics is anisotropic etching spacer material layer 202 ', etch based on spacer material layer 202 ' structure as shown in figure 2g, described time etch step is anisotropic etching spacer material layer 202 ', concrete, dry etching is adopted to be arranged in the spacer material layer 202 ' in fleet plough groove isolation structure region again, to form fleet plough groove isolation structure 208.After adopting the oxide skin(coating) 202 ' that dry etching removal part exposes, the cross section of the top surface of the fleet plough groove isolation structure 208 formed in shallow plough groove isolation area is groove type structure, described groove type structure can be the groove type structure of the semiconductor device structure in the applicable embodiment of the present invention such as bowl-type, inverted trapezoidal, preferably, described groove type structure is inverted trapezoidal, be equivalent to, the cross section of the top surface of described fleet plough groove isolation structure 208 is inverted trapezoidal.
In a specific embodiment of the present invention, adopt in the process of spacer material layer 202 ' described in dry etching, the height of spacer material layer 202 ' does not become, be equivalent to, the length of the top-to-bottom of spacer material layer 202 ' both sides is identical with the length of the top-to-bottom of fleet plough groove isolation structure 208 both sides formed after wet etching, dry etching only etches spacer material layer 202 ' core, to form groove type structure.
Dry method etch technology includes but not limited to: reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.Such as using plasma etching, etching gas can adopt based on fluorine-containing gas.Concrete, adopt lower radio-frequency (RF) energy also can produce low pressure and highdensity plasma gas to realize dry etching.As an example, the range of flow of the etching gas of using plasma etching can be 50 cc/min (sccm) ~ 150 cc/min (sccm), and reative cell internal pressure can be 5 millitorrs (mTorr) ~ 20 millitorr (mTorr).Wherein, the etching gas of dry etching can be bromize hydrogen gas, carbon tetrafluoride gas or gas of nitrogen trifluoride, can also pass into some and add gas, as nitrogen, helium or oxygen etc.
As shown in figure 2i, etching removes side wall 204, to expose the sidewall of floating gate structure 207, preferably adopts wet etching to remove side wall 204.After removing side wall 204, fleet plough groove isolation structure 208 is defined because the spacer material layer 202 in shallow plough groove isolation area has carried out time etching technics, the edge of floating gate structure 207 is no longer adjacent with fleet plough groove isolation structure 208, makes floating boom have higher coupling ratio.Meanwhile, described fleet plough groove isolation structure 208 top surface peek higher than described floating gate structure 207 bottom surface residing for plane
With reference to Fig. 3, illustrated therein is the process chart of the oxide skin(coating) in the sti region for returning etching nonvolatile memory according to one embodiment of the present invention.For schematically illustrating the flow process of whole manufacturing process.
In step 301, Semiconductor substrate is provided, shallow trench is formed in described Semiconductor substrate, the active area of described Semiconductor substrate is formed with oxide skin(coating), spacer material layer is filled in described shallow trench, spacer material layer is higher than oxide layer surface, and deposition forms spacer material layer on the semiconductor substrate;
In step 302, adopt spacer material layer described in dry etching, higher than described oxide layer surface the both sides of described isolated material form side wall;
In step 303, wet etching removes described oxide skin(coating), to expose described Semiconductor substrate;
In step 304, tunnel oxidation layer is formed on the surface of described Semiconductor substrate;
In step 305, deposition forms floating gate material layer on the semiconductor substrate;
Within step 306, chemical mechanical milling tech is adopted, to remove unnecessary floating gate material layer;
In step 307, perform back described spacer material layer that etching technics remove portion exposes to form fleet plough groove isolation structure, concrete, first perform wet etching and adopt dry etching again;
In step 308, wet etching is adopted to remove described side wall.
In addition, beyond the preparation method that the invention provides described semiconductor device, additionally provide a kind of semiconductor device, comprising:
Semiconductor substrate;
Be arranged in the fleet plough groove isolation structure of described Semiconductor substrate, the cross section of the top surface of described fleet plough groove isolation structure is groove type structure;
Tunnel oxidation layer between described fleet plough groove isolation structure in described Semiconductor substrate;
Be positioned at the floating gate structure on described tunnel oxidation layer.
The cross section of the top surface of described fleet plough groove isolation structure is inverted trapezoidal.
The top surface peek of described fleet plough groove isolation structure higher than described floating gate structure bottom surface residing for plane.
In sum, according to the groove type structure that the cross section of the top surface of the fleet plough groove isolation structure of the method formation of the oxide in time etching sti region that the present invention proposes is inverted trapezoidal, to make the nonvolatile memory of formation, there is higher gate coupling ratio rate; When returning the oxide in etching sti region, the side wall protection floating gate polysilicon of STI is to avoid the loss to floating boom; Form suitable shallow ditch groove structure in the nonvolatile memory, nonvolatile memory can be made to have very fast erasing speed; Distance suitable between STI edge and piled grids will be conducive to the reliability strengthening flash memories; Also help the cycle performance improving device.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to the present invention, within these variants and modifications all drop on the present invention's scope required for protection.
Claims (13)
1. make a method for semiconductor device, comprising:
Semiconductor substrate is provided,
Be formed with hard mask layer on the semiconductor substrate, described hard mask layer comprises the oxide skin(coating) and nitride layer that stack gradually;
Etch described hard mask layer and described Semiconductor substrate, to form shallow trench;
In described shallow trench, fill spacer material layer, the surface of described spacer material layer is concordant with the surface of described hard mask;
Remove described nitride layer;
Form spacer material layer on the semiconductor substrate;
Etch described spacer material layer, form side wall in the both sides of the described spacer material layer higher than described oxide layer surface;
Form floating gate material layer on the semiconductor substrate;
Flatening process is performed, till the top of exposing described spacer material layer, to form floating gate structure to described floating gate material layer;
The described spacer material layer that etching removal part is exposed, to form fleet plough groove isolation structure, the cross section of the top surface of described fleet plough groove isolation structure is groove type structure;
Remove described side wall.
2. the method for claim 1, is characterized in that, the cross section of the top surface of described fleet plough groove isolation structure is inverted trapezoidal.
3. the method for claim 1, is characterized in that, is also included in the step removing described oxide skin(coating) after forming described side wall.
4. method as claimed in claim 3, is characterized in that, is also included in the step forming tunnel oxidation layer after removing described oxide skin(coating) on described semiconductor substrate surface.
5. the method for claim 1, is characterized in that, the material of described spacer material layer is silicon nitride, adopts spacer material layer described in dry etching to form described side wall.
6. method as claimed in claim 3, is characterized in that, adopts wet etching to remove described oxide skin(coating).
7. the method for claim 1, is characterized in that, adopts wet etching to remove described side wall.
8. the method for claim 1, is characterized in that, the step of the described spacer material layer that described etching removal part is exposed comprises: after first carrying out an isotropic etch step, then carry out an anisotropic etching step.
9. method as claimed in claim 8, is characterized in that, adopts wet etching to perform described isotropic etch step, adopts dry etching to perform described anisotropic etching step.
10. the method for claim 1, is characterized in that, the top surface peek of described fleet plough groove isolation structure higher than described floating gate structure bottom surface residing for plane.
11. 1 kinds of semiconductor device, comprising:
Semiconductor substrate;
Be arranged in the fleet plough groove isolation structure of described Semiconductor substrate, the cross section of the top surface of described fleet plough groove isolation structure is groove type structure;
Tunnel oxidation layer between described fleet plough groove isolation structure in described Semiconductor substrate;
Be positioned at the floating gate structure on described tunnel oxidation layer.
12. devices as claimed in claim 11, is characterized in that, the cross section of the top surface of described fleet plough groove isolation structure is inverted trapezoidal.
13. devices as claimed in claim 11, is characterized in that, the top surface peek of described fleet plough groove isolation structure higher than described floating gate structure bottom surface residing for plane.
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| CN107946304A (en) * | 2017-11-22 | 2018-04-20 | 上海华力微电子有限公司 | One kind is used for size reduction NORFlash cell process integrated approaches |
| CN109755246A (en) * | 2017-11-03 | 2019-05-14 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof |
| CN109786383A (en) * | 2017-11-13 | 2019-05-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof and semiconductor structure |
| CN111199881A (en) * | 2018-11-20 | 2020-05-26 | 长鑫存储技术有限公司 | Preparation method of semiconductor structure |
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