CN104681431A - Production method of semiconductor device - Google Patents
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- CN104681431A CN104681431A CN201310641608.8A CN201310641608A CN104681431A CN 104681431 A CN104681431 A CN 104681431A CN 201310641608 A CN201310641608 A CN 201310641608A CN 104681431 A CN104681431 A CN 104681431A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Abstract
The embodiment of the invention discloses a production method of a semiconductor device. The production method comprises the steps of providing a semiconductor substrate; forming a groove in the semiconductor substrate; forming an epitaxial layer on the surface of one side, provided with the groove, of the semiconductor substrate, completely filling the groove with the epitaxial layer, wherein a doping type of the epitaxial layer is different from that of the semiconductor substrate; forming a drifting area on the surface of the epitaxial layer, wherein the drifting area completely covers the semiconductor substrate and the epitaxial layer; forming a front surface structure on the surface of the drifting area; thinning one side, away from the front surface structure, of the semiconductor substrate to form a current collection area, wherein the current collection area comprises a first doping-type current collection area and a second doping-type current collection area, which are arranged in parallel. By utilizing the production method provided by the invention, when a three-mode integrated insulation grid bipolar transistor is produced, a back surface photoetching process is not needed, so that the problem of the high breaking rate caused by the back surface photoetching process can be solved, and the rate of finished products of the three-mode integrated insulation grid bipolar transistor can be increased.
Description
Technical field
The present invention relates to semiconductor device processing technology field, particularly relate to a kind of manufacturing method of semiconductor device.
Background technology
Insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, be called for short IGBT) the compound full-control type voltage driven type power semiconductor that is made up of double pole triode (BJT) and insulating gate type field effect tube (MOSFET), have the advantage of the high input impedance of MOSFET element and low conduction voltage drop two aspect of power transistor (i.e. huge transistor is called for short GTR) concurrently.As shown in Figure 1, the back side due to described IGBT device is P type semiconductor, and when conducting, a large amount of holes can be injected in its P type collector region, there is conductivity modulation effect, reduce its conduction voltage drop, thus when it is turned off need the few sub-compound of surplus to fall, cause its turn-off speed slower.
Vertical double diffused metal-oxide field-effect transistor (Vertical Double diffused MOS, be called for short VDMOS), source-drain electrode electric current is controlled by grid voltage, there is drive circuit simple, driving power is little, fast and the operating frequency high of switching speed, has good switching characteristic and linear characteristic.As shown in Figure 2, the back side due to described VDMOS device is N type semiconductor, belongs to unipolar device, along with the increase that it is withstand voltage, its conduction voltage drop can be caused to increase rapidly.
Fast recovery diode (Fast Recovery Diode, be called for short FRD), it is good to be that one has switching characteristic, the semiconductor diode that reverse recovery time is short, main in the electronic circuits such as Switching Power Supply, PWM pulse width modulator, frequency converter, use as high-frequency rectification diode, fly-wheel diode or damper diode.
Therefore, people have invented the integrated insulated gate bipolar transistor of a kind of three-mode (Triple mode Integrate Insulated Gate Bipolar Transistor, be called for short TI-IGBT), as shown in Figure 3, the 26S Proteasome Structure and Function of IGBT, VDMOS, FRD tri-kinds of devices is combined cleverly.Described TI-IGBT device similar IGBT when forward conduction, has less conduction voltage drop; The similar VDMOS when turning off, has turn-off speed faster; FRD is similar to, without inverse parallel fast recovery diode when bearing back-pressure.But in prior art, the manufacture method fragment rate of TI-IGBT is higher, and rate of finished products is lower.
Summary of the invention
For solving the problems of the technologies described above, embodiments provide a kind of manufacturing method of semiconductor device, to reduce the fragment rate in the integrated insulated gate bipolar transistor manufacturing process of three-mode, improve the rate of finished products of the integrated insulated gate bipolar transistor manufacture method of three-mode.
For solving the problem, embodiments provide following technical scheme:
A kind of manufacturing method of semiconductor device, comprising:
Semiconductor substrate is provided;
Groove is formed in described Semiconductor substrate;
Form epitaxial loayer at the reeded side surface of described Semiconductor substrate tool, described epitaxial loayer fills described groove completely, and the doping type of described epitaxial loayer is different from the doping type of described Semiconductor substrate;
Form drift region in described epi-layer surface, described drift region covers described Semiconductor substrate and described epitaxial loayer completely;
Facad structure is formed on surface, described drift region;
The side described Semiconductor substrate being deviated to described Facad structure is carried out thinning, and form collector region, described collector region comprises the first doping type collector region and the second doping type collector region that are set up in parallel.
Preferably, form epitaxial loayer at the reeded side surface of described Semiconductor substrate tool, described epitaxial loayer is filled described groove completely and is comprised:
Form epitaxial loayer at the semiconductor substrate surface being only positioned at described groove, described epitaxial loayer fills described groove completely.
Preferably, the doping type of described epitaxial loayer and the doping type of described drift region identical or different.
Preferably, form epitaxial loayer at the reeded side surface of described Semiconductor substrate tool, described epitaxial loayer is filled described groove completely and is comprised:
Form described epitaxial loayer at the reeded side surface of described Semiconductor substrate tool, described epitaxial loayer fills described groove completely, and covers the reeded side surface of described Semiconductor substrate tool completely.
Preferably, the doping type of described epitaxial loayer is identical with the doping type of described drift region.
Preferably, in described epitaxial loayer, the formation process of Doped ions is in-situ doped, ion implantation or diffusion.
Preferably, described semiconductor device is duck semiconductor device or plane grid-type semiconductor device.
Preferably, the method also comprises: form resilient coating in described epi-layer surface, described resilient coating covers described Semiconductor substrate and described epitaxial loayer completely, and identical with the doping type of described drift region.
Preferably, the degree of depth of described groove is the thickness of collector region in described semiconductor device.
Preferably, described semiconductor device is the integrated insulated gate bipolar transistor of three-mode.
Compared with prior art, technique scheme has the following advantages:
The technical scheme that the embodiment of the present invention provides, first in Semiconductor substrate, form groove, then in described groove, epitaxial loayer is formed, because described Semiconductor substrate is different with the doping type of described epitaxial loayer, so after described Semiconductor substrate and epi-layer surface form drift region and Facad structure successively, undertaken thinning by the side described Semiconductor substrate being deviated to described Facad structure, the collector region comprising the first doping type collector region and the second doping type collector region be set up in parallel can be formed, thus the back light carving technology that instead of in prior art when forming the P type collector region and N-type collector region that are set up in parallel, make the manufacture method that the embodiment of the present invention provides, when the integrated insulated gate bipolar transistor of making three-mode, without the need to adopting back light carving technology again, solve the problem that the fragment rate that causes due to back light carving technology is high, improve the rate of finished products of the integrated insulated gate bipolar transistor of three-mode.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of IGBT in prior art;
Fig. 2 is the structural representation of VDMOS in prior art;
Fig. 3 is the structural representation of TI-IGBT in prior art;
Fig. 4-Fig. 7 is the manufacture method flow chart of TI-IGBT in prior art;
The manufacturing method of semiconductor device flow chart that Fig. 8-Figure 16 provides for the embodiment of the present invention.
Embodiment
Just as described in the background section, in prior art, the manufacture method fragment rate of TI-IGBT is higher, and rate of finished products is lower.
Inventor studies discovery, and the manufacture method of TI-IGBT in prior art, comprising: as shown in Figure 4, provide substrate; As shown in Figure 5, Facad structure is formed at substrate surface; As shown in Figure 6, thinning back side is carried out to the side that described substrate deviates from described Facad structure; As shown in Figure 7, thinning complete after, the side deviating from described Facad structure at described substrate forms P type collector region arranged side by side and N-type shorting region.Wherein, the side deviating from described Facad structure at described substrate forms P type collector region arranged side by side and N-type collector region comprises: the side deviating from described Facad structure at described substrate forms photoresist; Remove the photoresist of P type collector region to be formed region surface, and by ion implantation or be diffused in region, P type collector region to be formed formed P type collector region; Photoresist is formed on the surface of P type collector region; Remove the photoresist of N-type collector region to be formed region surface, and by ion implantation or be diffused in region, N-type collector region to be formed formed N-type collector region; Remove the photoresist on surface, P type collector region.
It should be noted that, when described substrate is P type substrate, and the doping content of its P type ion identical with the doping content of P type collector region to be formed time, form P type collector region arranged side by side in the side that described substrate deviates from described Facad structure and N-type collector region comprises: the side deviating from described Facad structure at described substrate forms photoresist; Remove the photoresist of N-type collector region to be formed region surface, and by ion implantation or be diffused in region, N-type collector region to be formed formed N-type collector region; Remove the photoresist on surface, P type collector region.
When described substrate is N-type substrate, and the doping content of its N-type ion identical with the doping content of N-type collector region to be formed time, form P type collector region arranged side by side in the side that described substrate deviates from described Facad structure and N-type collector region comprises: the side deviating from described Facad structure at described substrate forms photoresist; Remove the photoresist of P type collector region to be formed region surface, and by ion implantation or be diffused in region, P type collector region to be formed formed P type collector region; Remove the photoresist of N-type collector region to be formed region surface.
As from the foregoing, TI-IGBT manufacture method of the prior art at least needs 1-2 back light carving technology, and the thickness of substrate after thinning back side and Facad structure is less than 100 microns.Carry out the techniques such as photoetching, etching and ion implantation to so thin silicon chip structure, very easily cause fragment, cause the manufacture method fragment rate of TI-IGBT in prior art higher, rate of finished products is lower.
And, due to the particularity of back side photoetching, back side photoetching not only cost itself higher than front photoetching, also overleaf in photoetching process, need preparation back side lithography mask version, and the cost of back side lithography mask version is very high, thus causes the manufacture method cost of TI-IGBT in prior art higher.
In addition, back light carving technology does not belong to the common process of semiconductor machining, needs advanced equipment, the equipment that a lot of factory is not correlated with, and causes the difficulty of processing of back side photoetching comparatively large, thus causes the manufacture method difficulty of TI-IGBT in prior art larger.
In view of this, embodiments provide a kind of manufacturing method of semiconductor device, comprising:
Semiconductor substrate is provided;
Groove is formed in described Semiconductor substrate;
Form epitaxial loayer at the reeded side surface of described Semiconductor substrate tool, described epitaxial loayer fills described groove completely, and the doping type of described epitaxial loayer is different from the doping type of described Semiconductor substrate;
Form drift region in described epi-layer surface, described drift region covers described Semiconductor substrate and described epitaxial loayer completely;
Facad structure is formed on surface, described drift region;
The side described Semiconductor substrate being deviated to described Facad structure is carried out thinning, and form collector region, described collector region comprises the first doping type collector region and the second doping type collector region that are set up in parallel.
The technical scheme that the embodiment of the present invention provides, first in Semiconductor substrate, form groove, epitaxial loayer is formed again in described groove, because described Semiconductor substrate is different with the doping type of described epitaxial loayer, so after described Semiconductor substrate and epi-layer surface form drift region and Facad structure successively, undertaken thinning by the side described Semiconductor substrate being deviated to described Facad structure, the collector region comprising the first doping type collector region and the second doping type collector region be set up in parallel can be formed, thus the back light carving technology that instead of in prior art when forming the P type collector region and N-type collector region that are set up in parallel, make the manufacture method that the embodiment of the present invention provides, when the integrated insulated gate bipolar transistor of making three-mode, without the need to adopting back light carving technology again, solve the problem that the fragment rate that causes due to back light carving technology is high, improve the rate of finished products of the integrated insulated gate bipolar transistor of three-mode.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.Below for described semiconductor device for the integrated insulated gate bipolar transistor of three-mode, manufacturing method of semiconductor device provided by the present invention is described in detail, but manufacture method provided by the present invention is not limited in the making of the integrated insulated gate bipolar transistor of described three-mode, for other semiconductor device as device architectures such as FRD, GTO, IEGT, IGCT, MTO or IGDT, as long as the collector region of described semiconductor device comprises N-type collector region mutually arranged side by side and P type collector region, manufacturing method of semiconductor device provided by the present invention is all applicable.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here to implement with multiple, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention.Therefore the present invention is not by the restriction of following public concrete enforcement.
Embodiment one:
Embodiments provide a kind of manufacturing method of semiconductor device, comprising:
Step 1: Semiconductor substrate is provided.
In one embodiment of the invention, the monocrystalline silicon piece providing described Semiconductor substrate namely to get to have certain doping type and doping content is as Semiconductor substrate, wherein, described monocrystalline silicon piece can be CZ silicon chip or FZ silicon chip, and crystal orientation can unrestricted choice, the present invention does not limit this, is determined on a case-by-case basis.In other embodiments of the invention, the material of described Semiconductor substrate can also be SiC, GaN, diamond or GaP etc., and the present invention does not limit this.
Step 2: as shown in Figure 8, forms groove in described Semiconductor substrate.
In one embodiment of the invention, step 2 comprises:
Photoresist is formed at described semiconductor substrate surface;
Described photoresist defines open area, described photoresist is etched;
With described photoresist for mask, described Semiconductor substrate is etched, in described Semiconductor substrate, form groove.
It should be noted that, in one embodiment of the invention, described open area is corresponding with the region of P type collector region to be formed in described Semiconductor substrate; In another embodiment of the present invention, described open area is corresponding with the region of N-type collector region to be formed in described Semiconductor substrate.
Also it should be noted that, in a preferred embodiment of the invention, the degree of depth of described groove is identical with the thickness of collector region in described semiconductor device, in of the present invention other are implemented, the degree of depth of described groove can also be greater than or be slightly less than the thickness of collector region in described semiconductor device, the present invention does not limit this, specifically depends on the circumstances.
Step 3: form epitaxial loayer at the reeded side surface of described Semiconductor substrate tool, described epitaxial loayer fills described groove completely, and the doping type of described epitaxial loayer is different from the doping type of described Semiconductor substrate.
In embodiments of the present invention, described Semiconductor substrate can be P type semiconductor substrate, also can be N type semiconductor substrate, when described Semiconductor substrate is P type semiconductor substrate, described epitaxial loayer is N-type epitaxy layer, and the doping content of described Semiconductor substrate is identical with the doping content of P type collector region in described semiconductor device, the doping content of described epitaxial loayer is identical with the doping content of N-type collector region in described semiconductor device.When described Semiconductor substrate is N type semiconductor substrate, described epitaxial loayer is P type epitaxial loayer, and the doping content of described Semiconductor substrate is identical with the doping content of N-type collector region in described semiconductor device, the doping content of described epitaxial loayer is identical with the doping content of P type collector region in described semiconductor device.
In one embodiment of the invention, epitaxial loayer is formed at the reeded side surface of described Semiconductor substrate tool, described epitaxial loayer is filled described groove completely and is comprised: form epitaxial loayer at the semiconductor substrate surface being only positioned at described groove, described epitaxial loayer fills described groove completely.That is, described epitaxial loayer is only formed in described groove, and fills described groove completely, as shown in Figure 9.More specifically, epitaxial loayer is formed at the semiconductor substrate surface being only positioned at described groove, described epitaxial loayer is filled described groove completely and is comprised: form described epitaxial loayer at the reeded side surface of described Semiconductor substrate tool, described epitaxial loayer fills described groove completely, and covers the reeded side surface of described Semiconductor substrate tool completely; Remove the semiconductor substrate surface epitaxial loayer being positioned at described groove both sides, form epitaxial loayer at the semiconductor substrate surface being only positioned at described groove.
In another embodiment of the present invention, epitaxial loayer is formed at the reeded side surface of described Semiconductor substrate tool, described epitaxial loayer is filled described groove completely and is comprised: form described epitaxial loayer at the reeded side surface of described Semiconductor substrate tool, described epitaxial loayer fills described groove completely, and covers the reeded side surface of described Semiconductor substrate tool completely.That is, described epitaxial loayer is not only formed in described groove, also covers the whole surface that described Semiconductor substrate has groove side, as shown in Figure 10.
It should be noted that, in the process forming described epitaxial loayer, in described epitaxial loayer, the formation process of Doped ions is in-situ doped, ion implantation or diffusion.That is, in one embodiment of the invention, adopt in-situ doped mode, in epitaxially grown process, introduce Doped ions, form the epitaxial loayer with collector region in described semiconductor device with identical doping content.In another embodiment of the present invention, also first extension one deck can be adopted not have the epitaxial loayer of Doped ions, adopt ion implantation or diffusion technology again, the epitaxial loayer without Doped ions is adulterated, forms the epitaxial loayer with collector region in described semiconductor device with identical doping content.The present invention does not limit this, specifically depends on the circumstances.
It should be noted that, due to before the described epitaxial loayer of making, the surface out-of-flatness of described Semiconductor substrate, therefore, after described epitaxial loayer completes, need to carry out front attenuated polishing to described epi-layer surface, to improve described epi-layer surface evenness.
Step 4: form drift region in described epi-layer surface, described drift region covers described Semiconductor substrate and described epitaxial loayer completely.
In one embodiment of the invention, as shown in figure 11, when described epitaxial loayer is only formed in described groove, the doping type of described epitaxial loayer can be identical with the doping type of described drift region, also can be different, namely when described semiconductor device is N channel-type semiconductor device, the doping type of described drift region is N-type doping, the doping type of described epitaxial loayer can adulterate for N-type, also can adulterate for P type; When described semiconductor device is P channel-type semiconductor device, the doping type of described drift region is the doping of P type, and the doping type of described epitaxial loayer also can adulterate for N-type, or can adulterate for P type, and the present invention does not limit this.
In another embodiment of the invention, as shown in figure 12, when described epitaxial loayer is not only formed in described groove, and when covering the reeded side surface of described Semiconductor substrate tool completely, because described epitaxial loayer is positioned at the part of described groove for the formation of follow-up collector region, and described epitaxial loayer is positioned at the part of the part outside described groove for the drift region as follow-up formation.Therefore, in this embodiment, the doping type of described epitaxial loayer is identical with the doping type of described drift region, namely when described semiconductor device is N channel-type semiconductor device, the doping type of described drift region is N-type doping, and the doping type of described epitaxial loayer is also N-type doping; When described semiconductor device is P channel-type semiconductor device, the doping type of described drift region is the doping of P type, and the doping type of described epitaxial loayer is also the doping of P type.
It should be noted that, the semiconductor device that the embodiment of the present invention provides can be non-punch semiconductor device, and also can be punch semiconductor device, the present invention limit this.
In one embodiment of the invention, described semiconductor device is non-punch semiconductor device.In this embodiment, as is illustrated by figs. 11 and 12, after epitaxial loayer is formed, directly form drift region in described epi-layer surface, the doping content of described drift region is less than the doping content of described epitaxial loayer.
In another embodiment of the present invention, described semiconductor device is punch semiconductor device.In this embodiment, as shown in figure 13, the method also comprises: between described epitaxial loayer and described drift region, form resilient coating, the doping type of described resilient coating is identical with the doping type of described drift region, and the doping content of described resilient coating is greater than the doping content of described drift region, and be less than the doping content of described epitaxial loayer.That is, after epitaxial loayer is formed, first resilient coating is formed in described epi-layer surface; Again in the formation drift region, surface of described resilient coating.Wherein, the doping content of described resilient coating is greater than the doping content of drift region, is less than the doping content of epitaxial loayer.
It should be noted that, in embodiments of the present invention, the formation process of described drift region and resilient coating can be epitaxy technique, and can be also depositing technics, the present invention limit this, specifically depends on the circumstances.
After extension or depositing technics, the evenness on surface, described drift region can decline, and therefore, after described drift region is formed, needs front attenuated polishing, to improve the evenness on surface, described drift region.And in described drift region when being formed, need reserved enough thickness, to ensure after the front leveling of described drift region, the thickness of described drift region still can bear enough withstand voltage.
Also it should be noted that, the semiconductor device of different electric pressure, described resilient coating is not identical with thickness with the doping concentration distribution of drift region yet, and the present invention does not limit this, specifically depends on the circumstances.
Step 5: form Facad structure on surface, described drift region.It should be noted that, the semiconductor device that the embodiment of the present invention provides can be planar gate type semiconductor device, and also can be duck semiconductor device, the present invention limit this.
Below for described semiconductor device for the integrated insulated gate bipolar transistor of N raceway groove three-mode, the manufacture method that the embodiment of the present invention provides is described, but manufacture method provided by the present invention does not limit this, be equally applicable to the integrated insulated gate bipolar transistor of P raceway groove three-mode or other semiconductor device.
In one embodiment of the invention, described semiconductor device is the integrated insulated gate bipolar transistor of plane grid-type three-mode.In this embodiment, as shown in figure 14, form Facad structure on surface, described drift region to comprise:
Form grid structure on surface, described drift region, described grid structure comprises: the gate dielectric layer being positioned at surface, described drift region, is positioned at the gate electrode layer on described gate dielectric layer surface and is positioned at the grid oxic horizon on described gate electrode layer surface; P type base is formed in the drift region of described grid structure both sides; N-type emitter is formed in described P type base; N-type emitter electrode is formed in described N-type emitter surface.
In another embodiment of the present invention, described semiconductor device is the integrated insulated gate bipolar transistor of trench gate three-mode.In this embodiment, form Facad structure on surface, described drift region to comprise:
Groove is formed in described drift region; Form grid structure in described flute surfaces, described grid structure comprises: the gate dielectric layer being positioned at described flute surfaces, is positioned at described gate dielectric layer surface, and fills the gate electrode layer of described groove completely and be positioned at the grid oxic horizon on described gate electrode layer surface; P type base is formed in the drift region of described grid structure both sides; N-type emitter is formed in described P type base; N-type emitter electrode is formed in described N-type emitter surface.
Step 6: as shown in figure 15, the side described Semiconductor substrate being deviated to described Facad structure is carried out thinning, and form collector region, described collector region comprises the first doping type collector region and the second doping type collector region that are set up in parallel.Wherein, described first doping type is different from the second doping type.
Because described Semiconductor substrate is different from the doping type of described epitaxial loayer, therefore, undertaken thinning by the side described Semiconductor substrate being deviated to described Facad structure, the collector region comprising the first doping type collector region and the second doping type collector region be set up in parallel can be formed, thus adopt back light carving technology in alternative prior art, form the method for P type collector region and the N-type collector region be set up in parallel, make the manufacture method that the embodiment of the present invention provides, when the integrated insulated gate bipolar transistor of making three-mode, without the need to adopting back light carving technology again, solve the problem that the fragment rate that causes due to back light carving technology is high, improve the rate of finished products of the integrated insulated gate bipolar transistor of three-mode.
For convenience of explanation, in embodiments of the present invention, remember that undressed front described Semiconductor substrate upper surface is Z=0 plane, namely before not forming groove, described Semiconductor substrate is Z=0 plane towards the surface of described Facad structure, described Semiconductor substrate is Z > 0 region towards the side of described Facad structure, the side that described Semiconductor substrate deviates from described Facad structure is Z < 0 region, the degree of depth of described groove is H(H > 0), then the coordinate of described groove floor is-H, namely in described groove, the coordinate at Semiconductor substrate and described epitaxial layer interface place is-H.Continue for described semiconductor device for the integrated insulated gate bipolar transistor of N raceway groove three-mode is described, then the Doped ions of described drift region and described resilient coating is N-type Doped ions.
It should be noted that, when thinning back side is carried out in the side described Semiconductor substrate being deviated to described Facad structure, the technical process such as drift region and Facad structure is formed in described epi-layer surface owing to have passed through, and in these technical processs, the Doped ions between different doping type region can diffuse to form PN junction interface mutually.
In an embodiment of the invention, described epitaxial loayer is not only formed in described groove, and covers the reeded side surface of described Semiconductor substrate tool completely.In this embodiment, if the thickness of described epitaxial loayer is h, the Doped ions at described Semiconductor substrate and described epitaxial layer interface place can diffuse to form PN junction interface mutually, if the distance at Semiconductor substrate and described epitaxial layer interface place is D described in the PN junction interface distance that in described groove, the Doped ions at Semiconductor substrate and described epitaxial layer interface place diffuses to form mutually.If D < 0, then show the dosage that dosage that the Doped ions in described epitaxial loayer spreads is greater than the Doped ions in described Semiconductor substrate and upwards spreads downwards; If D > 0, then show the dosage that dosage that the Doped ions in described epitaxial loayer spreads is less than the Doped ions in described Semiconductor substrate and upwards spreads downwards.Then, in this embodiment, when carrying out thinning back side to described Semiconductor substrate, as long as after ensureing described Semiconductor substrate thinning back side, its position, back side Z=Z
backmeet D-h<Z
back<min (h-H, D), can ensure that the collector region described Semiconductor substrate being deviated to the thinning rear formation in side of described Facad structure comprises the first doping type region and the second doping type region that are set up in parallel, namely form the N-type collector region and P type collector region that are set up in parallel.
In another embodiment, described epitaxial loayer is only formed in described groove, if after attenuated polishing, the thickness of described epitaxial loayer is h1, and the degree of depth of described groove is H, and namely the coordinate of described groove floor position is-H.
In a specific embodiment of this embodiment, described Semiconductor substrate is P type semiconductor substrate, then the Doped ions of described Semiconductor substrate and described drift region (or resilient coating) interface can diffuse to form PN junction interface mutually.If the distance of Semiconductor substrate and described drift region (or resilient coating) interface is D1 described in described PN junction interface distance, if D1 < 0, then show the dosage that dosage that the Doped ions in described drift region (or resilient coating) spreads is greater than the Doped ions in described Semiconductor substrate and upwards spreads downwards; If D1 > 0, then show the dosage that dosage that the Doped ions in described drift region (or resilient coating) spreads is less than the Doped ions in described Semiconductor substrate and upwards spreads downwards.In this embodiment, when carrying out thinning back side to described Semiconductor substrate, as long as after ensureing described Semiconductor substrate thinning back side, its position, back side Z=Z
backmeet D-h<Z
back<h1-H+D1, can ensure to described Semiconductor substrate deviate from the side of described Facad structure thinning after, its back side comprises the first doping type region and the second doping type region that are set up in parallel, namely forms the N-type collector region and P type collector region that are set up in parallel.
In another specific embodiment of this embodiment, described Semiconductor substrate is N type semiconductor substrate, then described epitaxial loayer is P type epitaxial loayer, therefore the Doped ions of described epitaxial loayer and described drift region (or resilient coating) interface can diffuse to form PN junction interface mutually.If the distance of epitaxial loayer and described drift region (or resilient coating) interface is D2 described in described PN junction interface distance, if D2 < 0, then show the dosage that dosage that the Doped ions in described drift region (or resilient coating) spreads is greater than the Doped ions in described epitaxial loayer and upwards spreads downwards; If D2 > 0, then show the dosage that dosage that the Doped ions in described drift region (or resilient coating) spreads is less than the Doped ions in described epitaxial loayer and upwards spreads downwards.In this embodiment, when carrying out thinning back side to described Semiconductor substrate, as long as after ensureing described Semiconductor substrate thinning back side, its position, back side Z=Z
backmeet D-h<Z
back<h1-H+D2, can ensure that the collector region described Semiconductor substrate being deviated to the thinning rear formation in side of described Facad structure comprises the first doping type region and the second doping type region that are set up in parallel, namely form the N-type collector region and P type collector region that are set up in parallel.
The manufacture method that the embodiment of the present invention provides also comprises: step 7: as shown in figure 16, after thinning back side completes, deviate from formation collector region, the side electrode of described Facad structure in described collector region, described collector region electrode is all electrically connected with described P type collector region and N-type collector region.In one particular embodiment of the present invention, described collector region electrode comprises: be formed at the Al metal level that described collector region deviates from described Facad structure one deck; Be formed at the Ti metal level of described Al layer on surface of metal; Be formed at the Ni metal level of described Ti layer on surface of metal; Be formed at described Ni metal layer A g metal level, but the present invention does not limit to this, is determined on a case-by-case basis.
As from the foregoing, the manufacture method that the embodiment of the present invention provides, first in Semiconductor substrate, form groove, then in described groove, epitaxial loayer is formed, because described Semiconductor substrate is different with the doping type of described epitaxial loayer, so after described Semiconductor substrate and epi-layer surface form drift region and Facad structure successively, undertaken thinning by the side described Semiconductor substrate being deviated to described Facad structure, the collector region comprising the first doping type collector region and the second doping type collector region be set up in parallel can be formed, thus the back light carving technology that instead of in prior art when forming the P type collector region and N-type collector region that are set up in parallel, make the manufacture method that the embodiment of the present invention provides, when the integrated insulated gate bipolar transistor of making three-mode, without the need to adopting back light carving technology again, solve the problem that the fragment rate that causes due to back light carving technology is high, improve the rate of finished products of the integrated insulated gate bipolar transistor of three-mode.
And, the manufacture method that the embodiment of the present invention provides, owing to eliminating back light carving technology, thus neither need the equipment introducing back side photoetching, do not need preparation backlight lithography mask version, thus greatly reduce technology difficulty and the cost of manufacture of the integrated insulated gate bipolar transistor of described three-mode yet.
In this specification, various piece adopts the mode of going forward one by one to describe, and what each some importance illustrated is the difference with other parts, between various piece identical similar portion mutually see.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to embodiment illustrated herein, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (10)
1. a manufacturing method of semiconductor device, is characterized in that, comprising:
Semiconductor substrate is provided;
Groove is formed in described Semiconductor substrate;
Form epitaxial loayer at the reeded side surface of described Semiconductor substrate tool, described epitaxial loayer fills described groove completely, and the doping type of described epitaxial loayer is different from the doping type of described Semiconductor substrate;
Form drift region in described epi-layer surface, described drift region covers described Semiconductor substrate and described epitaxial loayer completely;
Facad structure is formed on surface, described drift region;
The side described Semiconductor substrate being deviated to described Facad structure is carried out thinning, and form collector region, described collector region comprises the first doping type collector region and the second doping type collector region that are set up in parallel.
2. manufacture method according to claim 1, is characterized in that, form epitaxial loayer at the reeded side surface of described Semiconductor substrate tool, described epitaxial loayer is filled described groove completely and comprised:
Form epitaxial loayer at the semiconductor substrate surface being only positioned at described groove, described epitaxial loayer fills described groove completely.
3. manufacture method according to claim 2, is characterized in that, the doping type of described epitaxial loayer and the doping type of described drift region identical or different.
4. manufacture method according to claim 1, is characterized in that, form epitaxial loayer at the reeded side surface of described Semiconductor substrate tool, described epitaxial loayer is filled described groove completely and comprised:
Form described epitaxial loayer at the reeded side surface of described Semiconductor substrate tool, described epitaxial loayer fills described groove completely, and covers the reeded side surface of described Semiconductor substrate tool completely.
5. manufacture method according to claim 4, is characterized in that, the doping type of described epitaxial loayer is identical with the doping type of described drift region.
6. the manufacture method according to any one of claim 1-5, is characterized in that, in described epitaxial loayer, the formation process of Doped ions is in-situ doped, ion implantation or diffusion.
7. manufacture method according to claim 6, is characterized in that, described semiconductor device is duck semiconductor device or plane grid-type semiconductor device.
8. manufacture method according to claim 7, is characterized in that, also comprises: form resilient coating in described epi-layer surface, described resilient coating covers described Semiconductor substrate and described epitaxial loayer completely, and identical with the doping type of described drift region.
9. the manufacture method according to claim 7 or 8, is characterized in that, the degree of depth of described groove is the thickness of collector region in described semiconductor device.
10. manufacture method according to claim 1, is characterized in that, described semiconductor device is the integrated insulated gate bipolar transistor of three-mode.
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| CN112928019A (en) * | 2021-01-25 | 2021-06-08 | 杰华特微电子（杭州）有限公司 | Method for manufacturing drift region of semiconductor device |
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Application publication date: 20150603 |