CN104679196B - System and its implementation are resetted when processor-based self-test, exception - Google Patents
System and its implementation are resetted when processor-based self-test, exception Download PDFInfo
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- CN104679196B CN104679196B CN201510103416.0A CN201510103416A CN104679196B CN 104679196 B CN104679196 B CN 104679196B CN 201510103416 A CN201510103416 A CN 201510103416A CN 104679196 B CN104679196 B CN 104679196B
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Abstract
The invention discloses a kind of processor-based self-test, it is abnormal when reset system and its implementation, including：Self-detection module, the first incrementer, register, processor control module and processor other modules, the self-detection module include the second incrementer, comparator and the pre- storage of increment.Through the above way, self-test the present invention is based on processor, it is abnormal when reset system and its implementation, ensure processor normal work, hardware need not be re-powered or replaced in the case of program operation exception, in program operation exception, it can automatically reset, processor is made more to stablize when running, avoids causing to re-power or replace hardware extremely because of environmental factor or oneself factor.
Description
Technical field
The present invention relates to system is resetted when a kind of self-test and exception, more particularly to a kind of processor-based self-test
System and its implementation are resetted when surveying, is abnormal.
Background technology
Core of the processor as electronic product, in operational process there are it is various abnormal the problem of.In some real-time systems
In, if electronic product does not react extremely, economic or unknown losses can be caused.
Processor operating mechanism：Increment is calculated by PC incrementers, and changes the value of PC registers, is read according to this value
Code is handled.Not having testing mechanism, this operating mechanism is detected to PC, when the value of PC registers is not desired value
When, program operation is just not normal.
Present processor is small, and the factors such as humiture, electromagnetic field are influenced easily in by environment, makes it in severe ring
In the case of border or environmental catastrophe, easily abnormal, sensitive for damages is run.It in normal operation, also can be because handling data during operation
The oneself factors such as abnormal, internal hardware exception are not normal there is a situation where running.
Existing various processors, when by environmental factor, if chip temperature is excessively high, processor will run not normal.Or
Because oneself factor generation operation is not normal, entire electronic product is caused not react, it is necessary to re-power or replace hardware.Existing place
It manages in device, program operation is directed toward program address by PC pointers, and the content that processor reads the address carries out operation, but be a lack of examining
Survey mechanism when the value in PC registers is not desired value, when reading error code, will occur operation exception, lead to electricity
Sub- product operation is not normal.
Invention content
The invention mainly solves the technical problem of providing a kind of processor-based self-test, it is abnormal when reset system and
Its implementation has many advantages, such as that unfailing performance is high, reaction speed is fast, while in the application of self-check system of processor and general
There are extensive market prospects on and.
In order to solve the above technical problems, one aspect of the present invention is：
System is resetted when a kind of processor-based self-test, exception are provided, including：Self-detection module, the first increment
Device, register, processor control module and processor other modules, the self-detection module include the second incrementer, comparator
With the pre- storage of increment, second incrementer and the register receive the information that first incrementer is sent, and described the
The information that two incrementers send first incrementer calculates, and the pre- storage of increment is to the meter of second incrementer
It calculates result to be preserved, the comparator obtains and judges that the pre- storage of increment neutralizes the numerical value in the first incrementer, the comparison
Device sends corresponding command signal to the processor control module according to judging result, and the processor control module utilizes institute
State processor other modules completion instruction action.
In a preferred embodiment of the present invention, first incrementer respectively with the processor control module and processing
Other modules of device are connected.
In a preferred embodiment of the present invention, the register respectively with the processor control module and processor its
He is connected module.
The implementation method of system is resetted when a kind of processor-based self-test, exception, step includes：
When the first incrementer update program address for the first time, the program address information of the first incrementer is sent to second
Incrementer；
Second incrementer carries out pre- increment to program address information, obtains the program address to be performed in next step, calculates
Next step program address；
Next step program address is stored in the pre- storage of increment；
Behind second of update program address of the first incrementer, comparator reads the next step journey in the pre- storage of increment simultaneously
Second of program address information in sequence address and the first incrementer；
Comparator compares next step program address and second of program address information；
If the value of next step program address and secondary action information differs, it is judged as program operation exception, concurrently
The number of delivering letters gives processor control module, and processor reset action is completed by processor control module.
The beneficial effects of the invention are as follows：Ensure processor normal work, it is not necessary in the case of program operation exception again
Hardware is powered on or replaced, in program operation exception, can be automatically reset, processor is made more to stablize when running, is avoided because of ring
Border factor or oneself factor cause to re-power or replace hardware extremely.
Description of the drawings
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing, wherein：
Fig. 1 resets system when being the processor-based self-test of the present invention, exception and its implementation one is preferably implemented
The structure diagram of example.
Specific embodiment
The technical solution in the embodiment of the present invention will be clearly and completely described below, it is clear that described implementation
Example is only the part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
All other embodiment that technical staff is obtained without making creative work belongs to the model that the present invention protects
It encloses.
Referring to Fig. 1, the embodiment of the present invention includes：
System is resetted when a kind of processor-based self-test, exception, which is characterized in that including：Self-detection module, first
Incrementer, register, processor control module and processor other modules, the self-detection module include the second incrementer, ratio
Compared with device and the pre- storage of increment, second incrementer and the register receive the information that first incrementer is sent, and institute
It states the information that the second incrementer sends first incrementer to calculate, the pre- storage of increment is to second incrementer
Result of calculation preserved, the comparator obtains and judges that the pre- storage of increment neutralizes the numerical value in the first incrementer, described
Comparator sends corresponding command signal to the processor control module, the processor control module profit according to judging result
With the processor, other modules complete instruction action.
In a preferred embodiment of the present invention, first incrementer respectively with the processor control module and processing
Other modules of device are connected.
In a preferred embodiment of the present invention, the register respectively with the processor control module and processor its
He is connected module.
The implementation method of system is resetted when a kind of processor-based self-test, exception, step includes：
When the first incrementer update program address for the first time, the program address information of the first incrementer is sent to second
Incrementer；
Second incrementer carries out pre- increment to program address information, obtains the program address to be performed in next step, calculates
Next step program address；
Next step program address is stored in the pre- storage of increment；
Behind second of update program address of the first incrementer, comparator reads the next step journey in the pre- storage of increment simultaneously
Second of program address information in sequence address and the first incrementer；
Comparator compares next step program address and second of program address information；
If the value of next step program address and secondary action information differs, it is judged as program operation exception, concurrently
The number of delivering letters gives processor control module, and processor reset action is completed by processor control module.
Self-test the present invention is based on processor, it is abnormal when reset system and the advantageous effect of its implementation and be：Ensure
Processor works normally, it is not necessary to hardware is re-powered or replaced in the case of program operation exception, in program operation exception,
It can automatically reset, processor is made more to stablize when running, avoids causing to re-power extremely because of environmental factor or oneself factor
Or replace hardware.
The foregoing is merely the embodiment of the present invention, are not intended to limit the scope of the invention, every to utilize this hair
The equivalent structure or equivalent flow shift that bright description is made directly or indirectly is used in other relevant technology necks
Domain is included within the scope of the present invention.
Claims (2)
1. reset system when a kind of processor-based self-test, exception, which is characterized in that including：Self-detection module, first increase
Measuring device, register, processor control module and processor other modules, the self-detection module include the second incrementer, compare
Device and the pre- storage of increment,
Second incrementer and the register receive the program address information that first incrementer is sent, and described second
The information that incrementer sends first incrementer calculates, calculating of the pre- storage of increment to second incrementer
As a result it is preserved, wherein, when the first incrementer update program address for the first time, by the program address information of the first incrementer
The second incrementer is sent to, the second incrementer carries out pre- increment to program address information, calculates next step program address, by under
In the one step program address deposit pre- storage of increment, behind second of update program address of the first incrementer, comparator is read simultaneously
Second of program address information in next step program address and the first incrementer in the pre- storage of increment, the comparator obtain
And judging that the pre- storage of increment neutralizes the program address in the first incrementer, the comparator sends corresponding finger according to judging result
Enabling signal, the processor control module is moved using the processor other modules completion instruction to the processor control module
Make, first incrementer is connected respectively with the processor control module and processor other modules, the register point
It is not connected with the processor control module and processor other modules.
2. the implementation method of system is resetted when a kind of processor-based self-test, exception, which is characterized in that step includes：
When the first incrementer update program address for the first time, the program address information of the first incrementer is sent to the second increment
Device；
Second incrementer carries out pre- increment to program address information, calculates next step program address；
Next step program address is stored in the pre- storage of increment；
Behind second of update program address of the first incrementer, comparator with reading the next step program in the pre- storage of increment simultaneously
Second of program address information in location and the first incrementer；
Comparator compares next step program address and second of program address information；
If the value of next step program address and secondary action information differs, it is judged as program operation exception, concurrently delivers letters
Number to processor control module, processor reset action is completed by processor control module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510103416.0A CN104679196B (en) | 2015-03-10 | 2015-03-10 | System and its implementation are resetted when processor-based self-test, exception |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510103416.0A CN104679196B (en) | 2015-03-10 | 2015-03-10 | System and its implementation are resetted when processor-based self-test, exception |
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| CN104679196B true CN104679196B (en) | 2018-07-06 |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6718294B2 (en) * | 2016-04-25 | 2020-07-08 | アズビル株式会社 | Register error detector |
| CN112667060B (en) * | 2020-12-30 | 2021-08-17 | 湖南博匠信息科技有限公司 | External equipment resetting method based on Loongson processor |
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| CN101025700A (en) * | 2006-02-21 | 2007-08-29 | 中兴通讯股份有限公司 | Abnormal reset system protection method and reset protection system |
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| CN104010889A (en) * | 2011-12-22 | 2014-08-27 | 罗伯特·博世有限公司 | Method and device for monitoring voltage supply for vehicle system |
| CN204480170U (en) * | 2015-03-10 | 2015-07-15 | 江苏邦融微电子有限公司 | Based on processor Autonomous test, abnormal time resetting system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004021833A (en) * | 2002-06-19 | 2004-01-22 | Renesas Technology Corp | Semiconductor integrated circuit incorporated with self-test function and system comprising it |
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2015
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| CN1258042A (en) * | 1998-12-22 | 2000-06-28 | 日本电气株式会社 | Monitoring timer system |
| US6212134B1 (en) * | 1998-12-22 | 2001-04-03 | Nec Corporation | Watch dog timer system |
| CN101025700A (en) * | 2006-02-21 | 2007-08-29 | 中兴通讯股份有限公司 | Abnormal reset system protection method and reset protection system |
| CN101470638A (en) * | 2007-12-28 | 2009-07-01 | 上海黄浦船用仪器有限公司 | Method for implementing continuous operation of computer at breakpoint |
| CN101968840A (en) * | 2010-10-26 | 2011-02-09 | 杭州晟元芯片技术有限公司 | Voltage detection and frequency detection-based chip anti-attack method |
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