CN104658603A - Optimal flash memory write operation time configuration method and flash memory write operation speed optimizing method - Google Patents
Optimal flash memory write operation time configuration method and flash memory write operation speed optimizing method Download PDFInfo
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- CN104658603A CN104658603A CN201510091617.3A CN201510091617A CN104658603A CN 104658603 A CN104658603 A CN 104658603A CN 201510091617 A CN201510091617 A CN 201510091617A CN 104658603 A CN104658603 A CN 104658603A
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Abstract
The invention discloses an optimal flash memory write operation time configuration method which comprises the following steps: I, initializing a time parameter, and performing write operation on a storage array within the time parameter; II, performing read operation on the storage array, judging whether the write operation within the time parameter is correct or not trough the read operation, if the write operation is correct, performing a step III, if the write operation is not correct, increasing one time quantum for the time parameter, thereby obtaining a present time parameter, and repeating the step I and the step II until the write operation is correct; III, configuring a register for the present time parameter, and writing the present time parameter as the optimal time into a specific storage area. The invention further discloses a flash memory write operation speed optimizing method. By adopting the optimal flash memory write operation time configuration method and the flash memory write operation speed optimizing method, the speed and performance of write operation of a flash memory can be improved.
Description
Technical field
The present invention relates to flash memory technology field, particularly relate to a kind of flash memory write optimum operation time compound method and flash memory write operating speed optimization method.
Background technology
The advantages such as flash memory is convenient with it, storage density is high, good reliability become the focus studied in non-volatility memorizer.Since coming out from first flash memory products 1980s, along with the development of technology and each electronic product are to the demand stored, flash memory is widely used in mobile phone, notebook, in the mobile and communication apparatus such as palm PC and u dish, flash memory is a kind of nonvolatile storer, its operation principles is that the critical voltage by changing transistor or storage unit controls the switch of gate pole passage to reach the object storing data, storage data in memory can not be disappeared because of power interruption, and flash memory is electric erasable and a kind of special construction of programmable ROM (read-only memory).Nowadays flash memory has occupied most of market share of non-volatile semiconductor memory, becomes non-volatile semiconductor memory with fastest developing speed.
But in some application (as ink-cases of printers chip) of flash memory, the capacity of flash memory is very little, but to flash memory write (write) rate request high (close to ferroelectric).The speed of current flash then due to need to consider high/low temperature and various capacity etc. factor, these factors are unfavorable for the application of flash memory high speed write.
Summary of the invention
The object of the invention is to, a kind of flash memory write optimum operation time compound method and flash memory write operating speed optimization method are provided, speed and the performance of flash memory write operation can be improved.
For solving the problems of the technologies described above, the invention provides a kind of flash memory write optimum operation time compound method, comprising:
Step one: initialization one time parameter, carries out write operation to a storage array in described time parameter;
Step 2: carry out read operation to described storage array, by described read operation, judges that in described time parameter, whether described write operation is correct; If described write operation is correct, then carry out step 3; If described write operation is incorrect, then described time parameter is increased by a time quantum, obtain current time parameter, and current described time parameter is substituted previous described time parameter, current described time parameter is used to re-start step one and step 2, till described write operation is correct;
Step 3: be current described time parameter configuration register, and current described time parameter is write a particular memory region as optimal time.
Further, in described flash memory write optimum operation time compound method, described storage array is the whole storage area of described flash memory.
Further, in described flash memory write optimum operation time compound method, described storage array is the territory, partial memory area of described flash memory.
According to another side of the present invention, a kind of flash memory write operating speed optimization method is also provided, comprises:
Trigger one by a trigger condition and write training pattern;
Described training pattern of writing obtains described optimal time according to flash memory write optimum operation time compound method as above;
Write training pattern described in exiting, enter normal mode.
Further, in described flash memory write operating speed optimization method, described trigger condition comprises temperature changing speed more than a specific speed.
Further, in described flash memory write operating speed optimization method, described in write the reference current that the reference current of read operation under training pattern is less than read operation under described normal mode.
Further, in described flash memory write operating speed optimization method, described storage array is the whole storage area of described flash memory.
Further, in described flash memory write operating speed optimization method, described storage array is the territory, partial memory area of described flash memory.
Further, in described flash memory write operating speed optimization method, in described normal mode, as needs carry out fast write operation, then described optimal time is used to carry out fast write operation.
Further, in described flash memory write operating speed optimization method, trigger one in the free time of described flash memory by described trigger condition and write training pattern.
Compared with prior art, flash memory write optimum operation time compound method provided by the invention and flash memory write operating speed optimization method have the following advantages:
In flash memory write optimum operation time compound method provided by the invention and flash memory write operating speed optimization method, carry out step one: initialization one time parameter, in described time parameter, write operation is carried out to a storage array; Carry out step 2: read operation is carried out to described storage array, by described read operation, judge that in described time parameter, whether described write operation is correct; If described write operation is correct, then carry out step 3; If described write operation is incorrect, then described time parameter is increased by a time quantum, obtain current time parameter, and current described time parameter is substituted previous described time parameter, current described time parameter is used to re-start step one and step 2, till described write operation is correct; Step one and step 2 is carried out by circulation, progressively increasing the time writing (write) writes scanning to described storage array, then judged by read operation, finally obtain optimal time, and particular memory region relevant configuration write in flash memory, and be configured in corresponding register.When needs carry out fast write operation, described optimal time be can directly call, thus speed and the performance of flash memory write operation improved.
Accompanying drawing explanation
Fig. 1 is the process flow diagram of flash memory write optimum operation time compound method in one embodiment of the invention;
Fig. 2 is the process flow diagram of flash memory write operating speed optimization method in one embodiment of the invention.
Embodiment
Below in conjunction with schematic diagram, flash memory write optimum operation time compound method of the present invention and flash memory write operating speed optimization method are described in more detail, which show the preferred embodiments of the present invention, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, a large amount of implementation detail must be made to realize the specific objective of developer, such as, according to regarding system or the restriction about business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, more specifically the present invention is described by way of example with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, provides a kind of flash memory write optimum operation time compound method, comprising: step one: initialization one time parameter, in described time parameter, carry out write operation to a storage array; Step 2: carry out read operation to described storage array, by described read operation, judges that in described time parameter, whether described write operation is correct; If described write operation is correct, then carry out step 3; If described write operation is incorrect, then described time parameter is increased by a time quantum, obtain current time parameter, and current described time parameter is substituted previous described time parameter, current described time parameter is used to re-start step one and step 2, till described write operation is correct; Step 3: be current described time parameter configuration register, and current described time parameter is write a particular memory region as optimal time.Step one and step 2 is carried out by circulation, progressively increasing the time writing (write) writes scanning to described storage array, then judged by read operation, finally obtain optimal time, and particular memory region relevant configuration write in flash memory, and be configured in corresponding register.When needs carry out fast write operation, described optimal time be can directly call, thus speed and the performance of flash memory write operation improved.
Below please refer to Fig. 1-Fig. 2 to illustrate flash memory write optimum operation time compound method and the flash memory write operating speed optimization method of the present embodiment, Fig. 1 is the process flow diagram of flash memory write optimum operation time compound method in one embodiment of the invention; Fig. 2 is the process flow diagram of flash memory write operating speed optimization method in one embodiment of the invention.
As shown in Figure 1, described flash memory write optimum operation time compound method, comprises step one to step 3:
First carry out step one S11: initialization one time parameter, in described time parameter, write operation is carried out to a storage array.Initialized time parameter is little as much as possible, and to ensure that optimal time is minimum available times, such as described initialized time parameter is 1ms, 2ms etc., in the present embodiment, and described initialized time parameter t
0for 1ms.Wherein, described storage array is the whole storage area of described flash memory, or described storage array is the territory, partial memory area of described flash memory, and the region making the write operation in step one S11 be only limitted to system reserved is carried out.
Then step 2 S12 is carried out: (read) operation is read to described storage array, by described read operation, judges that in described time parameter, whether described write operation is correct; If described write operation is correct, then carry out step 3; If described write operation is incorrect, then described time parameter is increased by a time quantum, obtain current time parameter, and current described time parameter is substituted previous described time parameter, current described time parameter is used to re-start step one and step 2, till described write operation is correct.
In the present embodiment, described time parameter t is judged
0whether interior described write operation is correct; If described write operation is correct, then carry out step 3; If described write operation is incorrect, then by described time parameter t
0increase by a time quantum Δ t, wherein said time quantum Δ t is little as much as possible, to ensure that optimal time is minimum available times, such as described time quantum Δ t is 1ms, 2ms etc., in the present embodiment, described time quantum Δ t is 1ms, then described current time parameter t
1=t
0+ Δ t=2ms, and by current described time parameter t
1substitute previous described time parameter t
0, use current described time parameter t
1re-start step one S11, at described current described time parameter t
1in write operation is carried out to described storage array, and carry out step 2 S12, judge described time parameter t
1whether interior described write operation is correct.
Judge described time parameter t
1whether interior described write operation is correct, if described write operation is correct, then carries out step 3; If described write operation is incorrect, then by described time parameter t
, 1increase by a time quantum Δ t, then described current time parameter t
2=t
1+ Δ t=3ms, and by current described time parameter t
2substitute previous described time parameter t
1, use current described time parameter t
2re-start step one S11, at described current described time parameter t
2in write operation is carried out to described storage array, and carry out step 2 S12, judge described time parameter t
2whether interior described write operation is correct.Circulation like this, till described write operation is correct.
Carry out step 3 S13 afterwards: be current described time parameter configuration register, and current described time parameter is write a particular memory region as optimal time.
Carry out step one and step 2 by circulation, progressively increasing the time writing (write) writes scanning to described storage array, is then judged by read operation, finally obtains optimal time.
Described flash memory write optimum operation time compound method can be applied to flash memory write operating speed optimization method, and as shown in Figure 2, described flash memory write operating speed optimization method comprises:
Carry out step S1, trigger one by a trigger condition and write training pattern, described trigger condition comprises temperature changing speed more than specific speed etc.Preferably, trigger one in the free time of described flash memory by described trigger condition and write training pattern.
Then carry out S2, described in write training pattern and obtain described optimal time according to flash memory write optimum operation time compound method as above.Preferably, the described reference current write the reference current of read operation under training pattern and be less than read operation under described normal mode, the standard writing read operation under training pattern described in making, higher than the standard of read operation under described normal mode, is conducive to the carrying out ensureing that read operation can be correct under described optimal time.
Carry out S3 afterwards, described in exiting, write training pattern, enter normal mode.In described normal mode, as needs carry out fast write operation, described optimal time be can directly call, thus speed and the performance of flash memory write operation improved.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. a flash memory write optimum operation time compound method, is characterized in that, comprising:
Step one: initialization one time parameter, carries out write operation to a storage array in described time parameter;
Step 2: carry out read operation to described storage array, by described read operation, judges that in described time parameter, whether described write operation is correct; If described write operation is correct, then carry out step 3; If described write operation is incorrect, then described time parameter is increased by a time quantum, obtain current time parameter, and current described time parameter is substituted previous described time parameter, current described time parameter is used to re-start step one and step 2, till described write operation is correct;
Step 3: be current described time parameter configuration register, and current described time parameter is write a particular memory region as optimal time.
2. flash memory write optimum operation time compound method as claimed in claim 1, it is characterized in that, described storage array is the whole storage area of described flash memory.
3. flash memory write optimum operation time compound method as claimed in claim 1, it is characterized in that, described storage array is the territory, partial memory area of described flash memory.
4. a flash memory write operating speed optimization method, is characterized in that, comprising:
Trigger one by a trigger condition and write training pattern;
Described training pattern of writing obtains described optimal time according to flash memory write optimum operation time compound method as claimed in claim 1;
Write training pattern described in exiting, enter normal mode.
5. flash memory write operating speed optimization method as claimed in claim 4, it is characterized in that, described trigger condition comprises temperature changing speed more than a specific speed.
6. flash memory write operating speed optimization method as claimed in claim 4, is characterized in that, described in write the reference current that the reference current of read operation under training pattern is less than read operation under described normal mode.
7. flash memory write operating speed optimization method as claimed in claim 4, it is characterized in that, described storage array is the whole storage area of described flash memory.
8. flash memory write operating speed optimization method as claimed in claim 4, it is characterized in that, described storage array is the territory, partial memory area of described flash memory.
9. flash memory write operating speed optimization method as claimed in claim 4, is characterized in that, in described normal mode, as needs carry out fast write operation, then use described optimal time to carry out fast write operation.
10. flash memory write operating speed optimization method as claimed in claim 4, is characterized in that, triggers one write training pattern in the free time of described flash memory by described trigger condition.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070233940A1 (en) * | 2006-04-03 | 2007-10-04 | Quanta Storage Inc. | Method for updating data in flash memory |
| US20080037348A1 (en) * | 2005-03-24 | 2008-02-14 | Hsieh Pingfu | Method for adjusting programming/erasing time in memory system |
| CN102640227A (en) * | 2009-09-23 | 2012-08-15 | 国家数字研究中心有限公司 | A flash memory device and control method |
| CN103839596A (en) * | 2014-03-17 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Optimal method for correcting embedded memory |
-
2015
- 2015-02-28 CN CN201510091617.3A patent/CN104658603A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080037348A1 (en) * | 2005-03-24 | 2008-02-14 | Hsieh Pingfu | Method for adjusting programming/erasing time in memory system |
| US20070233940A1 (en) * | 2006-04-03 | 2007-10-04 | Quanta Storage Inc. | Method for updating data in flash memory |
| CN102640227A (en) * | 2009-09-23 | 2012-08-15 | 国家数字研究中心有限公司 | A flash memory device and control method |
| CN103839596A (en) * | 2014-03-17 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Optimal method for correcting embedded memory |
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