CN103093831A - Built-in self trim for non-volatile memory reference current - Google Patents
Built-in self trim for non-volatile memory reference current Download PDFInfo
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- CN103093831A CN103093831A CN2012104262502A CN201210426250A CN103093831A CN 103093831 A CN103093831 A CN 103093831A CN 2012104262502 A CN2012104262502 A CN 2012104262502A CN 201210426250 A CN201210426250 A CN 201210426250A CN 103093831 A CN103093831 A CN 103093831A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
- G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0409—Online test
Abstract
A non-volatile memory built-in self-trim mechanism is provided by which product reliability can be improved by minimizing drift of reference current used for accessing the non-volatile memory and for performing initial trimming of the reference current. Embodiments perform these tasks by using an analog-to-digital converter to provide a digital representation of the reference current (Iref) and then comparing that digital representation to a stored target range value for Iref and then adjusting a source of Iref accordingly. For a reference current generated by a NVM reference bitcell, program or erase pulses are applied to the reference cell as part of the trimming procedure. For a reference current generated by a bandgap-based circuit, the comparison results can be used to adjust the reference current circuit. In addition, environmental factors, such as temperature, can be used to adjust the measured value for the reference current or the target range value.
Description
Technical field
Present disclosure relate generally to nonvolatile memory, and more particularly, relate to the built-in self trim mechanism of the reference current that uses in the access nonvolatile memory.
Background technology
Nonvolatile memory relies on usually that reference current (Iref) distinguishes cell stores be value 0(for example, less than Iref) for example still be worth 1(, greater than Iref).In order to generate Iref, the design of many nonvolatile memories is used as reference cell with the bit location (bitcell) of nonvolatile memory.In order to ensure the Performance And Reliability of nonvolatile memory array, reference cell should be stable, and not significantly drift in time.But as many other semiconductor devices, reference cell can run into environmental impact, and data keep wrong and read the interference mistake.
Although reference cell is finely tuned by the manufacturer of nonvolatile memory when beginning usually, there is no to be used at the scene or to be adjusted or again finely tuned by the client who nonvolatile memory is incorporated into subsequent product the mechanism of reference cell.In addition, the initial fine setting of reference cell is the time-consuming process that uses the equipment outside outside nonvolatile memory or encapsulation that incorporated nonvolatile memory into, and is therefore expensive with regard to resource and turnout reduction.Therefore, desirable be incorporate built-in self trim mechanism the encapsulation of nonvolatile memory within.In addition, desirable is that so built-in self trim mechanism can be used to make datum drift at the scene to minimize, and helps the initial fine setting of reference cell.
Description of drawings
By the reference accompanying drawing, the present invention may be better understood for those skilled in the art, and know the numerous purpose of the present invention, feature and advantage.
Fig. 1 is the simplified block diagram that can be used for the nonvolatile memory of embodiments of the invention.
Fig. 2 is according to comprising control-grid voltage based on the benchmark bit location of the embodiment of the reference circuit of the benchmark of floating boom formula bit location-drain current figure.
Fig. 3 illustrates according to an embodiment of the invention and the simplified block diagram that comprises based on the example of the related member of the reference circuit of the benchmark of floating boom formula bit location.
Fig. 4 illustrates the simplified flow chart of process of built-in self trim operation of embodiments of the invention that has merged the Iref circuit of floating boom formula bit location for execution.
Fig. 5 illustrates simplified block diagram with comprise based on the example of the reference circuit of the benchmark of band gap related member of the present invention according to embodiment.
Fig. 6 illustrates for execution to combine simplified flow chart based on the process of the built-in self trim operation of the embodiments of the invention of the Iref generator of band gap.
Indicate identical item with identical reference symbol in different accompanying drawings, except as otherwise noted.Accompanying drawing might not be drawn in proportion.
Embodiment
Herein disclosed is a kind of built-in self trim mechanism of nonvolatile memory, by this mechanism, the reliability of product can minimize to improve by the drift that is used in the reference current of accessing nonvolatile memory.Departed from the state of its factory set if reference current is interfered, the embodiment of built-in self trim mechanism can also refresh this reference current.The embodiment of built-in self trim mechanism can also be used to carry out the initial fine setting of reference current.The embodiment of built-in self trim mechanism carries out these tasks by following operation: the numeral that reference current (Iref) is provided with analog to digital converter, then the desired value of this numeral with the Iref that stores compared, and then correspondingly adjust the Iref source.For the reference current that is generated by the reference cell of nonvolatile memory, programming or erasing pulse can be applied to reference cell as the part of trim process.For by the reference current based on the circuit evolving of band gap, comparative result can be used for adjusting reference current circuit.In addition, environmental factor (for example, temperature) can be used to adjust one or more in the desired value of the measured value of reference current or reference current.
Nonvolatile memory is read the data that are stored in nonvolatile memory (NVM) array with reference current.Reference current be used to district office storage 0 and store 1.If the value of reference current changes along with the process in the life-span of NVM device, this can cause device to become unavailable, because data value can't correctly be read.Reference current is affected by the environmental factor such as temperature and voltage also, and perhaps curent change can impel the reference current drift.In addition, power cycle and extreme operating conditions can be disturbed the value of reference current equally.Accidental cause (for example, the reprogramming of reference cell) and uncommon natural cause (for example, cosmic radiation) can affect reference current equally.
In order to assist in ensuring that the lasting availability of NVM device in the whole process in the life-span of NVM device, desirable being to provide can be in order to the initial given value that reference current is adjusted into reference current or the mechanism of its acceptable scope.This adjustment or fine setting can be by comparing the currency of reference current and the calibrated initial value of reference current to carry out, and make as required suitable adjustment.
Fig. 1 is the simplified block diagram that can be used for the nonvolatile memory 101 of embodiments of the invention.NVM 101 comprises NVM cellular array 103, and is used for the circuit of accessed array 103.Nvm array 103 comprises 4 NVM unit 105,107,109 and 111, and these 4 NVM unit are exemplarily illustrated as floating boom formula flash cell.Should recognize, nvm array 103 can comprise the NVM unit (for example, nanocrystal, gate-division type flash memory and based on the storer of nitride) of the bit location that separately adds or other types.
OK/gate voltage control circuit 117 is provided for and generates the gate voltage (Vg) that is provided for row decoder 115 and Memory Controller 113.Row decoder 115 provides gate voltage optionally for during storage operation word line WL0 and WL1.The grid of the storage unit of word line and nvm array 103 couples.NVM 101 also comprises having and the bit line BL0 of the unit that is used for reading nvm array 103 and column decoder and sensor amplifier (CD/SA) circuit 121 of the sensor amplifier that BL1 couples.During storage operation, drain voltage control circuit 125 is given bit line BL0 and BL1 supply drain voltage (Vdrain).In addition, reference circuit 123 is returned the variable reference current (Iref) of benchmark sensor amplifier supply at the CD/SA circuit 121 that is used for reading/to sense bit location 105,107,109 and 111 logic state.In an example of NVM technology, the sensor amplifier of bit location output is that logic state 0(is non-conduction at the drain current of bit location during less than reference current), and be logic state 1(conducting at the bit location drain current during higher than reference current).The data of reading the unit of CD/SA circuit 121 outputs from data line.
Reference circuit 123 can be taked according to an embodiment of the invention for finely tuning the various forms of configuration.In one embodiment, reference circuit 123 comprises the benchmark based on floating boom formula bit location.Can be bit location in nvm array 103 based on the benchmark of floating boom formula bit location, but be protected in order to avoid be programmed.Reference cell in nvm array will have the characteristic identical with other bit locations in nvm array, and will be subjected to the environmental baseline identical with other bit locations in nvm array.In another embodiment of the NVM 101 that can be used for embodiments of the invention, reference circuit 123 comprises the benchmark based on band gap, but this reference circuit 123 is for the reference current circuit of simulation based on the digitizing fine setting of the output current behavior of the benchmark of bit location.Carry out adjusting control register based on the fine setting of the benchmark of band gap.Advantage based on the benchmark of band gap is: the operation drift of this benchmark is usually less than the operation drift based on the benchmark of floating boom formula bit location.
Memory Controller 113 controlling read, write with test operation during the storage operation of nvm array 103.Memory Controller 113 is controlled 127 with row/gate voltage control 117, reference circuit 123, drain voltage control 125 and source and is coupled, in order to control the voltage and current value that is offered nvm array 103 by these circuit during storage and test operation.Memory Controller 113 also provides control information for the operation of row decoder 115 and CD/SA 121 during storage and test operation.In this type of operating period, Memory Controller 113 comprises address wire, data line and the control line be used to the address, data and the control information that receive self processor or external test 150.Processor 150 can be positioned on the integrated circuit identical from NVM 101 or be positioned on different with it integrated circuit.
Fig. 2 is according to combining based on the benchmark bit location of the embodiment of the reference circuit 123 of the benchmark of floating boom formula bit location, having wiped bit location and the control-grid voltage of program bit unit-drain current figure.When calibration, the read-out voltage on the control gate of benchmark bit location (Vread) causes the reference current (Iref) in drain electrode place of benchmark bit location (Id).As discussed above, this calibrated reference current is used to determine the state (for example, programme or wipe) of the bit location in nvm array 103.If the benchmark bit location is as curve 230(" low ") and curve 240(" height ") between operate within shown predetermined acceptable performance range, the Iref that produces under concrete Vread is enough to access the bit location in nvm array 103.This opereating specification of Iref is shown in the Id between Iref_Low and Iref_High.This will keep the read margin of the bitcell current from the reference current to the nvm array.In Fig. 2, curve 210 with have greater than the drain current Id1 of the Iref_high of Vread to wipe bit location related.Curve 220 is related with the program bit unit that has less than the drain current Id0 of the Iref_Low of Vread.If Iref is outside opereating specification, the benchmark bit location should be made the bit location in nvm array 103 can continue accessed by fine setting.
For the benchmark based on floating boom formula bit location, if Iref is down to below Iref_Low, the benchmark bit location should pass through erase cycles.More than if Iref rises to Iref_High, the benchmark bit location should pass through program cycles.Within these fine setting operations can cause the operating parameter of the benchmark based on floating boom formula bit location shown in resetting to.
For the benchmark based on band gap, target be make Iref remain in the similar operating parameter of those operating parameters that shows by the benchmark based on floating boom formula bit location within.Thereby, if Iref is down to below Iref_Low, adjust by the value of adjusting the Iref control register with the digital trimming process based on the benchmark of band gap, so that Iref rises on Iref_Low.Similarly, if more than Iref rises to Iref_High, adjust by the value of adjusting the Iref control register with the digital trimming process based on the benchmark of band gap, so that Iref drops under Iref_High.
Fig. 3 illustrates according to an embodiment of the invention and the simplified block diagram that comprises based on the example of the related member of the reference circuit 123 of the benchmark of floating boom formula bit location.Reference generator 310 based on bit location comprises that one or more is based on the reference cell of floating boom formula bit location.As discussed above, these reference cells can be merged in nvm array 103, guarantee that thus reference cell is exposed under the environmental baseline and initial treatment condition identical with other bit locations in nvm array.Receive input from the program/erase controller 320 of NVM based on the reference generator 310 of bit location, the program/erase controller 320 of this NVM provides programming or erasing pulse to reference cell, if this reference cell needs fine setting.The program/erase controller 320 of NVM can be the part of Memory Controller 113.
Environmental characteristics (for example, temperature) can affect reference cell 310 in nvm array 103 and the behavior of bit location.Therefore, embodiments of the invention can provide environmental sensor, available skew is posted a letter to the desired value 350 of the result that is generated by ADC 330 and the Iref that is stored.As shown in Figure 3, temperature sensor 370 couples with the desired value register 350 of ADC 330 and Iref, in order to be provided for making the data of these value skews.
Fig. 4 illustrates the simplified flow chart of process of built-in self trim operation of embodiments of the invention that combines the Iref circuit of floating boom formula bit location for execution.At first, the measurement pattern of Iref can be set up or be triggered (410).For example, when the measurement pattern of Iref can be restarted in the system that combines NVM101, perhaps when receiving outside or inside (for example, periodic or (otherwise) trigger) order by Lookup protocol.In case the measurement pattern of Iref is activated, the value of Iref just can be measured and be stored (420).As discussed above, the measurement of the value of Iref can be carried out by ADC, and then this ADC is stored in the value of digital conversion in register.
Then, make Iref whether in determine (430) of (for example, between Iref_Low and Iref_High) within the preset range of desired value.As mentioned above, in one embodiment, this determines and can be undertaken by for example comparer.For example, by comparing, Iref is lower than predetermined Iref_Low and/or higher than predetermined Iref_High.If Iref is in the preset range of desired value, built-in self trim process finishes.If Iref is in outside target zone, make Iref whether less than determine (440) of the lower limit of target zone.If Iref is less than the lower limit of target zone, erasing pulse is applied in reference cell (460).If Iref is greater than the upper limit of target zone, programming pulse is applied in reference cell (450).As discussed above, in one embodiment, whether 360 execution of fine setting logical block will programme or erasing pulse puts on determining of reference cell.In case programming or erasing pulse are provided for reference cell, again carried out from the measurement of the Iref that generates of reference cell, within determining whether reference cell is in acceptable operating parameter now.
Fig. 5 illustrates according to an embodiment of the invention and the simplified block diagram that comprises based on the example of the related member of the reference circuit 123 of the benchmark of band gap.But the reference current circuit that comprises one or more digitizing fine setting based on the Iref generator 510 of band gap is as discussed above.Can receive input from Iref control register 520 based on the Iref generator 510 of band gap, this Iref control register 520 provides the information of being used by the Iref generator based on band gap to generate reference current.Iref control register 520 can be taked various ways, and can be the part of Memory Controller 113 for example.
The reference current that generates is provided for analog to digital converter (ADC) 530 based on the Iref generator 510 of band gap.ADC 530 is converted to Iref the digital value that can be stored in register and be provided for comparer 540.Comparer 540 compares the digital value of Iref and the desired value 550 that is stored in the Iref in register independently.If relatively being in preset range between the desired value of the digital value of Iref and Iref do not finely tuned the Iref generator based on band gap.Another aspect if relatively surpass predetermined scope between the desired value of the digital value of Iref and Iref, is finely tuned logical block 560 and is provided adjusted value to Iref control register 520.This adjusted value will change the reference current that is generated by the Iref generator based on band gap.
As discussed above, environmental characteristics can affect the behavior based on the Iref generator of band gap equally.Therefore, embodiments of the invention can provide environmental sensor, available skew is posted a letter to the desired value 550 of the result that is generated by ADC 530 and the Iref that is stored.As shown in Figure 5, temperature sensor 570 couples with the desired value register 550 of ADC 530 and Iref, in order to be provided for making the data of these value skews.
Be to be understood that, embodiments of the invention are not limited to the environmental characteristics by temperature sensor measurement, but can comprise equally in the value that affects ADC, storage register etc. one or more reference current or the sensor of the environmental baseline of the other types of adjustment.
Fig. 6 illustrates the simplified flow chart of process that is used for carrying out built-in self trim operation that combines based on the embodiments of the invention of the Iref generator of band gap.Shown process is similar to the above process of discussing about Fig. 4.At first, the measurement pattern of Iref can be set up (610).In case the measurement pattern of Iref is activated, the value of the Iref that generates can be measured and be stored (620).
Then, make about Iref whether being in determine (630) within the preset range of desired value.As mentioned above, in one embodiment, this determines and can be undertaken by comparer.Within if Iref is in the preset range of desired value, built-in self trim process finishes.If Iref is in outside target zone, make about Iref whether less than determine (640) of the lower limit of target zone.If Iref is less than the lower limit of target zone, band-gap circuit is finely tuned to increase Iref(660) (for example, by adjusting the reference current control register).As discussed above, this can provide adjusted value to carry out by for example giving Iref control register 520.If Iref is greater than the upper limit of target zone, band-gap circuit is finely tuned to reduce Iref(650) (for example, by adjusting the reference current control register).As discussed above, in one embodiment, it is increase or reduce determining of Iref that fine setting logical block 560 is carried out.In case the Iref generator based on band gap is adjusted, the measurement of the Iref that generates is carried out again with within determining whether reference current is in the object run scope now.
So far should recognize, this paper provides a kind of method, the method comprises: the digital value that the reference current of nonvolatile memory is converted to the NVM reference current, the digital value of NVM reference current and the limit of target range are compared, and if the digital value of NVM reference current is in outside the scope of desired value, the generator of adjusting the NVM reference current to be to produce the NVM reference current of being adjusted, and makes within the NVM reference current value of adjusting is in the scope of desired value.The NVM reference current is converted to the analog to digital converter that the digital value of NVM reference current can couple by the generator with the NVM reference current to be carried out.Change, compare and adjust and carried out by the member of the SOC (system on a chip) that comprises NVM.
Aspect of above embodiment, the generator of adjusting the NVM reference current comprises to produce the NVM reference current of being adjusted: if the digital value of NVM reference current is less than the scope of desired value, erasing pulse is put on the generator of NVM reference current, if and the digital value of NVM reference current is greater than the scope of desired value, with the generator of program pulse application in the NVM reference current.The embodiment of this aspect is included in the floating boom formula benchmark bit location in the generator of NVM reference current.In yet another aspect, the generator of NVM reference current with comprise that the nvm array of a plurality of floating boom formula bit locations couples, and floating boom formula benchmark bit location is the parts of these a plurality of floating boom formula bit locations.
Aspect another of above embodiment, the generator of adjusting the NVM reference current in order to produce the NVM reference current of adjusting comprises: if the digital value of NVM reference current is less than the scope of desired value, finely tune band-gap circuit to increase the NVM reference current, if and the digital value of NVM reference current is finely tuned band-gap circuit to reduce the NVM reference current greater than the scope of desired value.The embodiment of this respect is included in the circuit based on band gap in the generator of NVM reference current.In one aspect of the method, the fine setting band-gap circuit comprises the value of adjusting the reference current control register.
Another aspect of above embodiment comprises the digital value of adjusting the NVM reference current in response to the temperature value that records and the scope of desired value.
an alternative embodiment of the invention provides a kind of system, comprise: nonvolatile memory array, configuration is used for generating the NVM reference current generator with the NVM reference current that visits nvm array, couple and configure for the NVM reference current being converted to the ADC of the digital value of NVM reference current with NVM reference current generator, couple and configure with ADC for digital value and desired value comparer relatively with the NVM reference current, and couple and configure the fine setting logical block that the NVM reference current of being adjusted is provided when providing outside control signal is in desired value with the digital value at the NVM reference current scope for the generator to the NVM reference current with comparer.Within the digital value of the NVM reference current of adjusting related with the NVM reference current of adjusting is in the scope of desired value.
one aspect of the present invention also comprises the program/erase controller of NVM, the program/erase controller of this NVM couples with the generator of fine setting logical block and NVM reference current, and be arranged to: the control signal that receives the self trim logical block, if control signal comprises that the digital value of NVM reference current is lower than the mark of the lower limit of the scope of desired value, provide erasing pulse in response to this control signal to the generator of NVM reference current, if and control signal comprises that the digital value of NVM reference current is greater than the mark of the upper limit of the scope of desired value, provide programming pulse in response to this control signal to the generator of NVM reference current.For this respect, the generator of NVM reference current comprises floating boom formula benchmark bit location.Another aspect, nvm array comprise floating boom formula benchmark bit location.Another aspect comprises one or more register of the upper limit of the scope of the lower limit of the scope that couples and store desired value with comparer and desired value.
Another aspect comprise with ADC and register in one or more couple and configure for providing the temperature sensor of temperature data to one or more of ADC and register.ADC also is arranged to the digital value of adjusting when needed the NVM reference current in response to temperature data, and register also is arranged to when needed the upper limit of coming the scope of the lower limit of scope of adjustment aim value and desired value in response to temperature data.
Another aspect of above embodiment comprises with ADC and comparer and couples register for the digital value of storage NVM reference current.another aspect of above embodiment also comprises the control register that couples with the generator of finely tuning logical block and NVM reference current, this control register is arranged to the storing value in response to the control signal of coming the self trim logical block, and the NVM reference generator also comprises band-gap circuit, this band-gap circuit is finely tuned in response to being stored in the value in control register, to increase the NVM reference current during less than the scope of desired value in the digital value of NVM reference current, and this band-gap circuit is finely tuned to reduce the NVM reference current during greater than the scope of desired value in the digital value of NVM reference current.
In yet another aspect, the generator of NVM reference current be arranged in nvm array near, make both to be exposed under basically similar environmental baseline.In yet another aspect, ADC also is arranged to the conversion of the carrying out the digital value from the NVM reference current to the NVM reference current in response to receiving the order that starts described conversion.In yet another aspect, ADC also is arranged in response to the power that makes systemic circulation and carries out the digital value that the NVM reference current is converted to the NVM reference current.
Term " conclusive evidence " or " setting " and " negating " (perhaps " cancelling conclusive evidence " or " removing ") are used respectively when relating to the state that causes signal, mode bit or similar device to enter its logical truth or logical falsehood in this article.If the state of logical truth is logic level 1, the state of logical falsehood is logic level 0.And if the state of logical truth is logic level 0, the state of logical falsehood is logic level 1.
Realize that device major part of the present invention comprises electronic component and the circuit that those skilled in the art are known because be used for, so the details of circuit will no longer more explain necessary details except described above being considered to, so that the understanding of key concept of the present invention and understand and avoid confusion or broken away from instruction of the present invention.
Some embodiment in above-described embodiment can realize with various information handling system at where applicable.For example, although exemplary information processing framework has been described in Fig. 1 and discussion thereof, this exemplary framework provides just to provide the benchmark of use in various aspects of the present invention are discussed.Certainly, about the description of framework for for the purpose of discussing and simplified, and a kind of in its many dissimilar applicable framework that just can use in conjunction with the present invention.Those skilled in the art should recognize, the boundary between logical block is just illustrative, and interchangeable embodiment can merge logical block or circuit component or interchangeable Function Decomposition is forced at various logic piece or circuit component.
Accordingly, it should be understood that the shown framework of this paper is illustrative, and in fact, be used for realizing that many other frameworks of identical function can both be implemented.Abstractively, but meaning still clearly, but any member layout of solid line identical function is all effectively " association ", makes desired function be achieved.Therefore no matter, in conjunction with can both be counted as each other " association " with any two members of realizing specific function, make desired function be achieved, be what framework or intermediate member.Similarly, related any two members can be counted as each other " what connect in operation " or " coupling " equally in operation like this, to realize desired function.
In addition, and for example, in one embodiment, the element of shown NVM 101 is to be positioned at circuit on single integrated circuit or that be positioned at same device.As selection, NVM 101 can comprise independently integrated circuit or the device independently of many interconnection each other.For example, processor 150 can be positioned on the integrated circuit identical with nvm array 103 or be positioned at other elements of NVM 101 integrated circuit separated from one another on.In addition, in order to save the space, ADC 330 or 530 can be positioned on the circuit identical with nvm array 103 or be positioned at other elements of NVM 101 integrated circuit separated from one another on.But, for consistent environmental behaviour is provided, floating boom formula benchmark bit location or should be positioned on the circuit identical with the element of related nvm array based on the Iref generator of band gap.
And those skilled in the art should recognize, the boundary between the function of aforesaid operations is just illustrative.The function of a plurality of operations can be combined into single operation, and/or the function of single operation can be distributed in the operation that separately adds.And interchangeable embodiment can comprise the Multi-instance of specific operation, and the order of operation can be changed in other different embodiment.
In one embodiment, NVM 101 is merged in computer system, for example, and the personal computer system.Other embodiment can comprise dissimilar computer system.Computer system is can be designed to give the independently information handling system of computing power for one or more user.Computer system can have many forms, includes, but are not limited to large scale computer, micro computer, server, workstation, personal computer, notebook computer, personal digital assistant, electronic game machine, automobile and other embedded systems, mobile phone and other various wireless devices.Typical computer system comprises storer and a plurality of I/O (I/O) device of at least one processing unit, association.
Although the present invention describes with reference to specific embodiment at this, in the situation that the illustrated scope of the present invention of the claim below not breaking away from can be carried out various modifications and changes.Therefore, this instructions and accompanying drawing should be counted as illustrative, rather than restrictive, and all this type of revise all should be contained in scope of the present invention within.Should not be counted as feature or the important document of key, the necessary or essence of any or whole claims about the described any rights and interests of specific embodiment, advantage or solution of problem scheme at this.
Term as used herein " couples " should not be defined to and directly couples or machinery couples.
And term as used herein " " or " one " are defined as one or more.In addition, the use of introducing phrase in claims such as " at least one " and " one or more " should not be counted as and hint: any specific claim that will be contained the claim element of this introducing by the introducing of indefinite article " " or " one " caused other claim elements is defined in the invention that only contains such element, even comprising, identical claim introduces row phrase " one or more " or " at least one " and indefinite article, for example, " one " or " one ".Use for definite article is like this equally.
Except as otherwise noted, otherwise the term such as " first " and " second " is used to distinguish arbitrarily the described element of this type of term.Thereby these terms might not be time order and function or other order that will point out this class component.
Claims (20)
1. method comprises:
The reference current of nonvolatile memory (NVM) is converted to the digital value of NVM reference current, the analog to digital converter that wherein said conversion couples by the generator with described NVM reference current (ADC) is carried out;
The digital value of described NVM reference current and the scope of desired value are compared;
If the digital value of described NVM reference current is in outside the scope of described desired value, the generator of adjusting described NVM reference current is producing the NVM reference current of being adjusted, within wherein the digital value of the NVM reference current of adjusting related with the NVM reference current of adjusting is in the scope of described desired value; And
Wherein said conversion, comparison and adjustment are carried out by the member of the SOC (system on a chip) that comprises NVM.
2. method according to claim 1, the generator of the described NVM reference current of wherein said adjustment comprises to produce the NVM reference current of being adjusted:
If the digital value of described NVM reference current less than the scope of described desired value, puts on erasing pulse the generator of described NVM reference current; And
If the digital value of described NVM reference current is greater than the scope of described desired value, with the generator of program pulse application in described NVM reference current, wherein
The generator of described NVM reference current comprises floating boom formula benchmark bit location.
3. method according to claim 2, wherein
The generator of described NVM reference current with comprise that the nvm array of a plurality of floating boom formula bit locations couples, and
Described a plurality of floating boom formula bit location comprises described floating boom formula benchmark bit location.
4. method according to claim 1, the generator of the described NVM reference current of wherein said adjustment comprises to produce the NVM reference current of being adjusted:
If the digital value of described NVM reference current less than the scope of described desired value, is finely tuned band-gap circuit to increase described NVM reference current; And
If the digital value of described NVM reference current greater than the scope of described desired value, is finely tuned described band-gap circuit to reduce described NVM reference current, wherein
The generator of described NVM reference current comprises the circuit based on band gap.
5. method according to claim 4, the described band-gap circuit of described fine setting comprises the value of the control register of adjusting reference current.
6. method according to claim 1 also comprises:
Adjust the digital value of described NVM reference current and the scope of described desired value in response to the temperature value that records.
7. system comprises:
Nonvolatile memory (NVM) array;
Configuration is used for generating the generator with the NVM reference current of the NVM reference current that visits described nvm array;
Analog to digital converter (ADC) couples with the generator of described NVM reference current, and is arranged to the digital value that described NVM reference current is converted to the NVM reference current;
Comparer couples with described ADC, and the digital value and the desired value that are arranged to described NVM reference current compare; And
The fine setting logical block couples with described comparer, and is arranged to
Produce the NVM reference current of being adjusted when providing outside control signal is in described desired value with the digital value at described NVM reference current scope for the generator of described NVM reference current, within the digital value of the NVM reference current of wherein adjusting is in the scope of described desired value.
8. system according to claim 7 also comprises:
The NVM program/erase controller couples with the generator of described fine setting logical block and described NVM reference current, and is arranged to
Reception is from the described control signal of described fine setting logical block,
If described control signal comprises the digital value of described NVM reference current lower than the mark of the lower limit of the scope of described desired value, erasing pulse is provided for the generator of described NVM reference current in response to described control signal, and
If described control signal comprises the digital value of described NVM reference current greater than the mark of the upper limit of the scope of described desired value, programming pulse is provided for the generator of described NVM reference current in response to described control signal; And
The generator of described NVM reference current comprises floating boom formula benchmark bit location.
9. system according to claim 8, wherein said nvm array comprises described floating boom formula benchmark bit location.
10. system according to claim 8 also comprises:
One or more register couples with described comparer, the upper limit of the lower limit of the scope of the described desired value of storage and the scope of described desired value.
11. system according to claim 10 also comprises:
Temperature sensor couples with one or more in described ADC and described one or more register, and is arranged to temperature data to described one or more in described ADC and described register is provided;
Described ADC also is arranged to the digital value of adjusting when needed described NVM reference current in response to described temperature data; And
Described one or more register also is arranged to when needed the upper limit of adjusting the scope of the lower limit of scope of described desired value and described desired value in response to described temperature data.
12. system according to claim 7 also comprises:
Register couples with described ADC and described comparer, stores the digital value of described NVM reference current.
13. system according to claim 7 also comprises:
Control register couples with the generator of described fine setting logical block and described NVM reference current, and is arranged in response to from the described control signal of described fine setting logical block and storing value; And
Described NVM reference generator also comprises band-gap circuit, wherein, and in response to the value that is stored in described control register,
If the digital value of described NVM reference current is less than the scope of described desired value,
Described band-gap circuit is finely tuned to increase described NVM reference current, and
If the digital value of described NVM reference current is greater than the scope of described desired value,
Described band-gap circuit is finely tuned to reduce described NVM reference current.
14. system according to claim 7, the generator of wherein said NVM reference current be arranged in described nvm array near, make the generator of described NVM reference current be exposed under basically similar environmental baseline with described nvm array.
15. system according to claim 7, wherein said ADC also are arranged in response to receiving be used to the order that starts described conversion and carry out the described processing that described NVM reference current is converted to the digital value of NVM reference current.
16. system according to claim 7, wherein said ADC also be arranged in response to start, in outage or the diagnostic check of asking one or more and carry out the described processing that described NVM reference current is converted to the digital value of NVM reference current.
17. a device comprises:
Be used for the reference current of nonvolatile memory (NVM) is converted to the conversion equipment of the digital value of NVM reference current;
Be used for the scope comparison means relatively with digital value with the desired value of being scheduled to of described NVM reference current;
Be used for adjusting the generator of described NVM reference current to produce the adjusting gear of the NVM reference current of being adjusted, the digital value of the NVM reference current of wherein adjusting is related with the NVM reference current of adjusting within the scope that is in described desired value, carries out described adjustment if the digital value of described NVM reference current is in outside the scope of described desired value; And
Wherein said conversion equipment, comparison means and adjusting gear are the members that comprises the SOC (system on a chip) of NVM.
18. device according to claim 17 wherein comprises with the described adjusting gear that produces the NVM reference current of being adjusted for the generator of adjusting described NVM reference current:
Be used for erasing pulse being put on during less than the scope of described desired value in the digital value of described NVM reference current the device of the generator of described NVM reference current;
Be used for the digital value of described NVM reference current during greater than the scope of described desired value with the device of program pulse application in the generator of described NVM reference current, wherein
The generator of described NVM reference current comprises floating boom formula benchmark bit location.
19. device according to claim 18, wherein
Be used for generating the device of described NVM reference current and comprising that the nvm array of a plurality of floating boom formula bit locations couples, and
Described a plurality of floating boom formula bit location comprises described floating boom formula benchmark bit location.
20. device according to claim 17 wherein comprises with the described adjusting gear that produces the NVM reference current of being adjusted for the generator of adjusting described NVM reference current:
Be used for the digital value of described NVM reference current during less than the scope of described desired value the fine setting band-gap circuit to increase the device of described NVM reference current;
Be used for finely tuning described band-gap circuit to reduce the device of described NVM reference current, wherein in the digital value of described NVM reference current during greater than the scope of described desired value
The generator of described NVM reference current comprises the circuit based on band gap.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/286,175 | 2011-10-31 | ||
| US13/286,175 US8687428B2 (en) | 2011-10-31 | 2011-10-31 | Built-in self trim for non-volatile memory reference current |
Publications (2)
| Publication Number | Publication Date |
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| CN103093831A true CN103093831A (en) | 2013-05-08 |
| CN103093831B CN103093831B (en) | 2017-04-12 |
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| CN201210426250.2A Active CN103093831B (en) | 2011-10-31 | 2012-10-31 | Built-in self trim for non-volatile memory reference current |
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| US (2) | US8687428B2 (en) |
| KR (1) | KR102059899B1 (en) |
| CN (1) | CN103093831B (en) |
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| CN106448739A (en) * | 2016-07-05 | 2017-02-22 | 广东高云半导体科技股份有限公司 | Testing system and method for realizing FPGA (Field Programmable Gate Array) device on the basis of analog switch circuit |
| CN108231099A (en) * | 2016-12-15 | 2018-06-29 | 台湾积体电路制造股份有限公司 | For the adjusting circuit and its operating method of partitioned storage block |
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| US9601203B2 (en) * | 2012-06-09 | 2017-03-21 | Synopsys, Inc. | Floating gate non-volatile memory bit cell |
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| US9353017B2 (en) | 2014-06-17 | 2016-05-31 | Freescale Semiconductor, Inc. | Method of trimming current source using on-chip ADC |
| US9857999B2 (en) * | 2015-11-09 | 2018-01-02 | Western Digital Technologies, Inc. | Data retention charge loss sensor |
| US10431319B2 (en) | 2017-11-03 | 2019-10-01 | Micron Technology, Inc. | Selectable trim settings on a memory device |
| US10535415B2 (en) | 2017-11-03 | 2020-01-14 | Micron Technology, Inc. | Trim setting determination for a memory device |
| US10324839B2 (en) | 2017-11-03 | 2019-06-18 | Micron Technology, Inc. | Trim setting determination on a memory device |
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Also Published As
| Publication number | Publication date |
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| US20140160869A1 (en) | 2014-06-12 |
| US20130107621A1 (en) | 2013-05-02 |
| US8687428B2 (en) | 2014-04-01 |
| KR102059899B1 (en) | 2019-12-27 |
| KR20130047599A (en) | 2013-05-08 |
| US9076508B2 (en) | 2015-07-07 |
| CN103093831B (en) | 2017-04-12 |
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