CN104657287A - Novel data caching system and caching method for broadband receiver - Google Patents
Novel data caching system and caching method for broadband receiver Download PDFInfo
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- CN104657287A CN104657287A CN201510074440.6A CN201510074440A CN104657287A CN 104657287 A CN104657287 A CN 104657287A CN 201510074440 A CN201510074440 A CN 201510074440A CN 104657287 A CN104657287 A CN 104657287A
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Abstract
The invention discloses a novel data caching system and a data caching method for a broadband receiver. The caching method comprises the steps that (1) a controller receives a data request command transmitted by other logic modules of an intermediate frequency processor; (2) the controller detects the current data request command, makes arbitration and determines the data request command to be executed currently; (3) the controller generates the address that the current data is to be written into or to be read out according to the data request command to be executed after arbitration; (4) the current data is written to the specified address of a memory bank or the current data is read out from the specified address of the memory bank. The data caching system and the data caching method for the broadband receiver have the advantages that the contradiction between data accessing speed and data storage capacity is solved, and the data storage demand for large broadband and ultra-large broadband signals can be met; the storage space of the memory bank also can be allocated, and the requirements on multi-channel data accessing and small-broadband data continuous transmission, and synchronous large-broadband data write-in or read-out operation are met.
Description
Technical field
The present invention relates to a kind of the new types of data caching system and the caching method thereof that are applicable to broadband receiver, belong to data analysis field of storage.
Background technology
Under normal circumstances, in monitoring receiver, the scope of the signal that equipment can be caught often is required to comprise little of hundreds of KHZ bandwidth, greatly to the signal of tens MHz bandwidth.According to the vision of software radio, wish that equipment digitalized degree can be more high better, preferably only need the receiver of the additional a set of pure digi-tal of a antenna.But in fact because current digital device can only be operated in intermediate-frequency bandwidth substantially, therefore current receiver architecture is also add radio-frequency transmitter between antenna and data intermediate-frequency receiver.Radio-frequency transmitter is converted to digital signal feeding intermediate frequency processor again and carries out signal transacting after carrying out lower mixing to the signal that antenna receives, and finally by the various features of visual terminal demonstration signal.Signal, in the process being quantified as digital signal, also makes the variation range finally requiring the data stream bandwidth that Digital IF Processing device can process change from a few MBps to a few GBps.For large bandwidth signal, the bandwidth bottleneck of the whole data link often of the interface between visual terminal and intermediate frequency processor, realize large bandwidth or the continuous transmission of super large bandwidth signal between intermediate frequency processor is impossible at present substantially.Therefore in order to meet the detection requirement to large bandwidth signal, often need to carry out buffer memory to signal in intermediate frequency processor.Have the method that data buffer storage is conventional at present and adopt SRAM and solid state hard disc etc., SRAM access speed is very fast, but monolithic capacity is difficult to do greatly, adopting multi-disc SRAM to form storage battle array can cause again cost greatly to increase, although solid state hard disc has the feature of large data capacity, but its data bandwidth is relatively still comparatively slow, the data rate read-write requirement of large bandwidth super large bandwidth signal can not be met.
Summary of the invention
The object of the present invention is to provide a kind of the new types of data caching system and the caching method thereof that are applicable to broadband receiver, there is the problem of contradiction between data access speed and data storage capacity in the data cache method solving existing intermediate frequency processor.
To achieve these goals, the technical solution used in the present invention is as follows:
A kind of new types of data caching system being applicable to broadband receiver, comprise controller and carry out the memory bar of data transmission with controller, described controller comprises for receiving the data request command that in intermediate frequency processor, other logic modules send, and make the master control logic module of arbitration, for generation of the address generation logic module of address that the address of write or current data will read by current data, current data for reading from memory bar after performing data request command is carried out the reception buffer zone of buffer memory and the current data of write memory bar will be carried out the transmission buffer zone of buffer memory.
Particularly, described controller adopts programmable logic device (PLD) FPGA, and described memory bar is DDR2 memory bar.
Be applicable to a caching method for the new types of data caching system of broadband receiver, comprise the steps:
(1) controller receives the data request command that in intermediate frequency processor, other logic modules send;
(2) controller detects current data request command, and makes arbitration according to the state of current controller, the current data request command that will perform of final decision;
(3) controller is according to the address needing the data request command of execution will be read in the address of write or current data with the status information of current data generation current data after arbitration;
(4) controller produces and meets the control signal of memory bar interface standard, operates memory bar, current data to be written in memory bar assigned address or to read this current data from assigned address.
Further, described data request command is write request order, or read request command, or requires the read-write requests order of read and write simultaneously.
Further, in described step (1), controller receiving data request command is that the master control logic module in controller controls to carry out.
Again further, producing current data in described step (3) is that address generation logic module is in the controller carried out by the address of reading by the address of write or current data.
Again further, in described step (4), if write request order, in controller, master control logic module sends control signal and current data is sent to and sends buffer zone, then is sent to memory bar is stored, if read request command by transmission buffer zone, in controller, master control logic module sends a control signal to memory bar, current data is read from memory bar, and is sent to reception buffer zone, be sent to other logic modules in intermediate frequency processor again by reception buffer zone.
Compared with prior art, the present invention has following beneficial effect:
(1) the invention solves the contradiction between data access speed and data storage capacity, DDR2 memory bar and programmable logic device (PLD) is mainly utilized to form a spatial cache, this spatial cache has relatively large storage space, larger reading and writing data bandwidth can be provided simultaneously, the data storing work of large bandwidth and super large bandwidth signal can be met; And can distribute the storage space of this memory bar, meet multi-channel data access, and little band data is transmitted with the write of large bandwidth data or reads the requirement simultaneously carried out continuously.
(2) the present invention devises a controller for DDR2 memory bar, the storage space of this controller to DDR2 memory bar distributes, and the memory device of outside is controlled, the data of each passage can correctly be write in corresponding storage space, and ensure the data that correctly can read respective channel in the process of digital independent, the logical partitioning of the storage space that this controller realizes, make little band data and large bandwidth data, single-channel data and multi-channel data all can be stored on Same Physical medium, under guarantee meets the prerequisite of the demand of multiple operative scenario, save valuable PCB surface to amass, reduce the resource consumption of programmable logic device (PLD) entirety, reduce the complexity of intermediate frequency processor plate and eventually reduce production cost.
(3) during controller work of the present invention, read-write operation can be carried out simultaneously, and the type of current data can be gone out respectively, and according to data type, data are stored in corresponding continuous data storage area according to time domain continuous print principle, the present invention not only solves the dilemma that intermediate frequency processor meets with when processing large bandwidth signal, and provide a very simple and clear operation-interface, for the design of whole intermediate frequency processor reduces design complexities.
Accompanying drawing explanation
Fig. 1 is workflow diagram of the present invention.
Fig. 2 is system chart of the present invention.
Embodiment
Below in conjunction with embodiment and accompanying drawing thereof, the present invention is described in further detail, but embodiments of the present invention are not limited thereto.
Embodiment
As shown in Figure 1, a kind of new types of data caching method being applicable to broadband receiver, comprises the steps:
(1) controller receives the data request command that in intermediate frequency processor, other logic modules send, and this data request command is write request order, or read request command, or requires the read-write requests order of read and write simultaneously;
(2) controller detects current data request command, and makes arbitration according to the state of current controller, and which data request command final decision performs;
(3) the address generation logic module in controller produces with the status information of current data the address that the address of write or current data will read by current data according to the data request command needing after arbitration to perform, and this address produces correct address according to the information of current data and the memory of address logic to whole space;
(4) controller finally produces the control signal meeting memory bar interface standard, operates memory bar, current data to be written in memory bar assigned address or to read this current data from assigned address.
Controller receiving data request command is that the master control logic module in controller controls to carry out.Controller adopts programmable logic device (PLD) FPGA, and memory bar is DDR2 memory bar.
Wherein in step (4), if write request order, in controller, master control logic module sends control signal and current data is sent to transmission buffer zone, be sent to memory bar by transmission buffer zone again to store, if read request command, in controller, master control logic module sends a control signal to memory bar, current data is read from memory bar, and be sent to reception buffer zone, be sent to other logic modules in intermediate frequency processor again by reception buffer zone.
As shown in Figure 2, a kind of new types of data caching system being applicable to broadband receiver, comprise controller and carry out the memory bar of data transmission with controller, this controller is embedded on intermediate frequency process plate, this controller comprises for receiving the data request command that in intermediate frequency processor, other logic modules send, and after detecting data request command, make the master control logic module of arbitration, for generation of the address generation logic module of address that the address of write or current data will read by current data, current data for reading from memory bar after performing data request command is carried out the reception buffer zone of buffer memory and the current data of write memory bar will be carried out the transmission buffer zone of buffer memory.
According to above-described embodiment; just can realize the present invention preferably; under prerequisite based on said structure design; for solving same technical matters; even if some making on the invention are without substantial change or polishing; the essence of the technical scheme adopted is still the same with the present invention, therefore it also should in protection scope of the present invention.
Claims (7)
1. one kind is applicable to the new types of data caching system of broadband receiver, it is characterized in that, comprise controller and carry out the memory bar of data transmission with controller, described controller comprises for receiving data request command and making the master control logic module of arbitration, for generation of the address generation logic module of address that the address of write or current data will read by current data, the current data for reading from memory bar after performing data request command is carried out the reception buffer zone of buffer memory and the current data of write memory bar will be carried out the transmission buffer zone of buffer memory.
2. a kind of new types of data caching system being applicable to broadband receiver according to claim 1, is characterized in that, described controller adopts programmable logic device (PLD) FPGA, and described memory bar is DDR2 memory bar.
3. a kind of caching method being applicable to the new types of data caching system of broadband receiver according to claim 1-2 any one, is characterized in that, comprise the steps:
(1) controller receiving data request command;
(2) controller detects current data request command, and makes arbitration according to the state of current controller, the current data request command that will perform of final decision;
(3) controller is according to the address needing the data request command of execution will be read in the address of write or current data with the status information of current data generation current data after arbitration;
(4) controller produces and meets the control signal of memory bar interface standard, operates memory bar, current data to be written in memory bar assigned address or to read this current data from assigned address.
4. a kind of caching method being applicable to the new types of data caching system of broadband receiver according to claim 3, it is characterized in that, described data request command is write request order, or read request command, or requires the read-write requests order of read and write simultaneously.
5. a kind of caching method being applicable to the new types of data caching system of broadband receiver according to claim 3, is characterized in that, in described step (1), controller receiving data request command is that the master control logic module in controller controls to carry out.
6. a kind of caching method being applicable to the new types of data caching system of broadband receiver according to claim 5, it is characterized in that, producing current data in described step (3) is that address generation logic module is in the controller carried out by the address of reading by the address of write or current data.
7. a kind of caching method being applicable to the new types of data caching system of broadband receiver according to claim 6, it is characterized in that, in described step (4), if write request order, in controller, master control logic module sends control signal and current data is sent to transmission buffer zone, be sent to memory bar by transmission buffer zone again to store, if read request command, in controller, master control logic module sends a control signal to memory bar, current data is read from memory bar, and be sent to reception buffer zone, other logic modules in intermediate frequency processor are sent to again by reception buffer zone.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105242242A (en) * | 2015-08-27 | 2016-01-13 | 西安空间无线电技术研究所 | Super broadband signal pre-distortion compensation method based on parameter fitting |
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| US6625440B1 (en) * | 2000-01-31 | 2003-09-23 | Trw Inc. | Drum memory controller |
| CN201859658U (en) * | 2010-11-29 | 2011-06-08 | 成都傅立叶电子科技有限公司 | Embedded SDRAM (synchronous dynamic random access memory) module |
| CN102646084A (en) * | 2012-03-06 | 2012-08-22 | 上海纳轩电子科技有限公司 | Efficient network packet storage method implemented based on FPGA (field programmable gate array) |
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Patent Citations (4)
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| US5347637A (en) * | 1989-08-08 | 1994-09-13 | Cray Research, Inc. | Modular input/output system for supercomputers |
| US6625440B1 (en) * | 2000-01-31 | 2003-09-23 | Trw Inc. | Drum memory controller |
| CN201859658U (en) * | 2010-11-29 | 2011-06-08 | 成都傅立叶电子科技有限公司 | Embedded SDRAM (synchronous dynamic random access memory) module |
| CN102646084A (en) * | 2012-03-06 | 2012-08-22 | 上海纳轩电子科技有限公司 | Efficient network packet storage method implemented based on FPGA (field programmable gate array) |
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| CN105242242A (en) * | 2015-08-27 | 2016-01-13 | 西安空间无线电技术研究所 | Super broadband signal pre-distortion compensation method based on parameter fitting |
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Application publication date: 20150527 |