CN104637867B - Silicon hole lithographic method - Google Patents
Silicon hole lithographic method Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 137
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 66
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 66
- 239000010703 silicon Substances 0.000 title claims abstract description 66
- 230000008021 deposition Effects 0.000 claims abstract description 150
- 238000005530 etching Methods 0.000 claims abstract description 129
- 239000007789 gas Substances 0.000 claims abstract description 91
- 230000008569 process Effects 0.000 claims abstract description 76
- 230000008859 change Effects 0.000 claims abstract description 25
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 3
- 230000001788 irregular Effects 0.000 claims description 3
- 206010051986 Pneumatosis Diseases 0.000 claims description 2
- 238000009826 distribution Methods 0.000 abstract description 10
- 239000004065 semiconductor Substances 0.000 abstract description 7
- 230000003746 surface roughness Effects 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 description 123
- 238000010586 diagram Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 9
- 238000004904 shortening Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
- B81C1/00087—Holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
- B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
- B81C2201/0111—Bulk micromachining
- B81C2201/0112—Bosch process
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The present invention relates to technical field of semiconductors, disclose a silicon hole lithographic method, including repeated process cycle step, the process cycle step includes etch step and side wall deposition step, in the process cycle step respectively repeated, the execution time is gradually reduced the side wall deposition step.It is an advantage of the invention that, with repeating for process cycle step, etching depth gradually deepens, the execution time of side wall deposition step gradually shortens in process cycle step, by the execution time for adjusting side wall deposition step in the process cycle step repeated, with the intensification of etching depth, change the intake of etching gas and deposition gases in etching process, so as to change etching structure surface and side wall etching gas, the distribution of deposition gases and its caused plasma, realize the homogeneity of high aspect ratio structure etching, and etching structure surface roughness and verticality of side wall are ensured, the etching structure of high quality can be obtained.
Description
Technical field
The present invention relates to technical field of semiconductors, is related to silicon hole lithographic technique, more particularly to towards high aspect ratio structure
Silicon hole lithographic technique.
Background technology
In recent years, computer, communication, automotive electronics, aerospace industry and other consumer products are to microelectronics Packaging
Higher requirement is proposed, i.e., smaller, thinner and lighter, highly reliable, multi-functional, low-power consumption and low cost are, it is necessary on Silicon Wafer
Many perpendicular interconnection through holes are prepared to realize the electrical interconnection between different chips, silicon hole etching technics is increasingly becoming micro-nano and added
One important technology in work field.And with microelectronic mechanical devices and microelectromechanical systems（Micro
Electromechanical System, MEMS）It is applied to the field such as automobile and electricity charge electronics by more and more extensive, and
TSV（Through Silicon Via）Via etch（Through Silicon Etch）Technology is wide following encapsulation field
Wealthy prospect, deep silicon etching technique are increasingly becoming one of technique most very powerful and exceedingly arrogant in MEMS manufacturing fields and TSV technology.
Silicon hole etching technics is a kind of deep silicon etching technique of using plasma dry etching, relative in general silicon
Etching technics, its main distinction are：Etching depth is much larger than in general silicon etching process.The etching of in general silicon etching process
Depth is typically smaller than 1 μm, and the etching depth of deep silicon etching technique is then tens microns or even microns up to a hundred, has very big depth
Wide ratio.Therefore, the silicon materials that depth is dozens or even hundreds of micron are removed, it is necessary to etch to obtain good deep hole morphology, just
It is required that deep silicon etching technique has a faster etch rate, higher selection than with bigger depth-to-width ratio.
At present, conventional deep silicon etching technique is mainly characterized in that：Whole etching process is the multiple of etch unit
Repeat, the etch unit includes etch step and deposition step, and in other words, whole etching process is an etch step and one
The alternate cycles of deposition step.Fig. 1 performs schematic diagram for deep silicon etching technique etch unit in the prior art.As shown in figure 1, one
Individual etch step and a deposition step form an etch unit, it is however generally that, but during the execution of step and deposition step
Between identical, etch unit periodically repeated execution, be finally completed after repeatedly etch unit deep hole etching.
In the prior art, the process gas of etch step is mostly SF6, the gas etching silicon chip is with very high etching speed
Rate, but due to SF6Etching be isotropism, use CF in ensuing deposition stepxDeng the process gas of class containing F etched
Barrier layer is generated in journey to be protected to side wall side wall, to control sidewall profile（I.e. larger depth-to-width ratio, less lateral quarter
Erosion）；The barrier layer is usually the polymer that chemical reaction formation occurs with photoresist layer and/or silicon materials for plasma, for preventing
It is only laterally etched in etch step, so as to only be performed etching in the direction of vertical silicon chip, realize anisotropic etching.
However, with the continuous reduction pushed ahead with characteristic size of semiconductor technology node, silicon etching, it is particularly deeply
The depth-to-width ratio of silicon etching constantly increases, for the silicon etching structure that characteristic size is smaller, etching depth is deeper, by etching structure
The limitation of characteristic size, compared with the shallower position of substrate surface to be etched and depth, when etching proceeds to deeper position,
The distribution of etching gas, deposition gases and its caused plasma on etching structure side wall and surface varies widely, weight
In the etch unit carried out again, the balance between etch step and deposition step is broken, the roughness on etching structure surface and
Homogeneity is difficult to control, particularly the side wall quality of deep silicon etching, either sidewall roughness or verticality of side wall, all will be by
To considerable influence.
Therefore it provides towards the deep silicon etching technology of high aspect ratio structure, etching structure roughness, homogeneity are effectively controlled
And side wall quality, turn into and reliability of technology is improved under advanced technologies node, ensures semiconductor structure and device performance urgent need to resolve
The problem of.
The content of the invention
Technology to be solved by this invention is to provide a kind of silicon hole lithographic method, towards the deep silicon of high aspect ratio structure
Lithographic technique, etching structure roughness, homogeneity and side wall quality can be effectively controlled, solved in the deeper position of etching structure
Etching gas, deposition gases and its caused plasma are changed in the distribution of etching structure surface and side wall so as to influence
The problem of etching quality.
Silicon hole lithographic method provided by the invention, including the process cycle step performed is repeated several times, the processing procedure follows
Ring step includes etch step and side wall deposition step, and the side wall deposition step is in the process cycle step respectively repeated
In, the execution time is gradually reduced.
Alternatively, the process cycle step is during multiplicating, each execution time
Keep constant, and the single execution time of the process cycle step is 1~10s；The execution time of the etch step is system
Journey circulation step single performs the 50% of time.
Alternatively, the etch step is in the process cycle step respectively repeated, during execution
Between keep constant.
Alternatively, in the process cycle step performed first, the side wall deposition step include with
First stage that etch step performs jointly and the second stage individually performed.Further, it is described that the system performed is repeated several times
In journey circulation step, the time interval that the adjacent step of side wall deposition twice performs performs the time not less than the etch step
60%。
Alternatively, it is described to be repeated several times in the process cycle step performed, side wall deposition step list
The execution time-preserving of the second stage solely performed, the first stage that side wall deposition step performs jointly with etch step
The execution time is gradually reduced.Further, it is described to be repeated several times in the process cycle step performed, the execution of side wall deposition step
It is 0 that time, which was gradually reduced to the execution time of its first stage performed jointly with etch step,.
Alternatively, it is described to be repeated several times in the process cycle step performed, first gradually reduce side wall
The execution time for the first stage that deposition step and etch step perform jointly, after execution time of first stage is reduced to 0, then
Gradually reduce the execution time for the second stage that side wall deposition step individually performs.Further, it is described to be repeated several times what is performed
In process cycle step, the most short execution time of side wall deposition step performs the 50% of the time not less than etch step.
Alternatively, it is described to be repeated several times in the process cycle step performed, side wall deposition step
Perform linearly uniformly gradually to reduce, or gradually reduced with any non-linear rule, or irregular gradually reduce.
Alternatively, the etching gas that the etch step is passed through include SF6, the side wall deposition step
Suddenly the deposition gases being passed through include fluorocarbon gas.Further, the deposition gases bag that the side wall deposition step is passed through
Include C4F8Or CF4Or the mixed gas of the two.
Alternatively, in etch step and the side wall deposition step, the etching gas that are passed through and heavy
Product gas flow keeps constant.
Alternatively, in the part or all of execution time of the etch step, the etching gas that is passed through
Body flow is linear or nonlinear change.Further, in the implementation procedure of the etch step, the etching gas flow being passed through is in
The change of sinusoidal or Gaussian curve.
Alternatively, in the part or all of execution time of the side wall deposition step, what is be passed through is heavy
Pneumatosis body flow is linear or nonlinear change.Further, in the implementation procedure of the side wall deposition step, the deposition gas that is passed through
Body flow is in the change of sinusoidal or Gaussian curve.
In silicon hole lithographic method provided by the invention, with repeating for process cycle step, etching depth is gradual
Deepen, in process cycle step the execution time of side wall deposition step gradually shorten, by adjusting the process cycle that repeats
The execution time of side wall deposition step in step, with the intensification of etching depth, change etching gas and deposition in etching process
The intake of gas, so as to change etching structure surface and side wall etching gas, deposition gases and its caused plasma
Distribution.
Compared with the fixed cycle property of etching in the prior art/side wall deposition step is alternately performed, silicon provided by the invention
Etching method for forming through hole, in silicon hole etching process, particularly held in the deeper part of etching structure depth, side wall deposition step
The gradually shortening of row time, or even the time of occurrence interval between etch step and side wall deposition step, are passed through before being allowed to
Etching/deposition gases have the more sufficient time to diffuse to etching structure bottom, meanwhile, also cause polymer caused by etch step
Have abundance time diffuse out so that the position that etching structure depth is deeper, etching/deposition gases and its caused grade from
Daughter distribution reaches unanimity with its distribution in semiconductor substrate surface and the shallower position of etching structure depth, so as to realize profundity
The homogeneity of width-ratio structure etching, and etching structure surface roughness and verticality of side wall have been ensured, high quality can be obtained
Etching structure.
Brief description of the drawings
Fig. 1 is the first embodiment of silicon hole lithographic method schematic diagram provided by the invention；
Fig. 2 is the alternative embodiment schematic diagram of the first embodiment of silicon hole lithographic method one provided by the invention；
Fig. 3 is another alternative embodiment schematic diagram of the embodiment of silicon hole lithographic method first provided by the invention；
Fig. 4 is the second embodiment of silicon hole lithographic method schematic diagram provided by the invention.
Embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with implementation of the accompanying drawing to the present invention
Mode is described in further detail.Those skilled in the art can understand the present invention easily as the content disclosed by this specification
Other advantages and effect.The present invention can also be embodied or applied by other different embodiments, this explanation
Every details in book can also be based on different viewpoints and application, without departing from the spirit of the present invention carry out various modifications or
Change.
The silicon hole lithographic method that present embodiment provides, including the process cycle step C performed, institute is repeated several times
Stating process cycle step C includes etch step E and side wall deposition step D, in the process cycle step C respectively repeated, side
Wall deposition step D execution time TDGradually reduce.
As optional embodiment, process cycle step C in implementation procedure is repeated several times, protect by each execution time
Hold it is constant, and process cycle step C single perform time TCFor 1~10s, it is preferable that process cycle step C single performs
Time TCFor 4s or 10s.
As optional embodiment, in the process cycle step C respectively repeated, etch step E execution time
TECan be with identical, can also be different.As most preferred embodiment, in the process cycle step C of each repetition, etch step E's holds
Row time TEKeep constant, and etch step E execution time TEWith adjacent twice etching step Ei、Ei+1The interval time of execution
TEgIt is equal, in other words, etch step E execution time TETime T is performed for process cycle step C singlesC50%, i.e.,：TE=
TEg=TC×50%.Preferably, etch step E execution time TEAnd adjacent twice etching step Ei、Ei+1The interval time of execution
TEgIt is 2s or 5s.
As optional embodiment, the starting stage is etched in silicon hole, i.e., when performing process cycle step C first, side
Wall deposition step D includes the first stage D performed jointly with etch step E1The second stage D individually performed2, it is preferable that phase
Adjacent side wall deposition step D twicei、Di+1The time interval T of executionDgiTime T is performed not less than the etch step EE60%,
I.e.：Side wall deposition step D execution time TDNo longer than process cycle step member C singles perform time TC70%.
Fig. 1 is the first embodiment of silicon hole lithographic method schematic diagram provided by the invention.
As shown in figure 1, in the first embodiment, second stage D that side wall deposition step D is individually performed2Hold
Row time TD2Keep constant, and side wall deposition step D second stage D2Execution time TD2As adjacent twice etching step
Ei、Ei+1The interval time T of executionEg, as the presently preferred embodiments, in the silicon hole lithographic method that present embodiment provides,
The second stage D that side wall deposition step D is individually performed2Execution time TD2It is always 2s or 5s.
In the first embodiment, first stage D that side wall deposition step D and etch step E are performed jointly1Hold
Row time TD1Gradually reduce, when being completed to etching, side wall deposition step D execution time TDReduce to itself and etch step E and be total to
With the first stage D performed1Execution time TD1For 0, i.e.,：In the embodiment, the side wall deposition step D execution time
TDFrom T when performing firstD=TD1+TD2Reduce to TDn=TD2。
It is pointed out that in the process cycle step C repeated for the first time and subsequentlyiIn, side wall deposition step Di
Execution continue to next process cycle step Ci+1, i.e.,：In the process cycle step C that ith performsiIn, side wall deposition step
Rapid DiWith etch step EiThe first stage D performed jointly1iIncluding two parts：The side wall deposition step D of the i-th -1 time executioni-1With
The etch step E that ith performsiThe first stage D performed jointly1ai, the side wall deposition step D of ith executioniHeld with ith
Capable etch step EiThe first stage D performed jointly1bi, it is preferable that D1aiExecution time TD1aiMore than D1biThe execution time
TD1bi, that the difference between the two embodies is side wall deposition step DiPerform the gradually shortening of time, and TD1ai- TD1bi=△TDi/2；Can
Choosing, D1aiExecution time TD1aiWith D1biExecution time TD1biCan also be identical.In other words, side wall deposition is performed in ith
Step DiIn, its first stage D performed jointly with etch step E1iIncluding the etch step E performed with ithiIt is common to perform
First stage D1biWith the etch step E performed with i+1 timei+1The first stage D performed jointly1ai+1, it is preferable that D1bi's
Perform time TD1biWith D1a i+1Execution time TD1a i+1It is identical；Optionally, D1biExecution time TD1biMore than D1a i+1Hold
Row time TD1a i+1, that the difference between the two embodies is side wall deposition step DiPerform the gradually shortening of time, and TD1bi- TD1a i+1
=△TDi/2。
In the embodiment shown in fig. 1, process cycle step C is being performed first1During, step is performed etching first
E, and time T is performed first in etch step EEBefore end, start to perform side wall deposition step D, in process cycle step C1's
In implementation procedure, first stage D that side wall deposition step D and etch step E are performed jointly1Execution time TD1No more than etching
Step E performs time TE20%.
As another alternative embodiment, process cycle step C is being performed first1During, original state also can be simultaneously
Step E and side wall deposition step D are performed etching, and is no more than etch step E in the two common execution time and performs time TE's
When 20%, stop side wall deposition step D execution, step E to be etched continue executing with a period of time after, perform time TEBefore end,
Continue to start to perform side wall deposition step D, until process cycle step C1Terminate, and the side wall deposition step D execution time
Next process cycle step C can be extended to2.It is noted that in the embodiment, the process cycle step C that performs first1In, side
The time interval T that wall deposition step D is successively performed twiceDgTime T is performed not less than etch step EE60%, it is preferable that TDg=
TE× 60%, as most preferred embodiment, TDgFor 1.2s or 3s.
As shown in figure 1, in the first embodiment, etching process need to repeat n process cycle step C side can
Complete, in etching process, side wall deposition step DiThe second stage D individually performed2iExecution time TD2Keep constant, all the time
With etch step EiExecution time TEIt is equal, preferably 2s or 5s.Side wall deposition step DiPerform time TDiShortening, specifically
It is defined to side wall deposition step DiWith etch step EiThe first stage D performed jointly1=D1a+D1bExecution time TD1Gradually contract
It is short, i.e.,：△TDi=△TD1i, and the time △ T shortenedD1iThe side wall deposition step D of the i-th -1 time execution can be presented asi-1With i-th
The etch step E of secondary executioniThe first stage D performed jointly1aiPerform time TD1aiShortening, can be presented as ith perform
Side wall deposition step DiThe etch step E performed with ithiThe first stage D performed jointly1biPerform time TD1biContracting
It is short, it can also be presented as that above-mentioned two benches perform the time while shortened, until TD1ai=TD1bi=0, i.e.,：Last in etching process
The process cycle step C of secondary executionnIn, etch step EnWith side wall deposition step DnAlternately, the two is without the rank performed jointly
Section, and etch step EnWith side wall deposition step DnThe execution time it is equal, now, TDn=TD2n=TEn。
In the first embodiment, side wall deposition step D performs time TDGradually reduction, can be linear homogeneous
Gradually reduction, can gradually be reduced with any non-linear rule, or irregular gradually to reduce.Implement as optimal
Example, side wall deposition step D execution time TDLinearly, uniformly gradually reduce, until TDn=TD2n=TEn。
In addition, in this embodiment, the etching gas that the etch step E is passed through include SF6, the side wall sinks
The deposition gases that product step D is passed through include fluorocarbon gas, in etching process, the etching gas and deposition gases that are passed through
Flow can keep constant, can also do outflow control adjustment in etching process according to process requirements.
As the presently preferred embodiments, the deposition gases that the side wall deposition step D is passed through include C4F8Or CF4Or the two is mixed
Gas is closed, and as shown in figure 1, in the etch step E and side wall deposition step D, the etching gas and deposition gases that are passed through
Flow keeps constant.
Fig. 2 is the alternative embodiment schematic diagram of the first embodiment of silicon hole lithographic method one provided by the invention.
As shown in Fig. 2 as alternative embodiment, the part or all of execution of the etch step E/ side wall deposition steps D
During, etching gas/deposition gases flow linear change for being passed through.I.e.：In etch step E/ side wall deposition steps D, institute
Etching gas/deposition gases the flow needed is gradually increased to required flow value, when the etch step E/ side wall depositions in each cycle
At the end of step D, correspondingly, etching gas/deposition gases flow is gradually decreased as 0.The change of above-mentioned gas flow is line
Property change, the time that etching gas and deposition gases flow increase or decrease can be with identical, can also be different.
Fig. 3 is another alternative embodiment schematic diagram of the embodiment of silicon hole lithographic method first provided by the invention.
As shown in figure 3, as alternative embodiment, the part or all of execution of the etch step E/ side wall deposition steps D
During, etching gas/deposition gases flow nonlinear change for being passed through.I.e.：In etch step E/ side wall deposition steps D,
Required etching gas/deposition gases flow is non-linearly gradually increased to required flow value, when the etch step in each cycle
At the end of E/ side wall deposition steps D, correspondingly, etching gas/deposition gases flow is non-linearly gradually decreased as 0.This implementation
In example, the change of above-mentioned gas flow is sinusoidal variations or Gaussian curve change, and etching gas and deposition gases flow increase
, can also be different or the time of reduction can be with identical, i.e.,：In etch step E/ side wall deposition step D implementation procedures, gas is etched
The curve of body/deposition gases changes in flow rate can be symmetrical curve, can also be asymmetric.
Fig. 4 is the second embodiment of silicon hole lithographic method schematic diagram provided by the invention.
As shown in figure 4, in the second embodiment, compared with the first embodiment, the multiplicating is held
In capable process cycle step C, the first stage D that side wall deposition step D and etch step E is performed jointly is first gradually reduced1's
Perform time TD1, first stage D1Execution time TD1It is reduced to 0, performs to etch step EiExecution time TEiWith side wall
Deposition step DiPerform time TDi=TD2iAfter identical, the second-order that side wall deposition step D is individually performed further gradually is reduced
Section D2Execution time TD2, until etching terminates.It is pointed out that in the embodiment, described be repeated several times performs
Process cycle step CiIn, side wall deposition step D most short execution time TDminTime T is performed not less than etch step EE's
50%, i.e.,：TDn≥TEn×50%。
In present embodiment, as shown in figure 4, from side wall deposition step D first stage D1Execution time TD1Reduce
For 0, i.e. execution to etch step EiExecution time TEiWith side wall deposition step DiPerform time TDi=TD2iAfter identical, in processing procedure
Circulation step Ci+1To CnImplementation procedure in, process cycle step C not only includes the etch step E that individually performs and side
Wall deposition step D, in addition to the interval time performed without etching and side wall deposition step, with the progress that silicon hole etches, carve
Erosion depth gradually increases, and the introducing of above-mentioned interval time, the etching/deposition gases being passed through before being allowed to have the more sufficient time
Etching structure bottom is diffused to, meanwhile, the time that also causing polymer caused by etch step has abundance diffuses out, so that
The deeper position of etching structure depth, etching/deposition gases and its distribution of caused plasma are with it in semiconductor base table
The distribution of face and the shallower position of etching structure depth reaches unanimity, so as to realize the homogeneity of high aspect ratio structure etching.
It is similar with Fig. 2, embodiment illustrated in fig. 3, in the silicon hole lithographic method that present embodiment provides, the etching
In step E/ side wall deposition steps D part or all of implementation procedure, the etching gas/deposition gases flow being passed through is linear or non-
Linear change.I.e.：In etch step E/ side wall deposition steps D, required etching gas/deposition gases flow is linear or non-thread
Property be gradually increased to required flow value, at the end of the etch step E/ side wall deposition steps D in each cycle, correspondingly, carve
Erosion gas/deposition gases flow is linearly or non-linearly gradually decreased as 0.
As alternative embodiment, the change of above-mentioned gas flow is linear homogeneous change, etching gas and deposition gases
The time that flow increases or decreases can be with identical, can also be different.Preferably, performed in etch step E/ side wall deposition steps D
Intermediary time period, the flow of corresponding etching gas/deposition gases keeps stable, i.e.,：Above-mentioned gas flow is in the very short time
It is interior linearly uniformly to increase or decrease.
As another alternative embodiment, the change of above-mentioned gas flow is sinusoidal variations or Gaussian curve change, is etched
The time that gas and deposition gases flow increase or decrease can be with identical, can also be different, i.e.,：In etch step E/ side wall depositions
In step D implementation procedures, the curve of etching gas/deposition gases changes in flow rate can be symmetrical curve, can also be asymmetric.
In the silicon hole lithographic method that present embodiment provides, with repeating for process cycle step C, etching
Depth gradually deepens, process cycle step CiMiddle side wall deposition step DiExecution time TDiGradually shorten, repeated by adjusting
The process cycle step C of executioniMiddle side wall deposition step DiExecution time TDi, with the intensification of etching depth, change etching
During the intake of etching gas and deposition gases, so as to change etching structure surface and side wall etching gas, deposition gases
And its distribution of caused plasma.
Compared with the fixed cycle property of etch step E/ side wall depositions step D in the prior art is alternately performed, this is specific real
The silicon hole lithographic method that the mode of applying provides, in silicon hole etching process, particularly in the deeper part of etching structure depth,
Side wall deposition step D performs time TDGradually shortening, or even the time of occurrence between etch step E and side wall deposition step D
Interval, the etching/deposition gases being passed through before being allowed to have the more sufficient time to diffuse to etching structure bottom, meanwhile, also make
The time that obtaining polymer caused by etch step has abundance diffuses out, so that the position that etching structure depth is deeper, etching/
Deposition gases and its distribution of caused plasma and its point in semiconductor substrate surface and the shallower position of etching structure depth
Cloth reaches unanimity, and so as to realize the homogeneity of high aspect ratio structure etching, and has ensured etching structure surface roughness and side wall
Perpendicularity, the etching structure of high quality can be obtained.
Although by referring to some of the preferred embodiment of the invention, the present invention is shown and described,
It will be understood by those skilled in the art that can to it, various changes can be made in the form and details, without departing from this hair
Bright spirit and scope.
Claims (18)
- A kind of 1. silicon hole lithographic method, including the process cycle step that execution is repeated several times, the process cycle step Including etch step and side wall deposition step, it is characterised in that：The side wall deposition step is in the process cycle respectively repeated In step, the execution time is gradually reduced；The first stage that the side wall deposition step performs jointly with the etch step holds The row time is not zero.
- 2. silicon hole lithographic method according to claim 1, it is characterised in that the etch step is respectively repeating In process cycle step, time-preserving is performed.
- 3. silicon hole lithographic method according to claim 1, it is characterised in that the process cycle step is being repeated several times During, each execution time-preserving, be etch step the execution cycle, and the single of the process cycle step is held The row time is 1~10s.
- 4. silicon hole lithographic method according to claim 1, it is characterised in that the execution time of the etch step, be Process cycle step single performs the 50% of time.
- 5. silicon hole lithographic method according to claim 2, it is characterised in that in the process cycle step performed first, The side wall deposition step includes the first stage performed jointly with etch step and the second stage individually performed.
- 6. silicon hole lithographic method according to claim 5, it is characterised in that described that the process cycle performed is repeated several times In step, the time interval that the adjacent step of side wall deposition twice performs performs the 60% of the time not less than the etch step.
- 7. silicon hole lithographic method according to claim 6, it is characterised in that described that the process cycle performed is repeated several times In step, the execution time-preserving for the second stage that side wall deposition step individually performs, side wall deposition step walks with etching The execution time of the rapid first stage performed jointly is gradually reduced.
- 8. silicon hole lithographic method according to claim 7, it is characterised in that described that the process cycle performed is repeated several times In step, the execution time of side wall deposition step is gradually reduced to during the execution of its first stage performed jointly with etch step Between be 0.
- 9. silicon hole lithographic method according to claim 6, it is characterised in that described that the process cycle performed is repeated several times In step, the execution time for the first stage that side wall deposition step performs jointly with etch step, first stage are first gradually reduced The execution time be reduced to 0 after, then gradually reduce execution time of second stage that side wall deposition step individually performs.
- 10. silicon hole lithographic method according to claim 9, it is characterised in that the processing procedure performed that is repeated several times follows In ring step, the most short execution time of side wall deposition step performs the 50% of the time not less than etch step.
- 11. silicon hole lithographic method according to claim 1, it is characterised in that the processing procedure performed that is repeated several times follows In ring step, the execution linearly of side wall deposition step is uniformly gradually reduced, or is gradually reduced with any non-linear rule, Or irregular gradually reduce.
- 12. the silicon hole lithographic method according to any one in claim 1~11, it is characterised in that the etching step Suddenly the etching gas being passed through include SF6, the deposition gases that the side wall deposition step is passed through include fluorocarbon gas.
- 13. silicon hole lithographic method according to claim 12, it is characterised in that the side wall deposition step is passed through heavy Pneumatosis body includes C4F8Or CF4Or the mixed gas of the two.
- 14. silicon hole lithographic method according to claim 12, it is characterised in that etch step and the side wall deposition step In rapid, the etching gas and deposition gases flow that are passed through keep constant.
- 15. silicon hole lithographic method according to claim 12, it is characterised in that the etch step it is part or all of Perform in the time, the etching gas flow being passed through linearly or nonlinearly changes.
- 16. silicon hole lithographic method according to claim 15, it is characterised in that the implementation procedure of the etch step In, the etching gas flow being passed through is in the change of sinusoidal or Gaussian curve.
- 17. silicon hole lithographic method according to claim 12, it is characterised in that the part of the side wall deposition step or All perform in the times, the deposition gases flow that is passed through is linear or nonlinear change.
- 18. silicon hole lithographic method according to claim 17, it is characterised in that the execution of the side wall deposition step Cheng Zhong, the deposition gases flow being passed through is in the change of sinusoidal or Gaussian curve.
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| CN101958244A (en) * | 2009-07-21 | 2011-01-26 | 中微半导体设备(上海)有限公司 | Deep reactive ion etching method and gas flow control device thereof |
| WO2013008824A1 (en) * | 2011-07-12 | 2013-01-17 | 東京エレクトロン株式会社 | Plasma etching method |
| CN103159163A (en) * | 2011-12-19 | 2013-06-19 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Substrate etching method and substrate processing device |
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| CN101958244A (en) * | 2009-07-21 | 2011-01-26 | 中微半导体设备(上海)有限公司 | Deep reactive ion etching method and gas flow control device thereof |
| WO2013008824A1 (en) * | 2011-07-12 | 2013-01-17 | 東京エレクトロン株式会社 | Plasma etching method |
| CN103159163A (en) * | 2011-12-19 | 2013-06-19 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Substrate etching method and substrate processing device |
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