CN104618821A - Space satellite communication multiplexing method based on field programmable gate array (FPGA) - Google Patents
Space satellite communication multiplexing method based on field programmable gate array (FPGA) Download PDFInfo
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- CN104618821A CN104618821A CN201510086974.0A CN201510086974A CN104618821A CN 104618821 A CN104618821 A CN 104618821A CN 201510086974 A CN201510086974 A CN 201510086974A CN 104618821 A CN104618821 A CN 104618821A
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- multiplexer
- local area
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/60—Network structure or processes for video distribution between server and client or between remote clients; Control signalling between clients, server and network components; Transmission of management data between server and client, e.g. sending from server to client commands for recording incoming content stream; Communication details between server and client
- H04N21/61—Network physical structure; Signal processing
- H04N21/6106—Network physical structure; Signal processing specially adapted to the downstream path of the transmission network
- H04N21/6143—Network physical structure; Signal processing specially adapted to the downstream path of the transmission network involving transmission via a satellite
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/436—Interfacing a local distribution network, e.g. communicating with another STB or one or more peripheral devices inside the home
- H04N21/4363—Adapting the video or multiplex stream to a specific local network, e.g. a IEEE 1394 or Bluetooth® network
- H04N21/43632—Adapting the video or multiplex stream to a specific local network, e.g. a IEEE 1394 or Bluetooth® network involving a wired protocol, e.g. IEEE 1394
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs
- H04N21/4405—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs involving video stream decryption
Abstract
The invention discloses a space satellite communication multiplexing method based on a field programmable gate array (FPGA). The specific achieving process includes first setting a computer local area network and an IP telephone local area network sharing the same multiplexers; respectively connecting an image encoder and an image decoder with two groups of independent multiplexers in the computer local area network and the IP telephone local area network; enabling image signals to enter the image encoder which encodes the image signals into four ways of E1 signals which are transmitted into the multiplexers; enabling the image decoder to receive the four ways of E1 signals from the multiplexers, conduct image decoding and then transmit the signals to a display device to display images. The space satellite communication multiplexing method based on the FPGA achieves laser space transmission, and is high in transmission speed, high in information amount, wide in covering space, high in practicability and easy to popularize due to the fact that signals are received and transmitted through laser.
Description
Technical field
The present invention relates to data multiplexing technical field, specifically a kind of practical, based on FPGA Aerospace Satellite communication multiplexing method.
Background technology
The development need of information age set up a transmission rate fast, contain much information, communications network system that covering space is wide.The extremely short light wave of wavelength is adopted to carry out the communication of Aerospace Satellite, the preferred plan realizing high bit rate communication, even be considered to the only resource, especially in today that Aerospace Satellite is day by day crowded, this point has achieved the common recognition of the many experts and scholars in the communications field.In order to make full use of the advantage of laser space communication, ripe Digital Multiple Connection Technique can be brought as laser space communication service.If can Digital Multiple Connection Technique be used before the signal of telecommunication enters Laser Modulation part to carry out first-order multiplexes, the capacity of laser channel obviously can be used fully.
The application of Digital Multiple Connection Technique, first from local telephone network relay transmission, at that time for adapting to the flexible multiple connection of asynchronous branch road, adopted stuffing pulse technology to be high-speeld code-flow by the multiple connection of quasi synchronous low speed tributary signal.Communication media during beginning is cable, because band resource is nervous, therefore be mainly conceived to control stuffing jitter and save overhead bit expense, define the quasi-synchronous serial (PDH) of U.S., day, the three kinds of different rates structures in Europe according to the technology: history of country /region.These three kinds of asynchronous multiplexing systems, three is incompatible, intercommunication difficulty, and PDH multiplexing structure is complicated, so although it well can adapt to traditional point-to-point channel, but cannot adapt to the requirement of dynamically networking, also be difficult to exploitation and the modern network management of supporting new business, broadband integrated services digital network (B-ISDN) cannot be supported.
For adapt to telecommunications network develop rapidly and meet this situation is improved day by day to networking requirements, the convenience of the flexibility of operation Network Based, reliability, maintenance management and validity and the consideration to aspects such as the adaptability of future development, and a series of shortcoming of PDH, SDH has occurred.
SDH system is that TIU-T puts forward on the basis of U.S.'s Synchronous Optical Network (SONET) system.SONET is proposed by Bellcore of the U.S. at first, and the initial object formulating sonet standard is to stop growing in a large number of incompatible optical interface, realizes the optical interface of standard, is convenient to the intercommunication in light path of each plant equipment.But later development is well beyond this primary objective, SONET has been expanded into a kind of brand-new transmission network system, and it had not only been applicable to fiber channel but also had been applicable to the general counting system of the channel such as microwave and satellite.SDH specifies the interface standard of effective multiplexing various high speed business and original Low-rate traffic.
Certainly, as a kind of new technical system, can not be perfect, synchronous digital hierarchy still comes with some shortcomings part.As high not as traditional accurate synchro system in band efficiency; Adopt so-called Pointer Justification Count, add the complexity of equipment; Border shake is simultaneously more difficult reaches performance index requirements.In addition, Synchronization Network system is controlled by a whole set of software, if software is out of joint, probably causes the whole network to paralyse, and thus needs to stablize and reliable software.
Because Synchronization Network is introduced in plesiochronous network environment, thus relate to accurate synchronous and synchronous serial intercommunication problem.Within the quite a long time from now on, in telecommunications network, synchronous series and quasi-synchronous serial will be there is simultaneously.In the near future, WorldCom will be unified in synchronous digital network.
Society is digitized society, is the society of digital integrated circuit extensive use.And in PDH multiplex circuit in the past, what the mass part of system adopted is analog circuit, therefore there is significant limitation.Now, digital integrated circuit updates, system designers are more ready oneself design specialized integrated circuit (ASIC) chip, and wish that the design cycle of ASIC is short as far as possible, preferably just can design suitable asic chip in laboratory, and drop among practical application immediately, thus go out the on-the-spot logic programmable logical device (FPGA) of item, wherein most widely usedly surely belong to on-the-spot logic gate array (FPGA) and CPLD (CPLD).
Based on above-mentioned technology, now provide a kind of Aerospace Satellite based on FPGA communication multiplexing method.
Summary of the invention
Technical assignment of the present invention is for above weak point, provide a kind of practical, based on FPGA Aerospace Satellite communication multiplexing method.
Based on an Aerospace Satellite communication multiplexing method of FPGA, its specific implementation process is:
First arrange LAN (Local Area Network) and the IP phone local area network (LAN) of shared same multiplexer, described LAN (Local Area Network) comprises computer, the networking telephone, and this computer, the networking telephone all connect multiplexer by HUB interface; IP phone local area network (LAN) comprises the IP phone directly connecting multiplexer, and this multiplexer is also connected with RS232 interface;
Respectively image encoder, image decoder are connected two groups of multiplexers independently in LAN (Local Area Network) and IP phone local area network (LAN), thus form two groups of Digital Multiplex System, the multiplexer of two groups of Digital Multiplex System is connected by laser communication, wherein image encoder connection layout image source, this image source comprises DVD, CCD; Image decoder connects display unit, and this display unit comprises television set;
Picture signal enters image encoder, and this image encoder will become four road E1 signals after image signal encoding, then sends in multiplexer;
Image decoder carries out image decoding to divide the four road E1 Signal reception that pick out from multiplexer after, then gives display unit to show image.
The laser communication of described two groups of Digital Multiplex System refers to the laser communication device arranging band transmitting antenna on one group of multiplexer, another group multiplexer is arranged the laser communication device of band reception antenna.
The transmission code rate that described Digital Multiplex System adopts is 33.792M, and use 16 sequential altogether, the capacity of each sequential is 2.112M.
Described Digital Multiplex System completes telephony interface multiple connection, serial data multiple connection, Ethernet data multiple connection, E1 signal multiplexing, wherein
Telephony interface multiple connection process is: produce a burst pulse narrowclk as analog sampling mark with standard time clock clk2048k, obtain eight-digit number word signal; Through shift register SM module, be cached, wait for that the 4th sequential sends out;
Serial data multiple connection adopts asynchronous multiplexing method to realize, its multiple connection process is: first sample when clock 2.112M rising edge, after plaing two bats continuously, sends into the shift register of 16, after asynchronous-sampling, be directly converted to 2.112M clock synchronization data;
The multiple connection process of E1 signal is: first will carry out bit synchronous extraction; Code speed is adopted to carry out justification, insert pulse, the numeric code rate of each basic group is made to adjust to 2112kb/s by 2048kb/s, the main body of this code quick adjusting device is buffer storage, when the information bit in buffer storage drops to specified quantity, send control signal, at this moment control gate is closed, and readout clock is deducted a bit; Owing to not having readout clock, the information in buffer register just can not read, and at this moment information still just increases a bit toward buffer register stored in, the information therefore in buffer register; So repeat down, bitstream is sent out by buffer storage.
A kind of communication of the Aerospace Satellite based on FPGA multiplexing method of the present invention, has the following advantages:
A kind of communication of the Aerospace Satellite based on FPGA multiplexing method Ethernet interface of this invention, the serial ports based on RS232, telephone subscriber line interface, E1 interface, outside then completed the satellite communication in space by the modulation drive circuit of laser and the demodulator circuit of reception, signal is sent by laser pick-off, achieve the space propagation of laser, transmission rate is fast, contain much information, covering space is wide; Practical, be easy to promote.
Accompanying drawing explanation
Accompanying drawing 1 is overall structure block diagram of the present invention.
Accompanying drawing 2 is FPGA redundant system schematic block diagram.
Accompanying drawing 3 is the sequential chart of telephony interface.
Accompanying drawing 4 gives the clock of RJ017 and the datagram of RJ017 for FPGA.
Accompanying drawing 5 is the bit synchronization figure of HDB3.
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention will be further described.
Based on an Aerospace Satellite communication multiplexing method of FPGA, as shown in Figure 1, its specific implementation process is:
First arrange LAN (Local Area Network) and the IP phone local area network (LAN) of shared same multiplexer, described LAN (Local Area Network) comprises computer, the networking telephone, and this computer, the networking telephone all connect multiplexer by HUB interface; IP phone local area network (LAN) comprises the IP phone directly connecting multiplexer, and this multiplexer is also connected with RS232 interface;
Respectively image encoder, image decoder are connected two groups of multiplexers independently in LAN (Local Area Network) and IP phone local area network (LAN), thus form two groups of Digital Multiplex System, the multiplexer of two groups of Digital Multiplex System is connected by laser communication, wherein image encoder connection layout image source, this image source comprises DVD, CCD; Image decoder connects display unit, and this display unit comprises television set, and whole Digital Multiplex System outside connects the modulation drive circuit of laser and the demodulator circuit of reception;
Picture signal enters image encoder, and this image encoder will become four road E1 signals after image signal encoding, then sends in multiplexer;
Image decoder carries out image decoding to divide the four road E1 Signal reception that pick out from multiplexer after, then gives display unit to show image.
In above-mentioned steps, the present invention brings existing Digital Multiple Connection Technique into space optical communication service.Channel after its multiple connection is no longer optical cable, but wireless laser.Entire system block diagram such as V200D in Fig. 1, figure is image encoder, and V200E is image decoder.V200D will become four road E1 signals after image signal encoding, then send in multiplexer.V200E carries out image decoding to divide the four road E1 Signal reception that pick out from multiplexer after, then gives television set to show image.Two local area network (LAN)s couple together by multiplexer, and computer is communicated by local area network (LAN) with IP phone.Such multiplexer just achieves IP phone and computer remote laser communication.Official telephone and RS-232 signal are got up by multiplexer and other signal multiplexing, thus achieve the respective duplex communication of official telephone and RS-232.Two multiplexers are using laser as communications carrier after opto-electronic conversion, and the transmitting antenna of laser sends laser, and laser receiving antenna receives laser signal, thus achieve the space propagation of laser.
The laser communication of described two groups of Digital Multiplex System refers to the laser communication device arranging band transmitting antenna on one group of multiplexer, another group multiplexer is arranged the laser communication device of band reception antenna.
The transmission code rate that described Digital Multiplex System adopts is 33.792M, and use 16 sequential altogether, the capacity of each sequential is 2.112M.
Described Digital Multiplex System completes telephony interface multiple connection, serial data multiple connection, Ethernet data multiple connection, E1 signal multiplexing, wherein
Telephony interface multiple connection process is: as shown in Figure 3, is 2.112M with standard time clock clk2048k(actual frequency) produce a burst pulse narrowclk as analog sampling mark, obtain eight-digit number word signal.Through shift register SM module as shown in Figure 2, be cached, wait for that the 4th sequential sends out.The capacity of telephone signal is 8K, and time slot can transmit the capacity of 2M.Such time slot just can transmit No. 32 phones.
The multiple connection process of serial data is: the present invention selects asynchronous multiplexing method to carry out multiple connection rs 232 serial interface signal.In order to give FPGA by serial data, first sampling when clock 2.112M rising edge, after plaing two bats continuously, sending into the shift register of 16.After asynchronous-sampling, be directly converted to 2.112M clock synchronization data, account for a time slot.
The multiple connection process of Ethernet data is: network interface circuit forms primarily of the TP module of RJ45 interface and coupling transformer composition and chip RJ017.The RJ017(ChipBridge of the RAD company production of Israel) be that its one chip a kind of just can complete remote bridge function and the high-performance application-specific IC chip compatible mutually with IEEE802.3 agreement.Sequential as shown in Figure 4, as long as send into the clock with the 8.448M of standard time clock homology to RJ017, just can obtain the data sent.
Embodiment of the present invention adopts network transmission speed to be 8,000,000, because when the design is transmitted, a time slot can only transmit 2,000,000, needs to take 4 time slots so transmit it. and the buffer area wait finally sending into the serioparallel exchange of a 4bit is taken away.
The multiple connection process of E1 signal is: first will carry out bit synchronous extraction, and as shown in Figure 5, what E1 signal adopted is that HDB3 coded system transmits, and becomes the unipolar code of zero after decoding.Although it is accompanied with synchronizing information, consider complexity and the inconvenience of filter method, still adopt that digital servo-control is around-France extracts bit synchronization.
E1 signal code check is identical with the nominal value of multiple connection clock 2.048M, but in fact has certain deviation, must carry out justification.The present invention adopts positive justification mode to adjust.By inserting pulse, the numeric code rate of each basic group is made to adjust to 2112kb/s by 2048kb/s.Once complete clock adjustment, of namely taking in 16 time slots is transmitted.The main body of code quick adjusting device is buffer storage, also comprises the numeric code rate of the control circuit of some necessity, input branch road
=2.048Mbit/s ± 100bit/s, exporting numeric code rate is
=2.112Mbit/s.So-called positive justification be exactly because of
gain the name.
Assuming that the information in buffer was in half-full state originally, As time goes on, due to readout clock
be greater than write clock
, the information potential in buffer must be fewer and feweri, if do not take special measure, causes the information in buffer to be got sky at last, then the information read will be false information.In order to prevent the information of buffer from being got sky, need to take some measures.Drop to specified quantity once the information bit in buffer, just send control signal, at this moment control gate is closed, and readout clock is deducted a bit.Owing to not having readout clock, the information in buffer just can not read, and at this moment information still just increases a bit toward buffer stored in, the information therefore in buffer.So repeat down, just bitstream can be sent out by buffer storage.
Above-mentioned embodiment is only concrete case of the present invention; scope of patent protection of the present invention includes but not limited to above-mentioned embodiment; claims of any a kind of Aerospace Satellite based on FPGA communication multiplexing method according to the invention and the those of ordinary skill of any described technical field to its suitable change done or replacement, all should fall into scope of patent protection of the present invention.
Claims (4)
1., based on an Aerospace Satellite communication multiplexing method of FPGA, it is characterized in that, its specific implementation process is:
First arrange LAN (Local Area Network) and the IP phone local area network (LAN) of shared same multiplexer, described LAN (Local Area Network) comprises computer, the networking telephone, and this computer, the networking telephone all connect multiplexer by HUB interface; IP phone local area network (LAN) comprises the IP phone directly connecting multiplexer, and this multiplexer is also connected with RS232 interface;
Respectively image encoder, image decoder are connected two groups of multiplexers independently in LAN (Local Area Network) and IP phone local area network (LAN), thus form two groups of Digital Multiplex System, the multiplexer of two groups of Digital Multiplex System is connected by laser communication, wherein image encoder connection layout image source, this image source comprises DVD, CCD; Image decoder connects display unit, and this display unit comprises television set;
Picture signal enters image encoder, and this image encoder will become four road E1 signals after image signal encoding, then sends in multiplexer;
Image decoder carries out image decoding to divide the four road E1 Signal reception that pick out from multiplexer after, then gives display unit to show image.
2. a kind of communication of the Aerospace Satellite based on FPGA multiplexing method according to claim 1, it is characterized in that, the laser communication of described two groups of Digital Multiplex System refers to the laser communication device arranging band transmitting antenna on one group of multiplexer, another group multiplexer is arranged the laser communication device of band reception antenna.
3. a kind of communication of the Aerospace Satellite based on FPGA multiplexing method according to claim 1, it is characterized in that, the transmission code rate that described Digital Multiplex System adopts is 33.792M, and use 16 sequential altogether, the capacity of each sequential is 2.112M.
4. a kind of communication of the Aerospace Satellite based on FPGA multiplexing method according to claim 3, it is characterized in that, described Digital Multiplex System completes telephony interface multiple connection, serial data multiple connection, Ethernet data multiple connection, E1 signal multiplexing, wherein
Telephony interface multiple connection process is: produce a burst pulse narrowclk as analog sampling mark with standard time clock clk2048k, obtain eight-digit number word signal; Through shift register SM module, be cached, wait for that the 4th sequential sends out;
Serial data multiple connection adopts asynchronous multiplexing method to realize, its multiple connection process is: first sample when clock 2.112M rising edge, after plaing two bats continuously, sends into the shift register of 16, after asynchronous-sampling, be directly converted to 2.112M clock synchronization data;
The multiple connection process of E1 signal is: first will carry out bit synchronous extraction; Code speed is adopted to carry out justification, insert pulse, the numeric code rate of each basic group is made to adjust to 2112kb/s by 2048kb/s, the main body of this code quick adjusting device is buffer storage, when the information bit in buffer storage drops to specified quantity, send control signal, at this moment control gate is closed, and readout clock is deducted a bit; Owing to not having readout clock, the information in buffer register just can not read, and at this moment information still just increases a bit toward buffer register stored in, the information therefore in buffer register; So repeat down, bitstream is sent out by buffer storage.
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Cited By (1)
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| CN105763242A (en) * | 2016-02-03 | 2016-07-13 | 浪潮(北京)电子信息产业有限公司 | Space satellite communication demultiplexer and communication system |
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