CN104603947A - 抑制非硅器件工程的缺陷的方法 - Google Patents

抑制非硅器件工程的缺陷的方法 Download PDF

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Publication number
CN104603947A
CN104603947A CN201380045108.6A CN201380045108A CN104603947A CN 104603947 A CN104603947 A CN 104603947A CN 201380045108 A CN201380045108 A CN 201380045108A CN 104603947 A CN104603947 A CN 104603947A
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trap
lattice structure
type transistor
type
aspect ratio
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CN201380045108.6A
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CN104603947B (zh
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N·戈埃尔
R·皮拉里塞泰
N·慕克吉
R·S·周
W·拉赫马迪
M·V·梅茨
V·H·勒
J·T·卡瓦列罗斯
M·拉多萨夫列维奇
B·舒-金
G·杜威
S·H·宋
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Intel Corp
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Intel Corp
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Abstract

一种设备包括含有具有第一晶格结构的沟道材料的器件，所述沟道材料位于由阱材料构成的阱上，所述阱材料具有匹配晶格结构，所述阱处于具有第二晶格结构的缓冲材料内，所述第二晶格结构不同于所述第一晶格结构。一种方法包括在缓冲材料内形成沟槽；在所述沟槽内形成n型阱材料，所述n型阱材料具有不同于所述缓冲材料的晶格结构的晶格结构；以及形成n型晶体管。一种系统包括具有处理器的计算机，所述处理器包括互补金属氧化物半导体电路，所述电路包括具有沟道材料的n型晶体管，所述沟道材料具有第一晶格结构，并且处于设置在缓冲材料内的阱上，所述缓冲材料具有不同于第一晶格结构的第二晶格结构，所述n型晶体管耦合至p型晶体管。

Description

抑制非硅器件工程的缺陷的方法
技术领域
半导体器件。
背景技术
对于过去的几十年而言，集成电路的特征的缩小已经成为了半导体工业的推动力。特征不断缩小使得半导体芯片的有限体量的实物上的功能单元的密度增大。例如，缩小晶体管的尺寸允许将更高数量的存储器件结合到芯片上，从而制造出具有提高的容量的产品。但是，不断追求更高的容量并非不存在问题。优化每一器件的性能的愿望变得越来越迫切。
获得P沟道和N沟道场效应晶体管(FET)的增强性能的一种重要的可能性就是采用相对于硅具有大晶格失配的沟道材料。形成于外延生长半导体异质结构，例如，形成于III-V族材料系内的器件提供了(例如)格外高的晶体管沟道载流子迁移率，其原因在于低有效质量以及降低的由delta掺杂带来的杂质散射。这些器件提供了高驱动电流性能，并且未将来的低功率高速逻辑应用展现除了光明前景。但是，伴随着大的晶格失配，存在对器件成品率存在不利影响的线位错密度(TDD)或缺陷。对于互补金属氧化物半导体(CMOS)实现而言，基于硅或SOI衬底的对诸如III-V族材料和锗(Ge)的晶格失配材料的相互集成存在严峻的挑战。
附图说明
图1示出了在CMOS实现当中在衬底上包含NMOS三栅极器件和PMOS三栅极器件的结构的实施例的顶部正面透视图。
图2示出了在CMOS实现当中包括NMOS栅极全围绕(all around)器件和PMOS栅极全围绕器件的结构的另一实施例的顶部正面透视图。
图3示出了衬底基础、衬底基础上的缓冲材料以及在被指定用于NMOS结构的区域内形成于所述缓冲内的阱沟槽的顶部透视图。
图4示出了向阱沟槽内引入了缺陷俘获材料之后的图3的结构。
图5示出了在缓冲材料的上方表面上对用于NMOS和PMOS结构的隔离区进行构图并且在所述区域内引入器件层之后图4的结构。
图6示出了透过线6-6'的图5的结构的截面。
图7示出了透过线7-7'的图5的结构的截面。
图8示出了在器件层之上引入牺牲栅极氧化物和牺牲栅极之后透过线6-6'的图5的结构的截面。
图9示出了在对牺牲栅极构图，对器件层的暴露部分进行掺杂以及在所述结构上淀积电介质层之后图8的结构的顶面正面透视图。
图10示出了在暴露出电介质层内的牺牲栅极之后图9的结构。
图11示出了计算装置的示意图。
具体实施方式
描述了半导体器件以及用于形成和使用半导体器件的方法。还针对CMOS实现描述了由诸如III-V族半导体材料(对于NMOS而言)和锗材料(对于PMOS而言)的材料在硅上形成的NMOS器件和PMOS器件的相互集成。还介绍了减少缺陷向器件层的扩散的技术。
图1示出了包括非平面金属氧化物半导体场效应晶体管(MOSFET)的硅或SIO衬底的部分的实施例。例如，结构100是集成电路或芯片的部分。具体而言，图1示出了集成在用于CMOS的衬底上的两个三栅极器件。应当认识到，衬底可以含有很多其他这样的器件以及不同的器件(例如，平面器件)。参考图1，结构100包括由硅或SIO构成的衬底110。覆盖硅衬底110的是缓冲层120。在一个实施例中，缓冲层120是将按照接下来的描述受到修改的硅锗缓冲层，例如，Si0.3Ge0.7材料，在一个实施例中，所述缓冲层是通过生长技术引入到衬底110上的。缓冲层120具有几百纳米(nm)的代表性厚度。
在一个实施例中，将n型晶体管器件130和p型晶体管器件140设置到缓冲层120的表面上(如图所示)。N型晶体管器件130包括设置在缓冲层120的表面125上的鳍1310。鳍1310的代表材料是III-V族化合物半导体材料，例如，砷化铟镓(InGaAs)材料。在一个实施例中，鳍1310具有大于高度尺寸的长度L。代表性长度范围为10nm到1毫米(mm)的数量级，代表性高度范围为5nm到200nm的数量级。n型晶体管器件130的鳍1310是从缓冲层120的表面延伸的三维体。图1将所述三维体示为矩形体，但是应当认识到，在对这样的体进行处理的过程中，凭借可用的工具可能无法获得精确的矩形外形，而且可以产生其他的形状。代表性形状包括但不限于梯形(底部宽于顶部以及拱形)。
在鳍1310上面覆盖着栅极电介质层1330，其典型地由高K材料构成，例如但不限于氧化铝(Al2O3)或氧化铪(HfO2)，在栅极氧化物层上面覆盖着栅极1320，其具有大约3nm的代表性厚度。
在栅极电介质层1330上面覆盖着栅极1320。例如，栅极1320是金属材料，所述金属材料可以是但不限于金属氮化物、金属碳化物、金属硅化物、铪、锆、钛、钽、铝、钌、钯、铂、钴或镍。
栅极1320借助于设置在栅极下面的一侧的沟道区将器件的源极区和漏极区隔开。将沟道区设置到栅极下面的鳍1310内。通过这种方式，电流将不再向平面晶体管操作那样在栅极下面的平面内流动，而是如图所示在鳍的顶面和相对的侧壁上流动。
图1还示出了p型晶体管器件140，其为(例如)形成于缓冲层120的表面上的三维器件。P型晶体管器件140包括被示为具有矩形的鳍1410。在一个实施例中，P型鳍1410是锗材料。在鳍1410上面覆盖着栅极电介质层1430，其典型地由可以是但不限于Al2O3或HfO2的高K材料构成，其典型厚度约为3nm。在栅极电介质1430上面覆盖着(例如)由具有上文所述的材料的金属栅极构成的栅极1420。与n型器件类似，将栅极1420设置到鳍1410的源极区和漏极区之间，将鳍1410的沟道区设置到栅极的下面。
为了指示CMOS构造，将器件130和器件140的栅极和漏极示为已连接。
图2示出了半导体结构的另一实施例。与结构100类似，结构200包括三维MOSFET器件。更具体而言，描述了栅极全围绕(GAA)FET。参考图2，结构200包括衬底210，即硅或SOI。在衬底210上覆盖着缓冲层220，其由(例如)将按照接下来的描述修改的硅锗材料(例如，Si0.3Ge0.7缓冲材料)构成。n型器件230和p型器件240.位于缓冲层220的表面225上。N型器件230包括多个按照堆叠布置(一个摞一个)对准的鳍。在这一实施例中，n型器件230包括鳍2310A、2310B、2310C。应当认识到诸如n型器件230的GAA FET可以具有3个以下的鳍(例如，两个鳍)或者3个以上的鳍(例如，4个鳍、5个鳍等)。在一个实施例中，每一鳍是诸如InGaAs的III-V族化合物半导体材料。如图所示，每一鳍具有大于高度尺寸H的长度尺寸L。围绕每一鳍2310A、2310B、2310C的是栅极电介质材料2330A、2330B和2330C，其典型地由诸如Al2O3或HfO2的高K材料构成，其具有3nm左右的代表性厚度。栅极2320由(例如)上文所述的金属材料构成，其覆盖在栅极氧化物材料上面并且环绕相应鳍的每一侧面。栅极2320将每一鳍2310A、2310B、2310C的源极区和漏极区隔开，并在它们的相应源极区和漏极区之间界定了沟道。在栅极2320完全环绕沟道的情况下，电流能够在鳍2310A、2310B和2310C的每者的四面流动。
图2的结构220还示出了p型器件240。在这一实施例中，器件240包括堆叠布置的三个鳍(一个摞一个)。应当认识到诸如p型器件240的GAAFET可以具有3个以下的鳍(例如，两个鳍)或者3个以上的鳍(例如，4个鳍、5个鳍等)。鳍2410A、2410B和2410C的代表性材料为锗(Ge)。分别以诸如Al2O3或HfO2的高K材料为代表性材料的栅极电介质材料2430A、2430B和2430C围绕每一鳍2410A、2410B和2410C。由(例如)金属材料构成的栅极2420覆盖栅极电介质材料并且围绕每一鳍。栅极2420界定了鳍2410A、2410B和2410C中的每者当中的源极区和漏极区，还界定了源极区和漏极区之间的沟道区。
为了对CMOS实现进行举例说明，将n型器件230的栅极2320连接至p型器件240的栅极2420。还对每一器件的漏极区进行连接。
在图2中，将n型器件230和p型器件240中的每者示为包括矩形或长方体形状的鳍和栅极。应当认识到可以设想其他形状或者在对这样的结果或体的处理当中，借助于可用的工具可能无法获得精确的矩形外形，并且可能得到其他形状。代表性的例子包括但不限于圆化的形状、类似于基座(pedestal)的形状(其中，所述结构中间窄，顶部和/或底部宽)、类似于心脏的形状(例如，要么顶面要么底面存在凹痕的形状)、类似于针垫的形状(例如，在顶表面和底表面上都有凹痕的形状)以及梯形。
在上文相对于图1和图2描述的实施例中，描述了处于硅或SOI结构上的三维器件。为了使如图所示的每一器件中的器件层(例如鳍)中的缺陷降至最低，通过在形成器件之前沿鳍长度方向以及垂直于鳍长度方向俘获缺陷的方式制作所述器件。一种可以实现这一目的的方式是将这样的缺陷俘获到受到修改的缓冲层的体积内。
图3示出了包括衬底基础和位于衬底基础上的缓冲材料的结构的顶面正视图。参考图3，结构300包括衬底310，例如，其由硅或SOI构成。在这一实施例中，在衬底310上面覆盖缓冲层320，其由(例如)硅锗缓冲材料(例如，Si0.3Ge0.7)构成。在一个实施例中，对于n型和p型器件而言，要形成到所述结构上的用于缓冲层320的材料都是常见的。图3示出了在被指定为用于一个或多个n型器件的区域内形成于缓冲层320内的阱沟槽。阱沟槽350具有使得其长度L1小于其高度H1的尺寸，并且所述沟槽的宽度W1小于其高度H1。在一个实施例中，阱沟槽350具有约大于100纳米(nm)的代表性高度H1，大约60nm的长度L1以及大约40nm或50nm的宽度W1。在另一实施例中，L1和W1可以是类似的，例如，每者60nm，其用以描述双向陷获或者方形沟槽陷获的证实。图1还示出了在缓冲层320的上方表面(如图所示)内横向(沿宽度方向)形成的沟槽隔离(STI)340。在一个实施例中，STI 340界定了阱沟槽350的长度尺寸L1，并且将界定将要在缓冲层320上形成的一个或多个鳍的长度尺寸。最后，图3示出了衬在阱沟槽350的壁上的间隔体材料360。在一个实施例中，间隔体材料360是具有5nm的代表性厚度的氮化硅。
图4示出了在阱沟槽350内引入了n型材料之后图3的结构。一种适于引入到阱沟槽350内的n型材料是具有高带隙特性的材料。位于器件层下面的高带隙材料将倾向于使电荷局限到有源层内。在一个实施例中，还对阱材料370加以选择，从而使其具有与器件层的特征匹配的晶格特征，或者介于器件层和缓冲层320之间。代表性材料是III-V族化合物半导体材料，例如，磷化铟(InP)。一种将阱材料370引入到阱沟槽350内的方式是采用分子束外延(MBE)、金属有机气相处延(MOVPE)或金属有机化学气相淀积(MOCVD)在所述沟槽内生长材料。对阱材料370的引入使得阱的宽度和长度尺寸保持比阱沟槽350的高度小得多。使阱材料370的宽度和长度尺寸比高度尺寸小得多允许沿阱的侧壁俘获缺陷，并遏制缺陷达到所形成的阱的表面。代表性地，在诸如硅、锗、砷化镓、砷化铟镓的面心立方晶体中，线位错(TD)倾向于在<110>方向内沿{111}面滑移。{111}面相对于{100}面大约成55°角。因而，如果沟槽纵横比高度/宽度以及高度/长度大于1.5左右(等于α的正切，其中，α为54.7o)，那么TD能够终止于阱材料370的侧壁上。
图5示出了在缓冲层320的上方表面上构图之后图4的结构。在一个实施例中，STI 380界定了在缓冲层上形成的鳍的长度和宽度尺寸。STI层380界定了用于n型器件的处于阱材料370之上的有源区以及与阱材料370相邻的用于p型器件的区域。代表性地，STI 380界定的有源区的宽度为10nm到20nm。代表性地，STI 380的厚度或高度尺寸是在阱材料370以及用于一个或多个p型器件的缓冲层320的对应阱之上可达100nm。
图5还示出了在STI 380界定的有源区内引入器件层之后的结构300。在所描述的实施例中，在有源区内形成多个鳍，从而代表性地形成与图2类似的栅极全围绕结构。图5示出了在p型有源区内一个叠一个并且通过牺牲层387A、387B和387C隔开的有源器件层385A、385B和385C。在一个实施例中，有源器件层385A、385B和385C是存在压缩应变的Ge，其具有大约5nm的厚度或高度以及大约10nm到15nm的宽度。在一个实施例中，SiGe牺牲层387A、387B和387C每者具有大约15nm的厚度或高度。
在n型有源区内处于阱材料370之上的是一个叠一个并且通过牺牲层隔开的有源器件层390A、390B和390C。在一个实施例中，有源器件层390A、390B和390C是III-V族化合物半导体材料，例如，InGaAs，每一层具有大约5nm的厚度以及大约10nm到15nm的宽度。代表性地，设置在有源器件层390A、390B和390C之间的牺牲层395A、395B和395C是具有大约15nm的厚度或高度的InP材料。
图6示出了贯穿线6-6'的结构300的截面。图7示出了贯穿图5的线7-7'的结构300的截面。在图6中，n型区和p型区两者都是可以看到的。在图7中，只有n型区是可以看到的。参考图6，在p型区内，图6示出了有源器件层385A、385B和385C，例如，其由存在应变的Ge材料构成，所述层均通过牺牲层387A、387B和387C隔开，例如，所述牺牲层由类似于缓冲层320的材料的SiGe构成。图6还示出了n型区内的由III-V族化合物半导体材料构成的有源器件层390A、390B和390C，由(例如)InP材料构成的牺牲层395A、395B和395C设置在相应的有源器件层之间。在一个实施例中，所述有源器件层(在p型区和n型区两者内)具有大约10nm的代表性宽度WA。所述p型区有源器件层被示为与n型区有源器件层隔开所述宽度的两倍的距离2WA。如图所示在最下面的牺牲层395C的下面，图6还示出了任选的补充缓冲层398，其提供了类似或等同的与有源器件层390A、390B和390C的晶格匹配。在一个实施例中，补充缓冲材料398是砷化铟铝(InAlAs)。
参考图7，在一个实施例中，有源器件层390A、390B和390C具有大约100nm的长度LA。每一阱的有源器件层和牺牲层的堆叠的代表性高度HA约为(例如)100nm。
图8示出了贯穿(例如)图5中的线6-6'的结构300的截面图，并且示出了两个有源器件层堆叠，一个为p型，一个为n型。在形成有源器件层之后，通过借助于(例如)蚀刻去除与器件层堆叠相邻的STI 380而露出所述堆叠。其后继之以牺牲栅极氧化物层405和由(例如)多晶硅材料构成的栅极410的引入。毯式淀积牺牲栅极氧化物层405和牺牲栅极材料410，并采用(例如)等离子体蚀刻工艺对其构图，从而在有源器件层385A-385C以及390A-390C之上复制预期栅极/栅极电介质结构的尺寸。
在紧随形成牺牲栅极/栅极电介质的构图之后，可以在牺牲栅极410的侧壁上形成由(例如)氮化硅构成的间隔体415并在有源器件层385A-385C以及有源器件层390A-390C中执行掺杂(例如，顶端和/或源极类型及漏极类型掺杂)。图9示出了紧随电介质层420的引入之后的图8的结构，例如，所述电介质层420为氧化物，其覆盖牺牲栅极410、间隔体415以及有源器件层385A-385C和390A-390C的露出部分。
在紧随电介质层420的形成之后，通过(例如)对电介质层420抛光暴露出牺牲栅极410和间隔体415。之后，通过(例如)蚀刻去除牺牲栅极410和牺牲栅极氧化物层405，以暴露有源器件层385A-385C和有源器件层390A-390C的沟道部分，如图10所示。
去除居间牺牲层387A、387B和387C的部分，从而留下有源器件层385A、385B和385C，并且去除牺牲层395B和395C，从而留下有源器件层390A、390B和390C。可以通过选择性湿法蚀刻完成这样的去除，接下来器件制造进行至向每一有源器件层385A、385B和385C以及有源器件层390A、390B和390C的沟道区的周围引入(例如)高栅极电介质材料。其后继之以预期栅极材料的引入，例如，p结构的p型金属栅极和n结构的n型金属栅极。可以通过在对n型区域加以保护的同时引入p型栅极材料以及在对p型区域加以保护的同时引入n型金属栅极而形成这样的栅极。最后，在所形成的器件的栅极和漏极区之间制作接触，以提供CMOS构造。图2中示出了最终的构造。此时也可以添加其他接触(例如，源极接触)。
图11示出了根据本发明的一种实现的计算装置400。计算装置400包含板402。所述板402可以包括很多部件，其包括但不限于处理器404和至少一个通信芯片406。将处理器404物理和电耦合至板402。在一些实施方式中，所述至少一个通信芯片406还物理和电耦合至板402。在其他实施方式中，通信芯片406是处理器404的部分。
根据其应用，计算装置400可以包括其他部件，这些部件可以物理和电耦合至母板402，也可以不存在这样的耦合。这些其他部件包括但不限于易失性存储器(例如，DRAM)、非易失性存储器(例如，ROM)、闪速存储器、图形处理器、数字信号处理器、密码处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编码译码器、视频编译码器、功率放大器、全球定位系统(GPS)装置、罗盘、加速度计、陀螺仪、扬声器、照相机和大容量存储装置(例如，硬盘驱动器、紧致磁盘(CD)、数字通用盘(DVD)等)。
通信芯片406能够实现无线通信，从而进行往返于计算装置400的数据转移。“无线”一词及其派生词可以用来描述利用调制电磁辐射通过非固态介质进行数据通信的电路、装置、系统、方法、技术、通信信道等。该词并非暗示相关装置不含有任何布线，但是在一些实施例中它们可能不含有。通信芯片406可以实施很多无线标准或协议中的任何标准或协议，其包括但不限于Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙及其衍生产物以及任何其他被指定为3G、4G、5G和更高代的无线协议。计算装置400可以包括多个通信芯片406。例如，第一通信芯片406可以专用于较短范围的无线通信，例如，Wi-Fi和蓝牙，第二通信芯片406可以专用于较长范围的无线通信，例如，GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO及其他。
计算装置400的处理器404包括封装在处理器404内的集成电路管芯。在本发明的一些实施方式中，处理器的集成电路管芯包括一个或多个根据文中的实施形成的器件，例如，晶体管和CMOS实现。“处理器”一词可以指任何对来自寄存器和/或存储器的电子数据进行处理从而将该电子数据变换为其他可以存储在寄存器和/或存储器内的其他电子数据的装置或装置的部分
通信芯片406还包括封装在通信芯片406内的集成电路管芯。根据另一实施方式，所述通信芯片的集成电路管芯包括一个或多个根据上文描述的实施方式形成的器件，例如，晶体管和CMOS实现。
在其他实施方式中，计算装置400内包含的另一部件可以含有集成电路管芯，所述集成电路管芯包括一个或多个根据上文描述的实施方式形成的器件，例如，晶体管和CMOS实现。
在不同的实施方式中，计算装置400可以是膝上型电脑、上网本、笔记本、超级本、智能电话、平板电脑、个人数字助理(PDA)、超级移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字照相机、便携式音乐播放器或者数字视频记录仪。在其他实施方式中，计算装置400可以是任何其他处理数据的电子装置。
在上述说明中，出于解释的目的，阐述了很多具体的细节，以提供对实施例的透彻的理解。但是，对于本领域技术人员而言，显然能够在不需要这些具体细节中的某些的情况下实践一个或多个其他实施例。提供所描述的具体实施例的目的并非对本发明进行限定，而是对本发明进行举例说明。本发明的范围不由上文提供的具体例子决定，而是仅由下面的权利要求决定。在其他情况下，只是通过方框图的形式而未详细地示出公知的结构、器件和操作，以避免模糊对所述描述的理解。在适当的情况下，在附图中采用重复的附图标记或者附图标记的末尾部分来表示对应的和相似的要素，所述要素可以任选具有类似的特征。
还应当认识到，在本说明书中通篇对“一个实施例”、“实施例”、“一个或多个实施例”或者“不同实施例”的引述意味着(例如)在对本发明的实践当中可能包含特定特征。类似地，应当认识到，在说明书中，出于简化公开以及促进对本发明的各个方面中的一者或多者的理解的目的，有时可以在单个实施例、图示或其说明中将本发明的各种特征结合到一起。但是，不应将这种公开方法解释成反映了这样的意图，即本发明所需要的特征比每一权利要求中明确表述的特征多。相反，如下述权利要求所反映的，本发明的各个方面可以存在于单个公开实施例的所有特征中的部分特征中。因而，在此将紧接着具体实施方式的权利要求书明确包含到这一具体实施方式部分内，其中，每一权利要求本身代表本发明的独立的实施例。

Claims (15)

1.一种设备，包括：
半导体器件，其包括具有第一晶格结构的沟道材料，所述沟道材料位于由具有匹配的晶格结构的阱材料构成的阱上，所述阱被设置在具有不同于所述第一晶格结构的第二晶格结构的缓冲材料内，其中，所述阱包括高度比宽度的纵横比以及高度比长度的纵横比，所述纵横比均大于1.5。
2.根据权利要求1所述的设备，其中，所述半导体器件包括n型金属氧化物半导体场效应晶体管，所述n型金属氧化物半导体场效应晶体管包括由所述沟道材料构成的源极区和漏极区。
3.根据权利要求1所述的设备，其中，所述沟道材料是III-V族化合物半导体材料。
4.根据权利要求3所述的设备，其中，所述缓冲材料包括锗。
5.根据权利要求1所述的设备，其中，所述半导体器件是包括n型金属氧化物半导体场效应晶体管的第一半导体器件，所述设备还包括第二半导体器件，所述第二半导体器件包括形成在所述缓冲材料上的p型金属氧化物半导体场效应晶体管。
6.根据权利要求5所述的设备，其中，所述n型晶体管通过每个器件的栅极和漏极而被连接至所述p型晶体管。
7.一种方法，包括：
在衬底的缓冲材料内形成阱沟槽，所述阱具有大于1.5的高度比宽度的纵横比以及高度比长度的纵横比；
在所述阱沟槽内形成n型阱材料，所述n型阱材料的晶格结构不同于所述缓冲材料的晶格结构；
在所述阱材料上界定用于n型器件的沟道和结区的区域；以及
在所界定的区域内形成包括沟道和结区的n型晶体管。
8.根据权利要求7所述的方法，其中，通过沟槽隔离界定用于沟道和结区的区域。
9.根据权利要求7所述的方法，其中，所述n型阱材料是III-V族化合物半导体材料。
10.根据权利要求9所述的方法，其中，所述缓冲材料包括锗。
11.根据权利要求7所述的方法，还包括：
在所述阱材料上界定用于p型器件的沟道和结区的p型区域；以及
在所界定的p型区域内形成包括沟道和结区的p型晶体管。
12.根据权利要求11所述的方法，其中，所述n型晶体管包括栅极，所述p型晶体管包括栅极，每个晶体管的结区包括源极区和漏极区，所述方法还包括：
将所述n型晶体管通过每个器件的所述栅极和所述漏极而连接至所述p型晶体管。
13.一种系统，包括：
包括电耦合至印刷电路板的处理器的计算机，所述处理器包括互补金属氧化物半导体(CMOS)电路，所述互补金属氧化物半导体电路包括n型晶体管和p型晶体管，所述n型晶体管包括沟道材料，所述沟道材料具有第一晶格结构并且位于设置在缓冲材料内的阱上，所述缓冲材料具有不同于所述第一晶格结构的第二晶格结构，其中，所述阱包括均大于1.5的高度比宽度的纵横比以及高度比长度的纵横比，其中，所述n型晶体管通过每个器件的栅极和漏极而耦合至所述p型晶体管。
14.根据权利要求12所述的系统，其中，所述n型晶体管的沟道材料是III-V族化合物半导体材料。
15.根据权利要求12所述的系统，其中，所述缓冲材料包括锗。
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US9666583B2 (en) 2017-05-30
CN104603947B (zh) 2018-07-24
US9112028B2 (en) 2015-08-18
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WO2014051769A1 (en) 2014-04-03
US20150270265A1 (en) 2015-09-24
EP2901489B1 (en) 2022-05-25
KR20150038401A (ko) 2015-04-08
US8716751B2 (en) 2014-05-06
US20140091361A1 (en) 2014-04-03
US20140231871A1 (en) 2014-08-21

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