CN104601151A - Power on/off detection reset circuit - Google Patents
Power on/off detection reset circuit Download PDFInfo
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- CN104601151A CN104601151A CN201510011728.9A CN201510011728A CN104601151A CN 104601151 A CN104601151 A CN 104601151A CN 201510011728 A CN201510011728 A CN 201510011728A CN 104601151 A CN104601151 A CN 104601151A
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Abstract
The invention relates to a power on/off detection reset circuit. The circuit comprises a bias circuit module used for offering the electric current according to the adjustable electric current source and generating the first bias electric current and the second bias electric current; a reference voltage module used for generating the reference voltage according to the first bias electric current; a comparison circuit module used for generating the threshold voltage according to the second bias electric current and comparing the power voltage with the reference voltage according to the threshold voltage and judging whether the power supply is on or off according to the comparing result; a reset signal generating module used for generating the reset signal while judging the power supply is in the on/off state and outputting the reset signal. The power on/off detection reset circuit is used for detecting and resetting the off/on state of the circuit, the circuit is simple, the implementation is flexible and the power consumption is low.
Description
Technical field
The present invention relates to electronic circuit field, particularly relate to a kind of power on/off and detect reset circuit.
Background technology
Electronic system is in the process of power on/off, due to different circuit modules may be there is, so power on/off Time Inconsistency, and then system is caused to occur the phenomenon of work confusion instantaneously in power on/off, in order to prevent the appearance of this phenomenon, power on/off can be added detect reset circuit in some circuit modules.Power on/off detects reset circuit when system generation power-off or energising being detected, can send reset signal, then reset to circuit, thus make system enter predetermined state.Traditional power on/off detects reset circuit and generally there is the higher shortcoming of complex structure, power consumption.
Summary of the invention
The invention provides a kind of power on/off and detect reset circuit, in order to realize resetting to the detection of Circuit Interrupt electricity and energising, circuit is simple, realizes flexibly, low in energy consumption.
The invention provides a kind of power on/off and detect reset circuit, comprising:
Biasing circuit module, for the electric current provided according to adjustable current source, generates the first bias current and the second bias current;
Reference voltage module, for according to described first bias current, generating reference voltage;
Comparison circuit module, for according to described second bias current, generates threshold voltage, compares supply voltage and described reference voltage, judge whether power supply power-off or energising occur according to comparative result according to described threshold voltage;
Reset signal generation module, for when judging described power supply generation power-off or energising, generating reset signal, exports described reset signal.
The present invention designs a kind of power on/off and detects reset circuit, biasing circuit module generates the first bias current and the second bias current according to the electric current that adjustable current source provides, can be whole power on/off detection reset circuit and bias current is provided, the first bias current generating reference voltage that reference voltage module provides according to biasing circuit module, the threshold voltage generated according to the second bias current in comparison circuit module compares supply voltage and reference voltage, judge whether power supply power-off or energising occur according to comparative result, if power supply generation power-off or energising, then reset signal generation module generates and exports reset signal, if there is not power-off or energising in power supply, then reset signal generation module generates and exports and represents the normal signal of power supply, the detection of such realization to power cut-off and energising resets, circuit is simple, realize flexibly.And by the adjustable current source in biasing circuit module, can according to the demand adjustment electric current of each circuit module, the minimum current selecting guarantee circuit normally to work just can realize whole power on/off and detect the function resetted, and realizes low-power consumption.
Accompanying drawing explanation
Fig. 1 is the structural representation that power on/off of the present invention detects reset circuit first embodiment;
Fig. 2 is the structural representation that power on/off of the present invention detects reset circuit second embodiment;
Fig. 3 is the curve chart that power on/off of the present invention detects different voltage in reset circuit second embodiment.
Embodiment
Below in conjunction with specification drawings and specific embodiments, the invention will be further described.
As shown in Figure 1, for power on/off of the present invention detects the structural representation of reset circuit first embodiment, this circuit can comprise: biasing circuit module 11, reference voltage module 12, comparison circuit module 13 and reset signal generation module 14, reference voltage module 12 is connected with biasing circuit module 11, and comparison circuit module 13 is connected with reference voltage module 12.
In the present embodiment, the electric current of biasing circuit module 11 for providing according to adjustable current source, generates the first bias current and the second bias current; Reference voltage module 12 is for according to the first bias current generating reference voltage Vref; Comparison circuit module 13, for according to the second bias current, generates threshold voltage, compares supply voltage VDD and reference voltage Vref, judge whether power supply power-off or energising occur according to comparative result according to threshold voltage; When reset signal generation module 14 is for judging power supply generation power-off or energising, generating reset signal, exports this reset signal, when judging that power supply is normal, generating and representing the normal signal of power supply, export and represent the normal signal of power supply.
In the present embodiment, the first bias current and the second bias current is generated according to the electric current that adjustable current source provides by biasing circuit module 11, can be whole power on/off detection reset circuit and bias current is provided, the first bias current generating reference voltage Vref that reference voltage module 12 provides according to biasing circuit module 11, supply voltage VDD and reference voltage Vref is compared by the threshold voltage generated according to the second bias current in comparison circuit module 13, judge whether power supply power-off or energising occur by result, if power supply generation power-off or energising, then reset signal generation module 14 generates and exports reset signal, if there is not power-off or energising in power supply, namely power supply is normal, then reset signal generation module 14 generates and exports and represents the normal signal of power supply, the detection of such realization to power cut-off and energising resets, circuit is simple, realize flexibly.Due to the current adjustment that adjustable current source provides, so the first bias current of obtaining of the electric current that can be provided by adjustable current source according to the adjustment of the demand of each circuit module and the second bias current, select to ensure that the minimum current that circuit normally works just can realize the function that whole power on/off detects reset, thus realize low-power consumption.
Alternatively, schematic diagram shown in Figure 1 again, biasing circuit module 11 can comprise: adjustable current source I1, first PMOS M1, second PMOS M2, 3rd NMOS tube M3, 4th NMOS tube M4, the positive pole of adjustable current source I1 is connected to ground, the negative pole of adjustable current source I1 is connected with the drain electrode of the first PMOS M1, the source electrode of the first PMOS M1, the source electrode of the second PMOS M2 is all connected with supply voltage VDD, the grid of the first PMOS M1 is with drain electrode short circuit and be connected with the grid of the second PMOS M2, the grid of the 3rd NMOS tube M3, source electrode is all connected to ground, the source electrode of the 4th NMOS tube M4 is connected to ground, grid and the drain electrode short circuit of the 4th NMOS tube M4.Wherein, the electric current that can be provided by the implementation adjustment adjustable current source I1 changing adjustable current source I1, adjustable current source I1 has multiple implementation, such as: realize adjustable current source I1 with a resistance, just by the adjustment of resistance realization to electric current of adjusting resistance, thus can obtain adjustable first bias current and the second bias current, the electric current that first PMOS M1 provides according to adjustable current source transmits the first bias current to reference voltage module 12, the electric current that second PMOS M2 provides according to adjustable current source transmits the second bias current to the 4th NMOS tube M4, and the 4th NMOS tube M4 transmits the second bias current to comparison circuit module 13, the grid of 3rd NMOS tube M3 for the protection of the first PMOS M1 and the voltage at drain electrode short circuit place, particularly, when power-off occurs, in the process that supply voltage VDD declines, the grid of the first PMOS M1 also can along with decline with the voltage at drain electrode short circuit place, because the grid of the first PMOS M1 and the voltage at drain electrode short circuit place are lower than supply voltage VDD, so when supply voltage VDD is down to 0V, the grid of the first PMOS M1 can lower than 0V with the voltage at drain electrode short circuit place, there is overshoot phenomenon, if the brownout at the grid of the first PMOS M1 and drain electrode short circuit place, parasitic diode between the drain electrode of the 3rd NMOS tube M3 and substrate will conducting, like this will by the substrate of the 3rd NMOS tube M3 to the grid of the first PMOS M1 and drain electrode short circuit Injection Current, thus prevent the voltage at the grid of the first PMOS M1 and the short circuit place that drains well below 0V.
Alternatively, in the present embodiment, reference voltage module 12 is for being applied to field-effect transistor by the first bias current, generating reference voltage Vref, particularly, schematic diagram shown in Figure 1 again, reference voltage module 12 can comprise: the 5th PMOS M5, reference voltage generation unit 121, the source electrode of the 5th PMOS M5 is connected with supply voltage VDD, the grid of the 5th PMOS M5 is connected with drain electrode short circuit place with the grid of the first PMOS M1, the drain electrode of the 5th PMOS M5 is connected with reference voltage generation unit 121, reference voltage generation unit 121 is connected to ground.Wherein, 5th PMOS M5 and the first PMOS M1 forms mirror current source for reference voltage generation unit 121 provides the first bias current, reference voltage generation unit 121 comprises above-mentioned field-effect transistor, reference voltage Vref is the voltage on field-effect transistor, the conducting under the effect of the first bias current of this field-effect transistor, according to the first bias current generating reference voltage Vref.
Alternatively, in the present embodiment, the two or more metal-oxide-semiconductor that in reference voltage generation unit 121, field-effect transistor can be 1 metal-oxide-semiconductor or be connected in series, reference voltage Vref be voltage on each metal-oxide-semiconductor and, due to only each metal-oxide-semiconductor conducting need be ensured in circuit, so the first bias current can be very little, so the voltage on metal-oxide-semiconductor is approximately equal to the cut-ff voltage of this metal-oxide-semiconductor, then reference voltage Vref is the cut-ff voltage sum of each metal-oxide-semiconductor.Further, due to the number of metal-oxide-semiconductor can be regulated in reference voltage generation unit 121, so the size of reference voltage Vref can regulate.
Particularly, field-effect transistor can be 1 PMOS, then the source electrode of PMOS is connected with the drain electrode of the 5th PMOS M5, and the grid of PMOS is with drain electrode short circuit and be connected to ground, field-effect transistor can also be 1 NMOS tube, then the grid of NMOS tube and drain electrode short circuit being connected with the drain electrode of the 5th PMOS M5, and the source electrode of NMOS tube is connected to ground, field-effect transistor can also be 2 PMOS, i.e. PMOS P1 and PMOS P2, then the source electrode of PMOS P1 is connected with the drain electrode of the 5th PMOS M5, and the grid of PMOS P1 is with drain electrode short circuit and is connected with the source electrode of PMOS P2, the grid of PMOS P2 with drain short circuit being connected to ground, field-effect transistor can also be 2 NMOS tube, i.e. NMOS tube N1 and NMOS tube N2, the then grid of NMOS tube N1 and drain electrode short circuit being connected with the drain electrode of the 5th PMOS M5, the grid of NMOS tube N2 with drain short circuit being connected with the source electrode of NMOS tube N1, the source electrode of NMOS tube N2 is connected to ground, field-effect transistor can also be 1 PMOS and 1 NMOS tube, if PMOS P3 and NMOS tube N4, then the source electrode of PMOS P3 is connected with the drain electrode of the 5th PMOS M5, the grid of PMOS P3 is with drain electrode short circuit and be connected with the drain electrode of NMOS tube N4, grid and the drain electrode short circuit of NMOS tube N4, the source electrode of NMOS tube N4 is connected to ground, if NMOS tube N3 and PMOS P4, the then grid of NMOS tube N3 and drain electrode short circuit being connected with the drain electrode of the 5th PMOS M5, the source electrode of NMOS tube N3 is connected with the source electrode of PMOS P4, the grid of PMOS P4 is with drain electrode short circuit and be connected to ground, field-effect transistor can also be the combination of two or more PMOS or two or more NMOS tube or two or more PMOS and two or more NMOS tube, and its connected mode can refer to above-mentioned introduction, specifically repeats no more.
Alternatively, in the present embodiment, comparison circuit module 13 is for being applied to field-effect transistor by the second bias current, generate threshold voltage, now, threshold voltage is the cut-ff voltage on field-effect transistor, the difference between supply voltage VDD and reference voltage Vref and threshold voltage is compared, according to comparative result, judge whether power supply power-off or energising occur.Particularly, schematic diagram shown in Figure 1 again, comparison circuit module 13 can comprise: the 6th PMOS M6, the 7th NMOS tube M7, the source electrode of the 6th PMOS M6 is connected with supply voltage VDD, the grid of the 6th PMOS M6 is connected with the drain electrode of the 5th PMOS M5, the drain electrode of the 6th PMOS M6 is connected with the drain electrode of the 7th NMOS tube M7 and is connected with reset signal generation module 14, and the grid of the 7th NMOS tube M7 is connected with the grid of the 4th NMOS tube M4, and the source electrode of the 7th NMOS tube M7 is connected to ground.Wherein, the 7th NMOS tube M7 and the 4th NMOS tube M4 forms mirror current source provides the second bias current for the 6th PMOS M6, then obtain the cut-ff voltage V that threshold voltage is the 6th PMOS M6
tH6; When power supply generation power-off or energising, the difference of supply voltage VDD and reference voltage Vref is less than threshold voltage, and namely (VDD-Vref) is less than the cut-ff voltage V of the 6th PMOS M6
tH6time, now the 6th PMOS M6 closes, under the effect of the impedance of the second bias current and the 6th PMOS M6, the voltage of the junction of the drain electrode of the 6th PMOS M6 and the drain electrode of the 7th NMOS tube M7 is zero, therefore, be zero can judge power supply generation power-off or energising according to the voltage of the junction of the drain electrode of the 6th PMOS M6 and the drain electrode of the 7th NMOS tube M7; When power supply is normal, the difference of supply voltage VDD and reference voltage Vref is more than or equal to threshold voltage, and namely (VDD-Vref) is more than or equal to the cut-ff voltage V of the 6th PMOS M6
tH6time, 6th PMOS M6 is in conducting and conducting resistance is very little, under the conducting resistance effect of the second bias current and the 6th PMOS, the voltage of the junction of the drain electrode of the 6th PMOS M6 and the drain electrode of the 7th NMOS tube M7 equals supply voltage VDD, therefore, equal supply voltage VDD according to the voltage of the junction of the drain electrode of the 6th PMOS M6 and the drain electrode of the 7th NMOS tube M7 and can judge that power supply is normal, power-off or energising do not occur.
It should be noted that, in the present embodiment, voltage on the line that above-mentioned reference voltage Vref is the threshold voltage sum of each metal-oxide-semiconductor, voltage on the line of the drain electrode of the drain electrode of the 6th PMOS M6 and the 7th NMOS tube M7 is the drain electrode of the zero, the 6th PMOS M6 and the drain electrode of the 7th NMOS tube M7 equals the situations such as supply voltage VDD, all approximate scopes when practical application, can be approximately equal to, might not be equal to, but this affect the present invention detects reset effect to power on/off.
Alternatively, in the present embodiment, reset signal generation module 14 is specifically as follows Schmidt trigger, and the drain electrode of the 6th PMOS M6 is connected with the drain electrode of the 7th NMOS tube M7 and is connected with Schmidt trigger.When power supply generation power-off or energising, Schmidt trigger generates and exports reset signal; When power supply is normal, Schmidt trigger exports and represents the normal signal of power supply.Particularly, when power supply generation power-off or energising, Schmidt trigger output logic 0; When power supply is normal, Schmidt trigger output logic 1.This feature of strong anti-interference can be added according to Schmidt trigger, select Schmidt trigger can prevent in power-off or galvanization owing to disturbing the misoperation caused, or prevent the power-off because interference causes or energising from detecting unsuccessfully, ensure power-off or the reliable and stable of testing that be energized.
Alternatively, then schematic diagram shown in Figure 1, power on/off detects reset circuit can also comprise drive circuit module 15, and drive circuit module 15 is connected with reset signal generation module 14, for driving subsequent conditioning circuit according to reset signal.If the signal that reset signal generation module 14 exports is digital signal, logical zero as escribed above or logical one, drive circuit module 15 can realize by gate, and circuit is simple.
As shown in Figure 2, for power on/off of the present invention detects the structural representation of reset circuit second embodiment, be with the difference of Fig. 1, in the present embodiment, reference voltage generation unit 121 is specially 2 PMOS, i.e. PMOS P1 and PMOS P2, and these two PMOS are duplicate, so the cut-ff voltage V of PMOS P1
tH1with the cut-ff voltage V of PMOS P2
tH2equal, the source electrode of PMOS P1 is connected with the drain electrode of the 5th PMOS M5, and the grid of PMOS P1 is with drain electrode short circuit and is connected with the source electrode of PMOS P2, the grid of PMOS P2 with drain short circuit being connected to ground; Reset signal generation module 14 is specially Schmidt trigger D1, and the drain electrode of the 6th PMOS M6 is connected with the drain electrode of the 7th NMOS tube M7 and is connected with Schmidt trigger D1; Adjustable current source I1 specifically adopts resistance R1 to realize.
In the present embodiment, circuit carry out power on/off detect reset operation principle be: in biasing circuit module 11, the electric current that adjustable current source I1 provides is I
r=V1/R1, wherein V1 is the grid of the first PMOS M1 and the voltage at drain electrode short circuit place, from electric current I
rformula in can find out, if think electric current I
rdiminish, only need increase resistance R1 can realize.In reference voltage module 12, the 5th PMOS M5 and the first PMOS M1 forms mirror current source for PMOS P1 and PMOS P2 provides the first bias current, reference voltage Vref be the gate source voltage of PMOS P1 and PMOS P2 and, i.e. Vref=V
gS1+ V
gS2, so can by regulating the size adjustment reference voltage Vref of gate source voltage of PMOS P1 and PMOS P2, only need PMOS P1 and PMOS P2 conducting because of in module for this reason, so the first bias current can be very little, V
gS1+ V
gS2be approximately equal to the cut-ff voltage V of PMOS P1
tHP1with the cut-ff voltage V of PMOS P2
tHP2and, then reference voltage Vref is approximately equal to 2*V
tHP1.In comparison circuit module 13, the 7th NMOS tube M7 and the 4th NMOS tube M4 forms mirror current source for the 6th PMOS M6 provides the second bias current, then threshold voltage is the cut-ff voltage V of the 6th PMOS M6
tH6if the 6th PMOS M6 and PMOS P1 is just the same, then V
tH6=V
tHP1, the difference of supply voltage VDD and reference voltage Vref is (VDD-Vref), can judge power supply whether power-off by comparing (VDD-Vref) and threshold voltage.Particularly, when power supply generation power-off, supply voltage VDD reduces gradually, reference voltage Vref is substantially constant, so the difference of supply voltage VDD and reference voltage Vref (VDD-Vref) reduces gradually, when the difference (VDD-Vref) of supply voltage VDD and reference voltage Vref is less than threshold voltage, namely supply voltage VDD power supply is less than 3*V
tHP1time, 6th PMOS M6 closes, under the effect of the second bias current now provided at the 7th NMOS tube M7 and the impedance of the 6th PMOS M6, the voltage of the junction of the drain electrode of the 6th PMOS M6 and the drain electrode of the 7th NMOS tube M7 is close to 0V, then judge power supply generation power-off, Schmidt trigger D1 generates and exports reset signal logical zero; When power supply is normal, the value of the difference (VDD-Vref) of supply voltage VDD and reference voltage Vref is more than or equal to threshold voltage, and namely supply voltage VDD is more than or equal to 3*V
tHP1time, 6th PMOS M6 is now in the state of conducting and conducting resistance is very little, so the voltage of the junction of the drain electrode of the 6th PMOS M6 and the drain electrode of the 7th NMOS tube M7 is approximately equal to supply voltage VDD under the conducting resistance effect of the second bias current and the 6th PMOS M6, then judge that power supply is in normal condition, now Schmidt trigger D1 generates and output logic 1.
Similarly, in the present embodiment, energising detects the operation principle resetted: when energising occurs power supply, when supply voltage VDD increases gradually from 0, the grid of the first PMOS M1 and the voltage at drain electrode short circuit place are also along with increasing gradually, and biasing circuit module 11 is started working, and in reference voltage module 12, reference voltage Vref is set up gradually and keeps, when the difference (VDD-Vref) of supply voltage VDD and reference voltage Vref is less than threshold voltage, namely supply voltage VDD is less than 3*V
tHP1time, the 6th PMOS M6 closes, and the voltage of the junction of the now drain electrode of the 6th PMOS M6 and the drain electrode of the 7th NMOS tube M7 close to 0V, then judges that power supply is energized, and Schmidt trigger D1 generates and output logic 0, circuit reset; When supply voltage VDD increase to make the difference of supply voltage VDD and reference voltage Vref (Vdd-Vref) be more than or equal to threshold voltage time, namely supply voltage VDD is more than or equal to 3*V
tHP1time, the 6th PMOS M6 conducting, the voltage of the junction of the drain electrode of the 6th PMOS M6 and the drain electrode of the 7th NMOS tube M7 is approximately equal to supply voltage VDD, and Schmidt trigger D1 generates and output logic 1, resets and terminates.
From the above, in this example, when circuit normally works, first bias current and the second bias current all need the metal-oxide-semiconductor conducting ensureing to make in circuit module, so the first bias current and the second bias current all smaller, so the operating current of circuit integrity can be very little, in practical application, even can reach pA level, can low-power consumption be realized.
Schematic diagram shown in Figure 2 again, the grid of the first PMOS M1 is V1 with the voltage at drain electrode short circuit place, and the voltage of the drain electrode of the 6th PMOS M6 and the drain connections of the 7th NMOS tube M7 is V2.As shown in Figure 3, for power on/off of the present invention detects the curve chart of different voltage in reset circuit second embodiment, heavy line is supply voltage VDD, fine line is reference voltage Vref, short-term shape dotted line is the grid of the first PMOS M1 and the voltage V1 at drain electrode short circuit place, dotted line is the voltage V2 of the drain electrode of the 6th PMOS M6 and the drain connections of the 7th NMOS tube M7, the dash area on the left side represents that power supply is energized, middle dash area represents power cut-off, and the dash area on the right represents overshoot phenomenon.The grid of the first PMOS M1 changes along with the change of supply voltage VDD with the voltage V1 at drain electrode short circuit place; but all the time lower than supply voltage VDD; when supply voltage VDD is down to 0V; the grid of the first PMOS M1 just there will be aforesaid overshoot phenomenon with the voltage V1 at drain electrode short circuit place, by the protective effect of the 3rd NMOS tube M3, the voltage V1 at the grid of the first PMOS M1 and drain electrode short circuit place is gone back up near 0V.In energising testing process, along with the increase of supply voltage VDD, the voltage V2 of the drain electrode of the 6th PMOS M6 and the drain connections of the 7th NMOS tube M7 is reaching 3*V
tHP1be approximately 0V, the 6th PMOS M6 closes, and circuit reset, the voltage V2 of the drain electrode of the 6th PMOS M6 and the drain connections of the 7th NMOS tube M7 reaches 3*V instantaneously at t1 before
tHP1, afterwards along with the continuation of supply voltage VDD increases, the 6th PMOS M6 conducting, circuit reset terminates, and the voltage V2 of the drain electrode of the 6th PMOS M6 and the drain connections of the 7th NMOS tube M7 is finally approximately equal to supply voltage VDD; In outage detection process, along with the decline of supply voltage VDD, the voltage V2 of the drain electrode of the 6th PMOS M6 and the drain connections of the 7th NMOS tube M7 also along with decline, and reaches 3*V in the t2 time
tHP16th PMOS M6 closes afterwards, due to the effect of the impedance of the second bias current and the 6th PMOS M6, the voltage V2 of the drain electrode of the 6th PMOS and the drain connections of the 7th NMOS tube M7 reduces instantaneously close to 0V, then Schmidt trigger D1 exports reset signal logical zero.Reference voltage Vref was set up with the voltage V1 at drain electrode short circuit place at the grid of galvanization along with the first PMOS M1 increased gradually before t1, and it is constant to remain on certain value, is reduced to 0V gradually after t 2.
Last it is noted that above embodiment is only in order to illustrate technical scheme of the present invention and unrestricted, although with reference to preferred embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that, can modify to technical scheme of the present invention or equivalent replacement, and not depart from the spirit and scope of technical solution of the present invention.
Claims (9)
1. power on/off detects a reset circuit, it is characterized in that, comprising:
Biasing circuit module, for the electric current provided according to adjustable current source, generates the first bias current and the second bias current;
Reference voltage module, for according to described first bias current, generating reference voltage;
Comparison circuit module, for according to described second bias current, generates threshold voltage, compares supply voltage and described reference voltage, judge whether power supply power-off or energising occur according to comparative result according to described threshold voltage;
Reset signal generation module, for when judging described power supply generation power-off or energising, generating reset signal, exports described reset signal.
2. circuit according to claim 1, is characterized in that, described reference voltage module, for described first bias current is applied to field-effect transistor, generates described reference voltage.
3. circuit according to claim 1, it is characterized in that, described comparison circuit module is for being applied to field-effect transistor by described second bias current, generate described threshold voltage, difference between described supply voltage and described reference voltage and described threshold voltage are compared, according to comparative result, judge whether power supply power-off or energising occur.
4. circuit according to claim 1, it is characterized in that, described biasing circuit module comprises described adjustable current source, first PMOS, second PMOS, 3rd NMOS tube, 4th NMOS tube, the positive pole of described adjustable current source is connected to ground, the negative pole of described adjustable current source is connected with the drain electrode of described first PMOS, the source electrode of described first PMOS, the source electrode of described second PMOS is all connected with power supply, the grid of described first PMOS is with drain electrode short circuit and be connected with the grid of described second PMOS, the grid of described 3rd NMOS tube, source electrode is all connected to ground, the source electrode of described 4th NMOS tube is connected to ground, grid and the drain electrode short circuit of described 4th NMOS tube,
The electric current that described first PMOS provides according to described adjustable current source, transmits described first bias current to described reference voltage module; The electric current that described second PMOS provides according to described adjustable current source, transmits described second bias current to described 4th NMOS tube; Described 4th NMOS tube transmits described second bias current to described comparison circuit module.
5. circuit according to claim 2, it is characterized in that, described reference voltage module comprises the 5th PMOS, reference voltage generation unit, the source electrode of described 5th PMOS is connected with described power supply, the grid of described 5th PMOS is connected with drain electrode short circuit place with the grid of described first PMOS, the drain electrode of described 5th PMOS is connected with described reference voltage generation unit, and described reference voltage generation unit is connected with described;
Described 5th PMOS and described first PMOS form mirror current source for described reference voltage generation unit provides described first bias current;
Described reference voltage generation unit comprises described field-effect transistor, and described field-effect transistor generates described reference voltage according to described first bias current.
6. circuit according to claim 5, is characterized in that, the two or more metal-oxide-semiconductor that described field-effect transistor is 1 metal-oxide-semiconductor or is connected in series.
7. the circuit according to claim 3,4 or 5, it is characterized in that, described comparison circuit module comprises the 6th PMOS, the 7th NMOS tube, the source electrode of described 6th PMOS is connected with described power supply, the grid of described 6th PMOS is connected with the drain electrode of described 5th PMOS, the drain electrode of described 6th PMOS is connected with the drain electrode of described 7th NMOS tube and is connected with described reset signal generation module, the grid of described 7th NMOS tube is connected with the grid of described second PMOS, and the source electrode of described 7th NMOS tube is connected with described;
Described 7th NMOS tube and described 4th NMOS tube form mirror current source for described 6th PMOS provides described second bias current;
When the difference of described supply voltage and described reference voltage is less than described threshold voltage, described 6th PMOS is closed, under the effect of the impedance of described second bias current and described 6th PMOS, the voltage of the junction of the drain electrode of described 6th PMOS and the drain electrode of described 7th NMOS tube is zero, described power supply generation power-off or energising;
When the difference of described supply voltage and described reference voltage is more than or equal to described threshold voltage, described 6th PMOS is in conducting, under the conducting resistance effect of described second bias current and described 6th PMOS, the voltage of the junction of the drain electrode of described 6th PMOS and the drain electrode of described 7th NMOS tube equals described supply voltage, and described power supply is normal.
8. circuit according to claim 7, is characterized in that, described reset signal generation module is specially Schmidt trigger, and the drain electrode of described 6th PMOS is connected with the drain electrode of described 7th NMOS tube and is connected with described Schmidt trigger;
When described power supply generation power-off or energising, described Schmidt trigger generates and exports reset signal; When described power supply is normal, described Schmidt trigger exports and represents the normal signal of described power supply.
9. circuit according to claim 1, is characterized in that, described power on/off detects reset circuit and also comprises drive circuit module, and described drive circuit module is connected with described reset signal generation module, for driving subsequent conditioning circuit according to described reset signal.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105159391A (en) * | 2015-10-22 | 2015-12-16 | 杭州士兰微电子股份有限公司 | Current source and oscillating circuit utilizing same |
| CN106027006A (en) * | 2016-05-18 | 2016-10-12 | 上海华虹宏力半导体制造有限公司 | Power-on reset circuit |
| CN108964644A (en) * | 2017-05-19 | 2018-12-07 | 三星电子株式会社 | Power on/off reset circuit and reset signal generating circuit including the power on/off reset circuit |
| CN110007706A (en) * | 2018-01-04 | 2019-07-12 | 智原科技股份有限公司 | Core power detection circuit and input/output control system |
| CN114679163A (en) * | 2020-12-24 | 2022-06-28 | 圣邦微电子（北京）股份有限公司 | Power-on reset circuit and integrated circuit |
| CN118646403A (en) * | 2024-08-14 | 2024-09-13 | 深圳市爱普特微电子有限公司 | Input interface circuit supporting multiple input voltages |
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| CN105159391A (en) * | 2015-10-22 | 2015-12-16 | 杭州士兰微电子股份有限公司 | Current source and oscillating circuit utilizing same |
| CN106027006A (en) * | 2016-05-18 | 2016-10-12 | 上海华虹宏力半导体制造有限公司 | Power-on reset circuit |
| CN108964644A (en) * | 2017-05-19 | 2018-12-07 | 三星电子株式会社 | Power on/off reset circuit and reset signal generating circuit including the power on/off reset circuit |
| CN108964644B (en) * | 2017-05-19 | 2023-06-30 | 三星电子株式会社 | Power-on/power-off reset circuit and reset signal generation circuit including the same |
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| CN114679163B (en) * | 2020-12-24 | 2024-08-30 | 圣邦微电子（北京）股份有限公司 | Power-on reset circuit and integrated circuit |
| CN118646403A (en) * | 2024-08-14 | 2024-09-13 | 深圳市爱普特微电子有限公司 | Input interface circuit supporting multiple input voltages |
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Application publication date: 20150506 |