CN104601131B - Receipt signal strength automatic gain control method for gas ultrasonic flow meter transducer - Google Patents
Receipt signal strength automatic gain control method for gas ultrasonic flow meter transducer Download PDFInfo
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Abstract
Disclosed is a receipt signal strength automatic gain control method for a gas ultrasonic flow meter transducer. A used system comprises a digital signal processor (DSP), a field programmable gate array (FPGA), a transmitting transducer, a receiving transducer, a digital-analog (DA) converter, an AD converter, a power amplification circuit and a digital gain control circuit. The first output end of the DSP is connected with the first input end of the FPGA, the first output end of the FPGA is connected with the input end of the DA converter, the output end of the DA converter is connected with the input end of the transmitting transducer through the power amplification circuit, the transmitting transducer is used for sending ultrasonic pulse signals to the receiving transducer, the output end of the receiving transducer is connected with the input end of the AD converter through the digital gain control circuit which is connected with the DSP, the output end of the AD converter is connected with the second input end of the FPGA, and the second output end of the FPGA is connected with the DSP which is connected with a memorizer. By the aid of the method, the measurement accuracy is improved.
Description
Technical field
The present invention relates to Ultrasonic Wave Flowmeter field, more particularly, to a kind of Ultrasonic Wave Flowmeter transducer reception
Signal intensity auto gain control method.
Background technology
Ultrasonic Wave Flowmeter adopts time difference method to measure gas flow rate, and ultimate principle is measurement ultrasonic pulse pleasant
Time difference in body flow direction and inverse gas flow direction reacting flow velocity, thus measuring flow.Fig. 9 show supersonic flow
The schematic diagram of gauge time difference method velocity measurement, starts transmission pulse from first transducer and receives pulse signal to second transducer
Time is t1, and the time receiving pulse signal to first transducer from second transducer transmission pulse is t2.The difference of t1 and t2
For t, it is as shown in Equation 1 with fluids within pipes flow velocity relation:
In formula, c is ultrasound wave speed in a fluid, and D is two ultrasonic transducers and pipe level side for pipe diameter θ
To angle.From formula 1, when in stationary gas, spread speed is regarded as constant to ultrasound wave, rate of flow of fluid is just and the time
Difference t is directly proportional, and measurement t can get flow velocity, and then tries to achieve gas flow.
The transducer drive frequency of Ultrasonic Wave Flowmeter is 200K Hz, far below liquid ultrasonic low
1MHz, this is because decay in gas for the ultrasonic pulse is very big, more highly attenuating more of frequency.And test and show,
In the case of driving end signal strength constant, the receiving end signal intensity of gas ultrasound wave transducer can constantly decline over time
Subtract, after curstomer's site applies three months, receipt signal measured value decreases 40% to the transducer of applicant company.Can think
As As time goes on, the signal of transducer can be more and more weaker, until being unable to correct measurement flow velocity.Therefore, it is necessary to realize
Even if a kind of can change the design of amplifying circuit gain so that connecing automatically according to gas ultrasound wave transducer received signal strength
Receiver signal intensity significantly weakens, and system can also ensure enough sample signal strength by automatic gain control circuit.
Content of the invention
The present invention be directed to the deficiencies in the prior art, there is provided a kind of Ultrasonic Wave Flowmeter transducer receipt signal is strong
Degree auto gain control method, the method can solve Ultrasonic Wave Flowmeter transducer signal intensity over time and fast
Speed weakens and affects the problem of flow-speed measurement, by the dynamic bind of transmitting terminal gain control and receiving end signal gain control,
Solve the problems, such as signal non-linear distortion during only receiving terminal gain control, improve the accuracy of measurement.
The present invention is that the technical scheme solving above-mentioned technical problem employing is：A kind of Ultrasonic Wave Flowmeter transducer connects
Receive signal intensity auto gain control method, employ following system, this system includes DSP data processor, FPGA circuitry, sends out
Penetrate transducer, receive transducer, D/A converter, AD converter, power amplification circuit, digital gain control circuit, memorizer,
First outfan of described DSP data processor is connected with the first input end of FPGA circuitry, and the first of described FPGA circuitry is defeated
Go out end to be connected with the input of D/A converter, the outfan of described D/A converter is defeated through power amplification circuit and transmitting transducer
Enter end to connect, described transmitting transducer is used for sending ultrasonic pulsative signal to receive transducer, the output of described receive transducer
End is connected with AD converter input through digital gain control circuit, described AD converter outfan and the second of FPGA circuitry
Input connects, and the second outfan of described FPGA circuitry is connected with DSP data processor, and the of described DSP data processor
Two outfans are connected with digital gain control circuit, and described DSP data processor is connected with memorizer；
The method realizing Ultrasonic Wave Flowmeter flow-speed measurement using said system, comprises the following steps：
1) in memory the storage reference amplitude of received signal strength, initial driving amplitude, maximum drive amplitude and
Drive the increment of amplitude, the reference amplitude according to received signal strength sets to meet and drives the threshold values requiring；
2) start ultrasonic flowmeter and carry out flow-speed measurement, DSP data processor send initial driving amplitude order to
FPGA；
3) FPGA transmits the sinusoid information of respective strengths to DA according to the order of DSP data processor, and DA output is corresponding
The sine wave signal of frequency and amplitude drives transmitting transducer after power amplification；
4) receive transducer receives the signal generation piezoelectricity conversion of transmitting transducer, exports receipt signal, receipt signal warp
Digital gain control circuit is input to AD converter, and the AD sampled value of FPGA oversampling A/D-converter is simultaneously transferred at DSP data
Reason device；
5) DSP data processor judges whether the AD sampled value of receipt signal meets the threshold values of setting；
51) when the AD sampled value of the receipt signal detecting when DSP data processor meets the threshold values of setting, DSP data
Processor requirement FPGA continues, with the output of this sinusoidal magnitude data-driven DA, to complete flow-speed measurement；
52) when the AD sampled value of the receipt signal detecting when DSP data processor does not meet the threshold values of setting, DSP number
Continue to judge whether DA output amplitude reaches the maximum drive amplitude of setting according to processor；
521) if DA output amplitude is not reaching to the maximum drive amplitude setting, DSP data processor steps taken is：
On the basis of initial driving amplitude, it is continuously increased the amplitude of D/A converter sine wave output drive signal with the increment setting,
The driving energy that transmitting terminal transducer is obtained is made to strengthen, receiving end signal intensity also strengthens, meanwhile, DSP data processor is examined
Whether the AD sampled value surveying each receipt signal reaches the threshold values of setting, when the amplitude of D/A converter sine wave output drive signal
When increasing to an amplitude, now, DSP data processor detects the threshold values that receiving end signal intensity increases to set, then DSP number
According to processor requirement FPGA, DA output is driven with the sine wave drive signal of this amplitude, complete flow-speed measurement；
522) if DA amplitude reaches the maximum drive amplitude of setting, DSP data processor steps taken is：DSP number
Realize the amplification of transducer receiving end signal intensity according to processor by the amplification increasing digital gain control circuit, from
And so that the input signal of AD converter is strengthened, when the crest voltage that AD converter detects after amplifying through signal reaches the valve of setting
Value, DSP data processor using this amplification as the acquiescence gain amplifier of receipt signal, completes flow-speed measurement, and by its
Write memorizer.
Step 1) meeting of middle setting drive the threshold values requiring to be located in the range of the 80%～90% of reference amplitude.
Step 1) in the initial driving amplitude that sets be 4V, maximum drive amplitude is 8V, and the increment of driving amplitude is 0.5V.
Described digital gain control circuit includes active filter, digital gain-controlled amplifier, digital gain
The receipt signal of control circuit receive transducer after filtering, amplify after export to AD converter.
Described DSP data processor adopts the data processor of model TMS320F28335.
Described FPGA circuitry adopts the fpga chip of model EP4CE10.
Described D/A converter adopts the digital to analog converter of model AD9760AR.
Described AD converter adopts the analog-digital converter of model ADC12DL040CIVS.
Described power amplification circuit includes amplifier U24, current amplifier U25 and some resistance, electric capacity, described amplifier
The in-phase input end of U24 is connected with one end of the 76th resistance R76, the other end of the 76th resistance R76 respectively with the 77th electricity
One end of resistance R77, one end of the 85th electric capacity C85 connect, the other end ground connection of the 77th resistance R77, the 85th electric capacity C85's
The other end is connected with one end of the outfan of D/A converter, one end of the 74th resistance R74, the 84th electric capacity C84 respectively, and the 74th
The other end of individual resistance R74, the other end of the 84th electric capacity C84 are all grounded, and the inverting input of described amplifier U24 is respectively with
One end of 75 resistance R75, one end of the 78th resistance R78 connect, the other end ground connection of the 75th resistance R75, the 78th electricity
The other end of resistance R78 is connected with the outfan of amplifier U24, and the outfan of amplifier U24 is through the 79th resistance R79 and current amplifier
The input of U25 connects, and the outfan of current amplifier U25 is connected with transmitting transducer.
Described memorizer is EE memorizer, model FM25L04 of described EE memorizer.
The present invention having the beneficial effect that using technique scheme：Because the transmitting terminal that the present invention adopts transducer drives by force
Degree and the method for receiving end signal intensity gain dynamic bind, realize the automatic gain of Ultrasonic Wave Flowmeter transducer signal
Control so that when transducer receiving end signal is attenuated to certain threshold value, AGC system intervention measurement process so that
Received signal strength meet measurement requirement and will not distortion, solve Ultrasonic Wave Flowmeter transducer signal intensity at any time
Between passage and weaken rapidly and affect the problem of flow-speed measurement, solve the non-linear mistake of signal during only receiving terminal gain control
True problem, improves the accuracy of measurement.
Brief description
Fig. 1 is the circuit system block diagram of the present invention；
Fig. 2 is the circuit diagram of the D/A converter of the present invention；
Fig. 3 is the circuit diagram of the power amplification circuit of the present invention；
Fig. 4 is the circuit diagram of the AD converter of the present invention；
Fig. 5 is the circuit diagram of the memorizer of the present invention；
Fig. 6 is the digital gain control circuit of the present invention；
Fig. 7 is the receiving terminal transducer sinusoidal envelope figure of the present invention；
Fig. 8 is method of the present invention flow chart；
Fig. 9 is time difference method velocity measurement schematic diagram.
Specific embodiment
The invention will be further described with reference to the accompanying drawings and examples：
Referring to Fig. 1 to Fig. 8, a kind of Ultrasonic Wave Flowmeter transducer received signal strength auto gain control method,
Employ following system, this system includes DSP data processor, FPGA circuitry, transmitting transducer, receive transducer, DA conversion
Device, AD converter, power amplification circuit, digital gain control circuit, memorizer, the first of described DSP data processor is defeated
Go out end to be connected with the first input end of FPGA circuitry, the first outfan of described FPGA circuitry is connected with the input of D/A converter
Connect, the outfan of described D/A converter is connected with the input of transmitting transducer through power amplification circuit, described transmitting transducer
For sending ultrasonic pulsative signal to receive transducer, the outfan of described receive transducer through digital gain control circuit with
AD converter input connects, and described AD converter outfan is connected with the second input of FPGA circuitry, described FPGA circuitry
The second outfan be connected with DSP data processor, the second outfan of described DSP data processor and digital gain control
Circuit connects, and described DSP data processor is connected with memorizer.
Physical circuit is described as follows：Described digital gain control circuit includes active filter, digital gain control
Amplifier, the receipt signal of digital gain control circuit receive transducer after filtering, amplify after export to AD converter.Number
The AD8370 of ADI company chosen by word formula variable gain amplifier, yield value by DSP data processor controlled, its with DSP data at
Reason device be connected with three control lines, be clock (CLK) respectively, data (DATA) and latch (LTCH).DSP data processor passes through
Write the gain code of 7 place values, it is possible to provide up to 52 times of gain, so that the input signal of AD converter strengthens.Fortune
Put the input impedance that U31A effect is to increase signal, reduce the loss of signal, make up the relatively low signal causing of AD8370 input impedance
Loss.Described digital gain control circuit adopts the digital gain-controlled amplifier of model AD8370.Digital gain
Control amplifier to select the AD8370 of ADI company, there is high-gain, the advantages of signal bandwidth is big.When AD converter detect through
When crest voltage after signal amplification reaches the 90% of reference amplitude, DSP data processor is i.e. using this gain as receipt signal
Acquiescence gain amplifier, and be written into EE memorizer.TI company selected by the DSP data processor of the system
TMS320F28335, this DSP data processor chip functions is powerful, and real-coded GA operational capability is strong, and the speed of service can reach
150M Hz, meets the system arithmetic speed and requires.FPGA selects the EP4CE10 of ALTERA company, and inside has the logic of 10k
Unit, abundant I/O port and internal phaselocked loop.Described DSP data processor adopts at the data of model TMS320F28335
Reason device.Described FPGA circuitry adopts the fpga chip of model EP4CE10.Described D/A converter adopts model AD9760AR
Digital to analog converter.Described AD converter adopts the analog-digital converter of model ADC12DL040CIVS.
Described power amplification circuit includes amplifier U24, current amplifier U25 and some resistance, electric capacity, described amplifier
The in-phase input end of U24 is connected with one end of the 76th resistance R76, the other end of the 76th resistance R76 respectively with the 77th electricity
One end of resistance R77, one end of the 85th electric capacity C85 connect, the other end ground connection of the 77th resistance R77, the 85th electric capacity C85's
The other end is connected with one end of the outfan of D/A converter, one end of the 74th resistance R74, the 84th electric capacity C84 respectively, and the 74th
The other end of individual resistance R74, the other end of the 84th electric capacity C84 are all grounded, and the inverting input of described amplifier U24 is respectively with
One end of 75 resistance R75, one end of the 78th resistance R78 connect, the other end ground connection of the 75th resistance R75, the 78th electricity
The other end of resistance R78 is connected with the outfan of amplifier U24, and the outfan of amplifier U24 is through the 79th resistance R79 and current amplifier
The input of U25 connects, and the outfan of current amplifier U25 is connected with transmitting transducer.
Described memorizer is EE memorizer, model FM25L04 of described EE memorizer.
As shown in figure 1, being the design system block diagram of the present invention, it is also the design frame chart of Ultrasonic Wave Flowmeter simultaneously.
DSP data processor is the core cell of gain control system, sends data to FPGA, and FPGA orders according to DSP data processor
Order transmission respective strengths sinusoid information such as amplitude, to DA, DA exports corresponding frequencies to frequency and the sine wave signal of amplitude drives
Transmitting transducer, there is piezoelectricity conversion in the signal that receive transducer receives transmitting transducer, piezoelectricity conversion is ultrasonic transducer
Inherent character, after transducer receives ultrasonic pulsative signal, transducer can produce piezoelectric effect, transducer two ends output
The sinusoidal envelope of certain peak value, such as Fig. 7, the amplified circuit of sinusoidal signal of output some strength to AD converter, FPGA adopts
The sampled value (maximum) of sample AD converter is simultaneously transferred to DSP data processor, through corresponding data filtering, draws after process
Gas flow rate.
Referring to Fig. 8, the method that Ultrasonic Wave Flowmeter flow-speed measurement is realized using said system, comprise the following steps：
1) in memory the storage reference amplitude of received signal strength, initial driving amplitude, maximum drive amplitude and
Drive the increment of amplitude, the reference amplitude according to received signal strength sets to meet and drives the threshold values requiring.Step 1) middle setting
Meet drive require threshold values be located at reference amplitude 80%～90% in the range of.Step 1) the middle initial driving width setting
It is worth for 4V, maximum drive amplitude is 8V, the increment driving amplitude is 0.5V.
2) start ultrasonic flowmeter and carry out flow-speed measurement, DSP data processor send initial driving amplitude order to
FPGA；
3) FPGA transmits the sinusoid information of respective strengths to DA according to the order of DSP data processor, and DA output is corresponding
The sine wave signal of frequency and amplitude drives transmitting transducer after power amplification.
4) receive transducer receives the signal generation piezoelectricity conversion of transmitting transducer, exports receipt signal, receipt signal warp
Digital gain control circuit is input to AD converter, and the AD sampled value of FPGA oversampling A/D-converter is simultaneously transferred at DSP data
Reason device；
5) DSP data processor judges whether the AD sampled value of receipt signal meets the threshold values of setting；
51) when the AD sampled value of the receipt signal detecting when DSP data processor meets the threshold values of setting, DSP data
Processor requirement FPGA, to continue to export with this sinusoidal magnitude data-driven DA, completes flow-speed measurement；
52) when the AD sampled value of the receipt signal detecting when DSP data processor does not meet the threshold values of setting, DSP number
Continue to judge whether DA output amplitude reaches the maximum drive amplitude of setting according to processor；
521) if DA output amplitude is not reaching to the maximum drive amplitude setting, DSP data processor steps taken is：
On the basis of initial driving amplitude, it is continuously increased the amplitude of D/A converter sine wave output drive signal with the increment setting,
The driving energy that transmitting terminal transducer is obtained is made to strengthen, receiving end signal intensity also strengthens, meanwhile, DSP data processor is examined
Whether the AD sampled value surveying each receipt signal reaches the threshold values of setting, when the amplitude of D/A converter sine wave output drive signal
When increasing to an amplitude, now, DSP data processor detects the threshold values that receiving end signal intensity increases to set, then DSP number
According to processor requirement FPGA, DA output is driven with the sine wave drive signal of this amplitude, complete flow-speed measurement；
522) if DA amplitude reaches the maximum drive amplitude of setting, DSP data processor steps taken is：DSP number
Realize the amplification of transducer receiving end signal intensity according to processor by the amplification increasing digital gain control circuit, from
And so that the input signal of AD converter is strengthened, when the crest voltage that AD converter detects after amplifying through signal reaches the valve of setting
Value, DSP data processor using this amplification as the acquiescence gain amplifier of receipt signal, completes flow-speed measurement, and by its
Write memorizer.Initial amplification is 2, increases by 10% every time, until amplified crest voltage reaches on the basis of previous
To given threshold.Amplification setting is realized by the digital interface of DSP data processor controlled AD8370.
The flow-speed measurement idiographic flow of the present invention is as follows：DSP data processor reads and is stored in EE memorizer when dispatching from the factory
Received signal strength reference amplitude information.Control measurement by the driving end signal and receiving end signal yield value of factory default
Process, when detect received signal strength be less than reference amplitude information 85% when, typically transducer signal decays 80%～
After 90%, the accuracy of supersonic flow quantity algorithm can be greatly lowered, the median 85% of the range of choice therefore in this example.Above-mentioned
Receiving terminal transducer signal input after digital controlled gain circuit, AD converter, this value of FPGA quick sampling is simultaneously transferred to
DSP data processor.DSP data processor order FPGA with 4V as initial value, on this basis with certain increment, here
Increment is fixed as 0.5V, increases the amplitude of D/A converter sine wave output drive signal.The driving that transmitting terminal transducer is obtained
Energy also strengthens therewith, and receiving end signal intensity also strengthens.If now receiving end signal intensity increases to reference amplitude
90%, when amplitude be more than reference amplitude 90% when can basic guarantee ultrasonic flow calculate accuracy.Certainly according to different factories
This value of transducer of family needs actual measurement adjustment.So DSP data processor judges that now amplitude can meet requirement, and requires
FPGA is exported with sinusoidal magnitude data-driven DA now, completes flow-speed measurement.If receiving end signal intensity is not reaching to
90%, the DSP data processor order FPGA of reference amplitude continues to output the data making D/A converter increase sinusoidal magnitude, when
When DA amplitude reaches 8V, it is set to the Power Limitation that 8V is because transmitted waveform drive signal, the power supply electricity of power amplification circuit
Press for 12V 600 milliamperes, when driving transducer, electric current can reach 500 milliamperes it is contemplated that the fall volume of power supply uses, and chooses 8V
Highest driving voltage.Receiving end signal intensity again without reaching the 90% of reference amplitude, for reducing drive circuit power consumption, DSP
Data processor order FPGA no longer exports the data making D/A converter sine wave output amplitude increase, but by increasing numeral
The amplification of formula gain control circuit realizes the amplification of transducer receiving end signal intensity, and digital gain control circuit is chosen
The AD8370 of ADI company, by DSP data processor controlled, it is connected with three control lines with DSP data processor to yield value,
Clock (CLK) respectively, data (DATA) and latch (LTCH).DSP data processor passes through to write the gain code of 7 place values,
Up to 52 times of gain can be provided.So that the input signal of AD converter strengthens.When AD converter detects through signal
When crest voltage after amplification reaches the 90% of reference amplitude, DSP data processor is i.e. silent as receipt signal using this gain
Recognize gain amplifier, and be written into EE memorizer.
This method can automatically change the design of amplifying circuit gain according to gas ultrasound wave transducer received signal strength,
Even if so that receiving end signal intensity significantly weakens, system can also ensure enough samplings by automatic gain control circuit
Signal intensity.
Claims (10)
1. a kind of Ultrasonic Wave Flowmeter transducer received signal strength auto gain control method it is characterised in that：Using
Following system, this system includes DSP data processor, FPGA circuitry, transmitting transducer, receive transducer, D/A converter, AD
Transducer, power amplification circuit, digital gain control circuit, memorizer, the first outfan of described DSP data processor with
The first input end of FPGA circuitry connects, and the first outfan of described FPGA circuitry is connected with the input of D/A converter, described
The outfan of D/A converter is connected with the input of transmitting transducer through power amplification circuit, and described transmitting transducer is used for sending
, to receive transducer, the outfan of described receive transducer is through digital gain control circuit and AD converter for ultrasonic pulsative signal
Input connects, and described AD converter outfan is connected with the second input of FPGA circuitry, and the second of described FPGA circuitry is defeated
Go out end to be connected with DSP data processor, the second outfan of described DSP data processor is with digital gain control circuit even
Connect, described DSP data processor is connected with memorizer；
The method realizing Ultrasonic Wave Flowmeter flow-speed measurement using said system, comprises the following steps：
1) reference amplitude of storage received signal strength, initial driving amplitude, maximum drive amplitude and driving in memory
The increment of amplitude, the reference amplitude according to received signal strength sets to meet and drives the threshold values requiring；
2) start ultrasonic flowmeter and carry out flow-speed measurement, DSP data processor sends initial driving amplitude order to FPGA；
3) FPGA transmits the sinusoid information of respective strengths to D/A converter, D/A converter according to the order of DSP data processor
The sine wave signal of output corresponding frequencies and amplitude drives transmitting transducer after power amplification；
4) receive transducer receives the signal generation piezoelectricity conversion of transmitting transducer, exports receipt signal, receipt signal is through numeral
Formula gain control circuit is input to AD converter, and the AD sampled value of FPGA oversampling A/D-converter is simultaneously transferred to DSP data processor；
5) DSP data processor judges whether the AD sampled value of receipt signal meets the threshold values of setting；
51) when the AD sampled value of the receipt signal detecting when DSP data processor meets the threshold values of setting, DSP data processing
Device requires FPGA to continue to drive D/A converter output with the amplitude data of this sine wave, completes flow-speed measurement；
52) when the AD sampled value of the receipt signal detecting when DSP data processor does not meet the threshold values of setting, at DSP data
Reason device continues to judge whether D/A converter output amplitude reaches the maximum drive amplitude of setting；
521) if D/A converter output amplitude is not reaching to the maximum drive amplitude setting, DSP data processor steps taken
It is：On the basis of initial driving amplitude, it is continuously increased the width of D/A converter sine wave output drive signal with the increment setting
Value, makes the driving energy that transmitting terminal transducer is obtained strengthen, receiving end signal intensity also strengthens, meanwhile, DSP data processor
Detect whether the AD sampled value of each receipt signal reaches the threshold values of setting, when the width of D/A converter sine wave output drive signal
When value increases to an amplitude, now, DSP data processor detects the threshold values that receiving end signal intensity increases to set, then DSP
Data processor requires FPGA to drive D/A converter output with the sine wave drive signal of this amplitude, completes flow-speed measurement；
522) if DA amplitude reaches the maximum drive amplitude of setting, DSP data processor steps taken is：At DSP data
The amplification of transducer receiving end signal intensity realized by reason device by the amplification increasing digital gain control circuit, so that
The input signal of AD converter strengthens, when the crest voltage that AD converter detects after amplifying through signal reaches the threshold values of setting,
DSP data processor using this amplification as the acquiescence gain amplifier of receipt signal, completes flow-speed measurement, and is written into
Memorizer.
2. Ultrasonic Wave Flowmeter transducer received signal strength auto gain control method according to claim 1,
It is characterized in that：Step 1) meeting of middle setting drive the threshold values requiring to be located in the range of the 80%～90% of reference amplitude.
3. Ultrasonic Wave Flowmeter transducer received signal strength auto gain control method according to claim 1,
It is characterized in that：Step 1) in the initial driving amplitude that sets be 4V, maximum drive amplitude is 8V, and the increment of driving amplitude is
0.5V.
4. Ultrasonic Wave Flowmeter transducer received signal strength auto gain control method according to claim 1,
It is characterized in that：Described digital gain control circuit includes active filter, digital gain-controlled amplifier, digital increasing
The receipt signal of beneficial control circuit receive transducer after filtering, amplify after export to AD converter.
5. Ultrasonic Wave Flowmeter transducer received signal strength auto gain control method according to claim 1,
It is characterized in that：Described DSP data processor adopts the data processor of model TMS320F28335.
6. Ultrasonic Wave Flowmeter transducer received signal strength auto gain control method according to claim 1,
It is characterized in that：Described FPGA circuitry adopts the fpga chip of model EP4CE10.
7. Ultrasonic Wave Flowmeter transducer received signal strength auto gain control method according to claim 1,
It is characterized in that：Described D/A converter adopts the digital to analog converter of model AD9760AR.
8. Ultrasonic Wave Flowmeter transducer received signal strength auto gain control method according to claim 1,
It is characterized in that：Described AD converter adopts the analog-digital converter of model ADC12DL040CIVS.
9. Ultrasonic Wave Flowmeter transducer received signal strength auto gain control method according to claim 1,
It is characterized in that：Described power amplification circuit includes amplifier (U24), current amplifier (U25) and some resistance and electric capacity, institute
The in-phase input end stating amplifier (U24) is connected with one end of the 76th resistance (R76), and the other end of the 76th resistance (R76) divides
It is not connected with one end of the 77th resistance (R77), one end of the 85th electric capacity (C85), another termination of the 77th resistance (R77)
Ground, the other end of the 85th electric capacity (C85) respectively with the outfan of D/A converter, one end of the 74th resistance (R74), the 84th
One end of electric capacity (C84) connects, and the other end of the 74th resistance (R74), the other end of the 84th electric capacity (C84) are all grounded, institute
The inverting input stating amplifier (U24) is connected with one end of the 75th resistance (R75), one end of the 78th resistance (R78) respectively,
The other end ground connection of the 75th resistance (R75), the other end of the 78th resistance (R78) is connected with the outfan of amplifier (U24), fortune
The outfan putting (U24) is connected with the input of current amplifier (U25) through the 79th resistance (R79), current amplifier (U25)
Outfan be connected with transmitting transducer.
10. Ultrasonic Wave Flowmeter transducer received signal strength auto gain control method according to claim 1,
It is characterized in that：Described memorizer is EE memorizer, model FM25L04 of described EE memorizer.
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| CN104931588A (en) * | 2015-05-15 | 2015-09-23 | 合肥华欣自控设备成套有限公司 | kilomega network communication-based multichannel ultrasonic parallel high-speed acquisition hardware system |
| CN105043509B (en) * | 2015-05-22 | 2018-04-20 | 重庆川仪自动化股份有限公司 | The detection method and detecting system of liquid ultrasonic wave flowmeter |
| CN115096408A (en) * | 2022-05-10 | 2022-09-23 | 陕西航天动力高科技股份有限公司 | Automatic gain adjustment system and ultrasonic measurement and transducer health diagnosis method |
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