CN204359406U - The resonance frequency test macro of ultrasonic flowmeter transducer - Google Patents

Abstract

A resonant frequency testing system for ultrasonic flowmeter transducers, including DSP, FPGA circuit, transmitting transducer, receiving transducer, DA converter, AD converter, power amplifier circuit, memory, DSP is used to test command Pass it to the FPGA circuit, the FPGA circuit is used to receive the test command of the DSP, and output the data sequence to the DA converter, and the DA converter is used to receive the data sequence of the FPGA circuit and output sine wave signals of different frequencies to drive the transmitting transducer. It is used to send the ultrasonic pulse signal to the receiving transducer. The receiving transducer is used to receive the ultrasonic pulse signal of the transmitting transducer for piezoelectric conversion, and output a sinusoidal signal with a certain peak value to the AD converter. The FPGA circuit is used to sample the output of the AD converter. The sampled value is output to the DSP, and the DSP judges the point with the largest peak value in the AD sampled value, and writes the frequency value corresponding to this point into the memory as the resonance frequency.

Description

Resonant Frequency Testing System of Ultrasonic Flowmeter Transducer

technical field

The utility model relates to the driving field of ultrasonic flowmeter transducers, in particular to a resonant frequency testing system of ultrasonic flowmeter transducers.

Background technique

Ultrasonic flowmeter products usually use the time difference method to measure the fluid flow rate. The basic principle is to measure the time difference of the ultrasonic pulse in the downstream flow and the upstream flow to reflect the flow rate, so as to measure the flow rate. Figure 7 is a schematic diagram of ultrasonic flowmeter differential flow rate measurement, the time from the first transducer to send the pulse to the second transducer receives the pulse signal is t1, from the second transducer to send the pulse to the first The time when the transducer receives the pulse signal is t2. The difference between t1 and t2 is ⊿t, and its relationship with the fluid velocity in the pipeline is shown in Equation 1:

(1)

In the formula, c is the speed of ultrasonic waves in the fluid, and D is the diameter of the pipe is the angle between the two ultrasonic transducers and the horizontal direction of the pipeline. It can be seen from Equation 1 that when the propagation velocity of ultrasonic waves in a stationary fluid can be considered constant, the fluid flow velocity is proportional to the time difference ⊿t, and the flow velocity can be obtained by measuring ⊿t, and then the flow rate can be obtained.

The driving frequency of ultrasonic flowmeter transducers is fixed. For example, the driving frequency of liquid ultrasonic sensors is 1MHz, and the driving frequency of gas ultrasonic sensors is 200kHz. However, ultrasonic transducers are essentially piezoelectric crystals, and each transducer has a unique resonant frequency. Only when the driving frequency is consistent with its own resonant frequency can it be transmitted on the receiving end transducer under the same transmission power. Produces the strongest output signal and improves signal transmission performance. At present, the driving frequency of the transducer of traditional ultrasonic flowmeter products is a fixed frequency, which is not the resonant frequency of the ultrasonic transducer. At the same transmission power, the best effect of the ultrasonic transducer cannot be exerted. Therefore, it is necessary to design a resonant frequency test system for each ultrasonic flowmeter and its transducer, so that the ultrasonic flowmeter itself can test the resonant parameters of the transducer, and write the test information into the external memory as a frequency constant Fixed, you don’t need to power on to test the resonant frequency, and then read the previously written parameters from the memory.

Invention content

The utility model aims at the deficiencies of the prior art, and provides a resonant frequency testing system for ultrasonic flowmeter transducers. The system can accurately test the resonant frequency of each ultrasonic flowmeter transducer. Under the same transmission power, Using this frequency as the driving frequency of the transducer can enhance the signal strength of the receiving end of the ultrasonic transducer.

The technical solution adopted by the utility model to solve the above technical problems is: a resonant frequency test system of ultrasonic flowmeter transducer, including DSP data processor, FPGA circuit, transmitting transducer, receiving transducer, DA converter , AD converter, power amplifying circuit, memory, described DSP data processor is used for passing test order to FPGA circuit, and described FPGA circuit is used for receiving the test order of DSP data processor, output data sequence to DA converter, so The DA converter is used to receive the data sequence of the FPGA circuit and output sine wave signals of different frequencies to drive the transmitting transducer, the transmitting transducer is used to send ultrasonic pulse signals to the receiving transducer, and the receiving transducer is used to receive the transmitted The ultrasonic pulse signal of the transducer undergoes piezoelectric conversion, and a sinusoidal signal with a certain peak value is output to the AD converter. The AD converter is used to sample the sinusoidal signal received from the transducer and transmit it to the FPGA circuit. The FPGA circuit It is used to output the sampled value of the received AD converter to the DSP data processor, and the DSP data processor determines the point with the largest peak value in the AD sampled value, and writes the frequency value corresponding to this point into the memory as the resonance frequency .

The DSP data processor adopts a data processor whose model is TMS320F28335.

The FPGA circuit adopts an FPGA chip whose model is EP4CE10.

The DA converter adopts a digital-to-analog converter whose model is AD9760AR.

The AD converter adopts an analog-to-digital converter whose model is ADC12DL040CIVS.

The power amplifying circuit includes an operational amplifier (U24), a current amplifier (U25), and several resistors and capacitors. The non-inverting input terminal of the operational amplifier (U24) is connected to one end of the 76th resistor (R76), and the 76th resistor (R76) ) are respectively connected to one end of the 77th resistor (R77) and one end of the 85th capacitor (C85), the other end of the 77th resistor (R77) is grounded, and the other end of the 85th capacitor (C85) is respectively Connect to the output terminal of the DA converter, one end of the 74th resistor (R74), one end of the 84th capacitor (C84), the other end of the 74th resistor (R74), and the other end of the 84th capacitor (C84) are all grounded, the inverting input terminal of the operational amplifier (U24) is respectively connected to one end of the 75th resistor (R75) and one end of the 78th resistor (R78), and the other end of the 75th resistor (R75) is grounded, The other end of the 78th resistor (R78) is connected to the output terminal of the operational amplifier (U24), and the output terminal of the operational amplifier (U24) is connected to the input terminal of the current amplifier (U25) through the 79th resistor (R79). The current amplifier The output terminal of (U25) is connected with the transmitting transducer.

The memory is an EE memory.

The model of the EE memory is FM25L04.

The utility model has the beneficial effects of adopting the above-mentioned technical solution: because the resonance frequency test system of the ultrasonic flowmeter transducer of the present utility model includes a DSP data processor, an FPGA circuit, a transmitting transducer, a receiving transducer, and a DA converter , AD converter, power amplifying circuit, memory, described DSP data processor is used for passing test order to FPGA circuit, and described FPGA circuit is used for receiving the test order of DSP data processor, output data sequence to DA converter, so The DA converter is used to receive the data sequence of the FPGA circuit and output sine wave signals of different frequencies to drive the transmitting transducer, the transmitting transducer is used to send ultrasonic pulse signals to the receiving transducer, and the receiving transducer is used to receive the transmitted The ultrasonic pulse signal of the transducer undergoes piezoelectric conversion, and a sinusoidal signal with a certain peak value is output to the AD converter. The AD converter is used to sample the sinusoidal signal received from the transducer and transmit it to the FPGA circuit. The FPGA circuit It is used to output the sampled value of the received AD converter to the DSP data processor, and the DSP data processor determines the point with the largest peak value in the AD sampled value, and writes the frequency value corresponding to this point into the memory as the resonance frequency , used as a driving frequency constant, at the same transmission power, the best effect of the ultrasonic transducer cannot be exerted.

The utility model can accurately test the resonant frequency of each transducer of the ultrasonic flowmeter, and under the same transmission power, using the frequency as the driving frequency of the transducer can enhance the signal strength of the receiving end of the ultrasonic transducer.

Description of drawings

Fig. 1 is a system circuit diagram of the utility model;

Fig. 2 is the circuit diagram of the DA converter of the present utility model;

Fig. 3 is the circuit diagram of the power amplifying circuit of the present utility model;

Fig. 4 is the circuit diagram of the AD converter of the present utility model;

Fig. 5 is the circuit diagram of the memory of the present utility model;

Fig. 6 is the flow chart of automatic testing method of the present utility model;

Fig. 7 is a schematic diagram of flow rate measurement by time difference method.

Detailed ways

Below in conjunction with accompanying drawing and embodiment the utility model is further described:

Referring to Figures 1 to 6, an embodiment of a resonance frequency testing system for an ultrasonic flowmeter transducer, including a DSP data processor, an FPGA circuit, a transmitting transducer, a receiving transducer, a DA converter, and an AD converter , power amplifying circuit, memory, described DSP data processor is used for passing test command to FPGA circuit, and described FPGA circuit is used for receiving the test order of DSP data processor, and output data sequence is given DA converter, and described DA converter uses The data sequence of the receiving FPGA circuit outputs sine wave signals of different frequencies to drive the transmitting transducer, the transmitting transducer is used to send the ultrasonic pulse signal to the receiving transducer, and the receiving transducer is used to receive the output of the transmitting transducer The ultrasonic pulse signal undergoes piezoelectric conversion, and outputs a sinusoidal signal with a certain peak value to the AD converter. The AD converter is used to sample the sinusoidal signal of the receiving transducer and transmit it to the FPGA circuit. The sampling value of the AD converter is output to the DSP data processor, and the DSP data processor judges the point with the largest peak value in the AD sampling value, and writes the frequency value corresponding to this point into the memory as the resonance frequency.

DSP is the core unit of the system, which transmits commands for the FPGA, so that the FPGA sends corresponding data to the DA converter (the data is transmitted to the DA in 10-bit parallel mode, and these data are pre-designed sequences, through which the DA can output Set the amplitude and frequency of the sine wave, that is, the 800 K Hz~1200 kHz frequency signal referred to above), so that the DA outputs sine wave signals of different frequencies to drive the transmitting transducer, and the receiving transducer receives the signal of the transmitting transducer The signal undergoes piezoelectric conversion, and a sinusoidal signal of a certain intensity is output and input to the AD converter. FPGA samples the sampling value (maximum value) of the AD converter. The maximum value is the drive signal of the transducer at the receiving end when it receives the transducer at the transmitting end. Finally, the piezoelectric effect is generated, and a sine wave signal envelope with a certain peak value is induced. The point with the largest sine wave peak value in the envelope is the maximum value sampled by the AD converter and transmitted to the DSP. Receiver signal strength.

The specific circuit is as follows: the DSP data processor adopts a data processor whose model is TMS320F28335. The memory is an EE memory. The model of the EE memory is FM25L04. The FPGA circuit adopts an FPGA chip whose model is EP4CE10. The DA converter adopts a digital-to-analog converter whose model is AD9760AR. The AD converter adopts an analog-to-digital converter whose model is ADC12DL040CIVS.

The power amplifying circuit includes an operational amplifier (U24), a current amplifier (U25), and several resistors and capacitors. The non-inverting input terminal of the operational amplifier (U24) is connected to one end of the 76th resistor (R76), and the 76th resistor (R76) ) are respectively connected to one end of the 77th resistor (R77) and one end of the 85th capacitor (C85), the other end of the 77th resistor (R77) is grounded, and the other end of the 85th capacitor (C85) is respectively Connect to the output terminal of the DA converter, one end of the 74th resistor (R74), one end of the 84th capacitor (C84), the other end of the 74th resistor (R74), and the other end of the 84th capacitor (C84) are all grounded, the inverting input terminal of the operational amplifier (U24) is respectively connected to one end of the 75th resistor (R75) and one end of the 78th resistor (R78), and the other end of the 75th resistor (R75) is grounded, The other end of the 78th resistor (R78) is connected to the output terminal of the operational amplifier (U24), and the output terminal of the operational amplifier (U24) is connected to the input terminal of the current amplifier (U25) through the 79th resistor (R79). The current amplifier The output terminal of (U25) is connected with the transmitting transducer.

Referring to Fig. 6, the workflow of the present invention is as follows: after the power is turned on, the DSP sends a fixed driving frequency data to the FPGA, which is generally 80% of the previous fixed frequency. Taking the liquid ultrasonic transducer as an example, it is 800K Hz. The FPGA sends the data corresponding to the frequency information to the DA converter, and the DA converter sends an analog sine wave signal in real time to drive the power amplification unit, which drives the corresponding transmitting transducer direction, and the receiving end transducer receives the signal from the transmitting end. The piezoelectric effect is generated after the ultrasonic signal of the transducer, and a sine wave signal of a certain intensity is output to be sampled by the AD converter, and the FPGA outputs the AD sampling value to the DSP, and the DSP obtains the sine wave signal of the transducer at the receiving end at the driving frequency peak voltage. Then DSP sends 810K Hz frequency drive signal to FPGA to FPGA, (FPGA outputs different 10-bit parallel data sequences according to DSP commands, controls DA converter to output sinusoidal waveform corresponding to frequency and peak value to drive transmitter to output ultrasonic signal ) Similarly, the peak sine wave voltage of the transducer at the receiving end at a frequency of 810KHz can be obtained, and so on until the driving frequency is 1200k Hz, and the peak voltage value of the receiving end signal strength at each driving frequency point can be obtained. The ultrasonic flowmeter corresponds to the optimum frequency driving point of the transducer, that is, the resonance point of the transducer. After determining the frequency point, write the corresponding DSP-driven FPGA frequency parameters into the external EE memory, and use it as a frequency constant to be directly called by the DSP and output to the FPGA, without having to test the resonance point every time.

Claims (8)

1. the resonance frequency test macro of a ultrasonic flowmeter transducer, it is characterized in that: comprise DSP data processor, FPGA circuit, transmitting transducer, receiving transducer, D/A converter, AD converter, power amplification circuit, storer, described DSP data processor is used for test command to pass to FPGA circuit, described FPGA circuit is for receiving the test command of DSP data processor, export data sequence to D/A converter, the sine wave signal that described D/A converter exports different frequency for the data sequence receiving FPGA circuit drives transmitting transducer, described transmitting transducer is for sending ultrasonic pulsative signal to receiving transducer, described receiving transducer is for receiving the ultrasonic pulsative signal generation piezoelectricity conversion of transmitting transducer, export the sinusoidal signal of certain peak value to AD converter, described AD converter is used for sampling to the sinusoidal signal of receiving transducer, and pass to FPGA circuit, described FPGA circuit is used for the sampled value of the AD converter of reception to export to DSP data processor, the point that in AD sampled value, peak value is maximum judged by described DSP data processor, and the frequency values corresponding to this point is write storer as resonance frequency.

2. the resonance frequency test macro of ultrasonic flowmeter transducer according to claim 1, is characterized in that: described DSP data processor adopts model to be the data processor of TMS320F28335.

3. the resonance frequency test macro of ultrasonic flowmeter transducer according to claim 1, is characterized in that: described FPGA circuit adopts model to be the fpga chip of EP4CE10.

4. the resonance frequency test macro of ultrasonic flowmeter transducer according to claim 1, is characterized in that: described D/A converter adopts model to be the digital to analog converter of AD9760AR.

5. the resonance frequency test macro of ultrasonic flowmeter transducer according to claim 1, is characterized in that: described AD converter adopts model to be the analog to digital converter of ADC12DL040CIVS.

6. the resonance frequency test macro of ultrasonic flowmeter transducer according to claim 1, it is characterized in that: power amplification circuit comprises amplifier (U24), current amplifier (U25) and some resistance, electric capacity, the in-phase input end of described amplifier (U24) is connected with one end of the 76th resistance (R76), the other end of the 76th resistance (R76) respectively with one end of the 77th resistance (R77), one end of 85th electric capacity (C85) connects, the other end ground connection of the 77th resistance (R77), the other end of the 85th electric capacity (C85) respectively with the output terminal of D/A converter, one end of 74th resistance (R74), one end of 84th electric capacity (C84) connects, the other end of the 74th resistance (R74), the equal ground connection of the other end of the 84th electric capacity (C84), the inverting input of described amplifier (U24) respectively with one end of the 75th resistance (R75), one end of 78th resistance (R78) connects, the other end ground connection of the 75th resistance (R75), the other end of the 78th resistance (R78) is connected with the output terminal of amplifier (U24), the output terminal of amplifier (U24) is connected with the input end of current amplifier (U25) through the 79th resistance (R79), the output terminal of current amplifier (U25) is connected with transmitting transducer.

7. the resonance frequency test macro of ultrasonic flowmeter transducer according to claim 1, is characterized in that: described storer is EE storer.

8. the resonance frequency test macro of ultrasonic flowmeter transducer according to claim 7, is characterized in that: the model of described EE storer is FM25L04.