CN104600049B - Lead frame and its chip packing-body - Google Patents
Lead frame and its chip packing-body Download PDFInfo
- Publication number
- CN104600049B CN104600049B CN201410856105.7A CN201410856105A CN104600049B CN 104600049 B CN104600049 B CN 104600049B CN 201410856105 A CN201410856105 A CN 201410856105A CN 104600049 B CN104600049 B CN 104600049B
- Authority
- CN
- China
- Prior art keywords
- chip
- chip carrier
- lead frame
- connecting rod
- bridge frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses lead frame,Including the first lead frame and bridge frame,First lead frame includes the first chip carrier,Multiple first connecting rods,One the first external pin and the first outline border,The outer end of the first connecting rod is connected with first outline border,Its is inner to be connected with first chip carrier,The outer end of first external pin is connected with first outline border,Its inner and the gate turn-on for the chip being placed on first chip carrier,The bridge frame includes the second chip carrier,Multiple second connecting rods and the second outline border,The outer end of the second connecting rod is connected with second outline border,Its is inner to be connected with second chip carrier,The following of second chip carrier is provided with flanging,When the bridge frame is folded into the top of first lead frame,The bottom of the flanging and the lower surface of first chip carrier are in same level,The space of adhering chip is provided between first chip carrier and second chip carrier.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, more particularly to lead frame and its chip packing-body.
Background technology
Semiconductor packages method is that will have the chip that chip cutting forms to be configured on lead frame and make chip electrical
Lead frame is connected to, then, by packing colloid coating chip, prevents that chip from receiving the infringement of extraneous adverse circumstances, and carry
For the medium being electrically connected between chip and external circuit.
Current method for packing is by being bonded in reference to material on the chip carrier of lead frame, then by welding gold by chip
Line, chip and pin are electrically connected, and due to the presence of bonding wire, its package area is big, and encapsulation volume is big, and packaging technology is multiple
It is miscellaneous.
The content of the invention
It is an object of the invention to propose a kind of lead frame and its chip packing-body, package area can be reduced, reduce envelope
Fill volume.Simplify packaging technology.
For this purpose, the present invention uses following technical scheme：
In a first aspect, lead frame, including the first lead frame and bridge frame,
First lead frame includes the first chip carrier, multiple first connecting rods, first external pin and the first outline border,
The outer end of the first connecting rod is connected with first outline border, its is inner to be connected with first chip carrier, outside described first
The outer end of pin is connected with first outline border, its inner and the gate turn-on for the chip being placed on first chip carrier,
The bridge frame includes the second chip carrier, multiple second connecting rods and the second outline border, the outer end of the second connecting rod with
Second outline border connection, its is inner to be connected with second chip carrier, and second chip carrier is provided with flanging below,
When the bridge frame is folded into the top of first lead frame, the bottom of the flanging and first chip carrier
Lower surface be in same level, the sky of adhering chip is provided between first chip carrier and second chip carrier
Between.
Further, first outline border is consistent with the appearance and size of second outline border.
Further, when the bridge frame and first lead frame are superimposed with each other, the institute of the first lead frame both sides
Quantity and the position for stating first connecting rod and the second connecting rod of the bridge frame both sides are corresponding.
Second aspect, chip packing-body, including：
First lead frame, first lead frame include the first chip carrier, the first external pin and multiple first connecting rods, institute
State the inner of first connecting rod to be connected with first chip carrier, the inner of first external pin is with being placed on first core
The gate turn-on of flip-chip on bar；
Bridge frame, the bridge frame are folded on first lead frame, and the bridge frame includes the second chip carrier and more
A second connecting rod, the inner of the second connecting rod are connected with second chip carrier, and the following of second chip carrier is provided with
Flanging, the lower surface of the bottom of the flanging and first chip carrier be in same level, first chip carrier with
The space of adhering chip is provided between second chip carrier；
Flip-chip, the acting surface of the flip-chip are welded on the upper surface of first chip carrier, its non-active face
It is bonded in the lower surface of second chip carrier；
Packing colloid, coats flip-chip and the bridge frame, the bottom surface of the flanging, first external pin it is outer
End and the bottom surface of first chip carrier leak outside in outside the packing colloid.
Further, when the bridge frame and first lead frame are superimposed with each other, the institute of the first lead frame both sides
It is corresponding to state quantity and the position of first connecting rod and the second connecting rod of the bridge frame both sides, the first connecting rod and described
The outer end of second connecting rod leaks outside in outside the packing colloid.
Further, the upper surface of the bridge frame is coated in the packing colloid or the upper surface of the bridge frame
Leak outside in outside the packing colloid.
A kind of lead frame and its chip packing-body provided by the invention, by using two-conductor line frame, the first lead frame and bridge
The flip chip packaging structure of frame overlapping so that chip packing-body is simple in structure, technique is simple and cost is relatively low, passes through at the same time
Product space is directly saved, chip area and packing colloid area ratio are as drain pin using the leakage flanging of bridge frame
More than 82%, PCB space is saved, is integrated beneficial to circuit height.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
Have technology describe needed in attached drawing do one and simply introduce, it should be apparent that, drawings in the following description are this hairs
Some bright embodiments, for those of ordinary skill in the art, without creative efforts, can be with root
Other attached drawings are obtained according to these attached drawings.
Fig. 1 is the main structure diagram for the lead frame that the embodiment of the present invention one provides；
Fig. 2 is the schematic cross-sectional view of A1-A1 in Fig. 1；
Fig. 3 is the main structure diagram for the first lead frame that the embodiment of the present invention one provides；
Fig. 4 is the schematic cross-sectional view of A2-A2 in Fig. 4；
Fig. 5 is the main structure diagram for the bridge frame that the embodiment of the present invention one provides；
Fig. 6 is the schematic cross-sectional view of A3-A3 in Fig. 4；
Fig. 7 is the main structure diagram of chip packing-body provided by Embodiment 2 of the present invention；
Fig. 8 is the side structure schematic view of chip packing-body provided by Embodiment 2 of the present invention；
Fig. 9 is the backsight structural representation of chip packing-body provided by Embodiment 2 of the present invention；
Figure 10 is the vertical profile structure diagram of chip packing-body provided by Embodiment 2 of the present invention；
Figure 11 is the main structure diagram for the chip packing-body that the embodiment of the present invention three provides；
Figure 12 is the side structure schematic view for the chip packing-body that the embodiment of the present invention three provides；
Figure 13 is the backsight structural representation for the chip packing-body that the embodiment of the present invention three provides；
Figure 14 is the vertical profile structure diagram for the chip packing-body that the embodiment of the present invention three provides；
Wherein：
11st, the first chip carrier 12, first connecting rod 13, the first outline border
14th, the first external pin
21st, the second chip carrier 22, second connecting rod 23, the second outline border
24th, flanging
30th, space 40, flip-chip 50, packing colloid
Embodiment
To make the object, technical solutions and advantages of the present invention clearer, hereinafter with reference to attached in the embodiment of the present invention
Figure, technical scheme is clearly and completely described by embodiment, it is clear that described embodiment is the present invention one
Section Example, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making
Go out all other embodiments obtained under the premise of creative work, belong to the scope of protection of the invention.
Embodiment one：
The lead frame provided referring to figs. 1 to Fig. 6, the embodiment of the present invention one, including the first lead frame and bridge frame,
First lead frame includes the first chip carrier 11,12, first external pins 14 of multiple first connecting rods and the
One outline border 13, the outer end of the first connecting rod 12 are connected with first outline border 13, its is inner to connect with first chip carrier 11
Connect, the outer end of first external pin 14 is connected with first outline border 13, it is inner with being placed on first chip carrier
The gate turn-on of chip on 11,
The bridge frame includes the second chip carrier 21,22 and second outline border 23 of multiple second connecting rods, the second connecting rod 22
Outer end be connected with second outline border 23, its is inner to be connected with second chip carrier 21, under second chip carrier 21
While flanging 24 is provided with,
When the bridge frame is folded into the top of first lead frame, the bottom of the flanging 24 and first chip
The lower surface of seat 11 is in same level, and bonding is provided between first chip carrier 11 and second chip carrier 21
The space 30 of chip.
A kind of lead frame provided by the invention, by using two-conductor line frame, the upside-down mounting of the first lead frame and bridge frame overlapping
Chip-packaging structure so that chip packing-body is simple in structure, technique is simple and cost is relatively low,
Wherein, first outline border 13 is consistent with the appearance and size of second outline border 23.
Wherein, when the bridge frame and first lead frame are superimposed with each other, described the of the first lead frame both sides
The quantity and position of one connecting rod 12 and the second connecting rod 22 of the bridge frame both sides are corresponding.
Embodiment two：
With reference to figure 7 to Figure 10, chip packing-body provided by Embodiment 2 of the present invention, including：
First lead frame, first lead frame includes the first chip carrier 11, the first external pin 14 and multiple first connects
Bar 12, the inner of the first connecting rod 12 are connected with first chip carrier 11, and the inner of first external pin 14 is with putting
Put the gate turn-on of the flip-chip on first chip carrier 11；
Bridge frame, the bridge frame are folded on first lead frame, and the bridge frame includes the second chip carrier 21, more
A second connecting rod 22, the inner of the second connecting rod 22 is connected with second chip carrier 21, under second chip carrier 21
While being provided with flanging 24, the bottom of the flanging 24 and the lower surface of first chip carrier 11 are in same level, institute
State the space 30 that adhering chip is provided between the first chip carrier 11 and second chip carrier 21；
Flip-chip 40, the flip-chip 40 are arranged in the space 30, its acting surface is welded on first core
The upper surface of bar 11, its non-active face are bonded in the lower surface of second chip carrier 21；
Packing colloid 50, coats the flip-chip 40 and bridge frame, and the bottom surface of the flanging 24, draw outside described first
The outer end of foot 14 and the leakage of the bottom surface of first chip carrier 11 are in outside the packing colloid 50.
Chip packing-body provided by the invention, the leakage flanging by directly using bridge frame are used as drain pin, are saved
Product space, chip area and packing colloid area ratio are more than 82%, save PCB space, are integrated beneficial to circuit height.
Wherein, when the bridge frame and first lead frame are superimposed with each other, described the of the first lead frame both sides
The quantity and position of one connecting rod 12 and the second connecting rod 22 of the bridge frame both sides are corresponding, the first connecting rod 12 and institute
The outer end for stating second connecting rod 22 leaks outside in outside the packing colloid 50.
Wherein, the upper surface of the bridge frame is coated in the packing colloid 50.
Embodiment three
The chip packing-body provided with reference to figures 11 to Figure 14, the embodiment of the present invention three, is sealed with the chip that embodiment two provides
The main distinction of dress body is：The upper surface of the bridge frame leaks outside in outside the packing colloid 50.Other structures and embodiment
Two structure is identical.
Note that it above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various obvious changes,
Readjust and substitute without departing from protection scope of the present invention.Therefore, although being carried out by above example to the present invention
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
It can include other more equivalent embodiments, and the scope of the present invention is determined by scope of the appended claims.
Claims (6)
1. lead frame, including the first lead frame and bridge frame, it is characterised in that
First lead frame includes the first chip carrier, multiple first connecting rods, first external pin and the first outline border, described
The outer end of first connecting rod is connected with first outline border, its is inner to be connected with first chip carrier, first external pin
Outer end be connected with first outline border, it is inner with the gate turn-on for the chip being placed on first chip carrier,
The bridge frame includes the second chip carrier, multiple second connecting rods and the second outline border, the outer end of the second connecting rod with it is described
Second outline border connects, its is inner to be connected with second chip carrier, and second chip carrier is provided with flanging below,
When the bridge frame is folded into the top of first lead frame, under the bottom of the flanging and first chip carrier
Surface is in same level, and the space of adhering chip is provided between first chip carrier and second chip carrier.
2. lead frame according to claim 1, it is characterised in that the shape ruler of first outline border and second outline border
It is very little consistent.
3. lead frame according to claim 1, it is characterised in that the bridge frame and first lead frame are superimposed with each other
When, the quantity of the second connecting rod of the first connecting rod of the first lead frame both sides and the bridge frame both sides and position
It is corresponding.
4. chip packing-body, it is characterised in that including：
First lead frame, first lead frame include the first chip carrier, the first external pin and multiple first connecting rods, and described
The inner of one connecting rod is connected with first chip carrier, and the inner of first external pin is with being placed on first chip carrier
On flip-chip gate turn-on；
Bridge frame, the bridge frame are folded on first lead frame, and the bridge frame includes the second chip carrier and multiple the
Two connecting rods, the inner of the second connecting rod are connected with second chip carrier, and the following of second chip carrier is provided with flanging,
The lower surface of the bottom of the flanging and first chip carrier is in same level, first chip carrier and described the
The space of adhering chip is provided between two chip carriers；
Flip-chip, the acting surface of the flip-chip are welded on the upper surface of first chip carrier, its non-active face bonding
In the lower surface of second chip carrier；
Packing colloid, coats flip-chip and the bridge frame, the bottom surface of the flanging, first external pin outer end and
The bottom surface of first chip carrier leaks outside in outside the packing colloid.
5. chip packing-body according to claim 4, it is characterised in that the bridge frame and first lead frame are mutual
During overlapping, the quantity of the second connecting rod of the first connecting rod of the first lead frame both sides and the bridge frame both sides and
Position is corresponding, and the outer end of the first connecting rod and the second connecting rod leaks outside in outside the packing colloid.
6. chip packing-body according to claim 4, it is characterised in that the upper surface of the bridge frame is coated on the envelope
Fill in colloid or the upper surface of the bridge frame leaks outside in outside the packing colloid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410856105.7A CN104600049B (en) | 2014-12-31 | 2014-12-31 | Lead frame and its chip packing-body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410856105.7A CN104600049B (en) | 2014-12-31 | 2014-12-31 | Lead frame and its chip packing-body |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104600049A CN104600049A (en) | 2015-05-06 |
| CN104600049B true CN104600049B (en) | 2018-04-17 |
Family
ID=53125725
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410856105.7A Active CN104600049B (en) | 2014-12-31 | 2014-12-31 | Lead frame and its chip packing-body |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104600049B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201174381Y (en) * | 2008-03-28 | 2008-12-31 | 菱生精密工业股份有限公司 | Construction reducing thickness of integrated circuit package |
| US8604610B1 (en) * | 2012-06-13 | 2013-12-10 | Fairchild Semiconductor Corporation | Flexible power module semiconductor packages |
| CN203536411U (en) * | 2013-09-26 | 2014-04-09 | 杰群电子科技（东莞）有限公司 | Semiconductor packaging structure |
| CN203536410U (en) * | 2013-09-11 | 2014-04-09 | 杰群电子科技（东莞）有限公司 | Supporting leg for bent-foot radiating fin used for semiconductor packaging part |
-
2014
- 2014-12-31 CN CN201410856105.7A patent/CN104600049B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201174381Y (en) * | 2008-03-28 | 2008-12-31 | 菱生精密工业股份有限公司 | Construction reducing thickness of integrated circuit package |
| US8604610B1 (en) * | 2012-06-13 | 2013-12-10 | Fairchild Semiconductor Corporation | Flexible power module semiconductor packages |
| CN203536410U (en) * | 2013-09-11 | 2014-04-09 | 杰群电子科技（东莞）有限公司 | Supporting leg for bent-foot radiating fin used for semiconductor packaging part |
| CN203536411U (en) * | 2013-09-26 | 2014-04-09 | 杰群电子科技（东莞）有限公司 | Semiconductor packaging structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104600049A (en) | 2015-05-06 |
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