CN104600026A - Method for etching surface insulation layer of PAD at bottom of TSV hole of CIS product - Google Patents
Method for etching surface insulation layer of PAD at bottom of TSV hole of CIS product Download PDFInfo
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- CN104600026A CN104600026A CN201510048223.XA CN201510048223A CN104600026A CN 104600026 A CN104600026 A CN 104600026A CN 201510048223 A CN201510048223 A CN 201510048223A CN 104600026 A CN104600026 A CN 104600026A
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- tsv hole
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- tsv
- surface insulation
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- 238000000034 method Methods 0.000 title claims abstract description 49
- 238000009413 insulation Methods 0.000 title claims abstract description 37
- 238000005530 etching Methods 0.000 title claims abstract description 26
- 230000004888 barrier function Effects 0.000 claims abstract description 50
- 238000001312 dry etching Methods 0.000 claims abstract description 15
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims description 12
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 7
- 210000000170 cell membrane Anatomy 0.000 claims description 6
- 229910052809 inorganic oxide Inorganic materials 0.000 claims description 6
- 238000003384 imaging method Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 229920002521 macromolecule Polymers 0.000 claims description 4
- 239000012528 membrane Substances 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 239000003973 paint Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 239000010408 film Substances 0.000 description 5
- 101100406797 Arabidopsis thaliana PAD4 gene Proteins 0.000 description 4
- 101150094373 Padi4 gene Proteins 0.000 description 4
- 102100035731 Protein-arginine deiminase type-4 Human genes 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a method for etching a surface insulation layer of a PAD at a bottom of a TSV (Temperature Safety Valve) hole of a CIS (Cartographic Information System) product. The method comprises the following steps: (1) before the TSV hole is etched on the back of the wafer, and a first insulation layer is firstly deposited; (2) photo-etching and dry etching processes are continuously performed to the TSV hole to etch the TSV hole; (3) after the TSV hole is deposited, a second insulation layer is continuously etched; (4) the dry etching process is performed to the whole back surface of the wafer until the insulation layer on the PAD at the bottom of the TSV hole is totally etched. The advantage of the method lies in that the first insulation layer firstly deposited may be regarded as the second insulation layer on the subsequent PAD, removed and used as a barrier layer, when the second insulation layer on the subsequent PAD is etched, the first insulation layer on the back surface of the wafer isn't worried about being destroyed, the photo-etching process with relatively high process difficulty is omitted and the process cost is saved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to the lithographic method of PAD surface insulation layer bottom a kind of CIS product TSV hole.
Background technology
Along with the development of semiconductor technology, the characteristic size of integrated circuit constantly reduces, and device interconnection density improves constantly.Especially CIS product, pixel is increasing, from initial 1,000,000 grades of millions till now, two dimension encapsulation traditional so can not meet the demand of industry, therefore the stacked package mode based on TSV perpendicular interconnection interconnects and superintegrated key technology advantage with its short distance, has led the trend that encapsulation technology develops gradually.
TSV technology comprises following critical process: through hole etches, and makes insulating barrier, filling through hole, chip thinning and stacking etc.Wherein making insulating barrier is can not a unheeded step, and this directly affects the interconnected characteristic of TSV.It is generally utilize the mode of PECVD Direct precipitation insulating material in through hole that traditional insulating barrier makes, and should be used as interconnected PAD metal like this and also be covered by insulating barrier, subsequent etching processes therefore must be utilized to carry out insulating barrier to its surface and remove.
Current industry mainly utilizes the mode of dry etching to carry out insulating barrier removal to PAD surface, and general flow comprises: light blockage coating, exposure imaging and etching etc.Here following problem can be related to:
1) mode of light blockage coating technique general glue spraying is carried out, this kind of mode can cause bottom TSV hole, the photoresistance variable thickness of the edge of sidewall and top-open causes, to such an extent as to because light blocking incessantly causes damage on the limit of the region that should not be etched in subsequent etching processes especially TSV hole upper opening;
2) degree of depth along with TSV hole is more and more darker, aperture is more and more less, therefore the exposure bottom TSV hole above PAD and development can become more and more difficult, and whether be also difficult to detect bottom after development develops completely, and once there be photoresistance to remain on the insulating barrier on PAD surface, so remove will be failed for this insulating barrier, finally causes interconnected inefficacy.
For this problem, current industry is attempted without exposure imaging technique for the simple TSV technique that depth-to-width ratio is little gradually, directly carry out dry etching, load effect is there is due to during insulating layer deposition, therefore bottom TSV hole, the thickness of insulating layer of sidewall, upper shed place and wafer rear is all different, especially the thickness of insulating layer on PAD surface and differing greatly of wafer rear bottom TSV hole, therefore utilize suitable dry etch process that TSV bottom insulation layer can be made to remove, can also at wafer back part surface residual suitable thickness insulating barrier.
There is load effect equally in dry etching, namely wafer back surface etch rate is fast, bottom TSV hole, etch rate is slow, and in order to ensure that TSV hole bottom insulation layer is completely removed, just need to carry out over etching to bottom TSV hole, and over etching can accelerate the clearance of the insulating barrier of wafer back surface equally, the insulating barrier of some region of wafer back surface especially on TSV hole upper opening limit finally may be caused to be etched away, make failure of insulation, increase the thickness that upper surface covers insulating barrier, then bottom insulation layer thickness in TSV hole also can increase, and increases the difficulty of etching technics.
Summary of the invention
For this problem, the invention provides the lithographic method of PAD surface insulation layer bottom a kind of CIS product TSV hole, bottom can utilizing stronger over etching technique guarantee TSV hole, PAD surface insulation layer is successfully etched, the insulating barrier that effectively prevent again wafer back surface is destroyed, present invention process is simple, eliminate the gold-tinted technique that technology difficulty is higher, reduce etching difficulty, save process costs.
A lithographic method for PAD surface insulation layer bottom CIS product TSV hole, it comprises the following steps:
(1), at wafer back surface depositing first insulator layer;
(2), TSV hole is etched by gold-tinted and etch process;
(3), in TSV hole and on first, the second insulating barrier is deposited;
(4) one side of, splitting TSV hole carries out whole etching, by insulating barrier removal above PAD in hole.
It improves further and is: in step (1), step (3), described first insulating barrier is inorganic oxide or the organic insulation substrate plasma membrane with insulating capacity; Described inorganic oxide is oxide, nitride, nitrogen oxide, carbide; Described insulant plasma membrane is coating photoresistance, electrophoretic paint, macromolecule membrane, dry film;
In step (2), gold-tinted technique comprises light blockage coating, exposure imaging technique, and etching adopts dry etching;
In step (4), whole etching is dry etching;
The etch rate of the first insulating barrier is consistent with the etch rate of wafer body;
First insulating barrier adopts different materials from the second insulating barrier.
Bottom CIS product TSV hole of the present invention, the beneficial effect of the lithographic method of PAD surface insulation layer is:
1) in the present invention, the thickness of insulating layer of twice deposition can regulate separately, and can be the film of unlike material, like this in follow-up PAD surface insulation layer is removed, the different etch process of Selection radio just can be utilized to carry out etching to PAD surface insulation layer and do not worry that wafer back surface insulating barrier is destroyed;
2) eliminate the gold-tinted technique that technology difficulty is higher, save process costs;
3) upper shed limit in TSV hole there is dielectric protection layer, protect the upper shed edge in the TSV hole of silicon face below, make it be unlikely to be damaged in dry etching.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below.Apparently, the accompanying drawing in the following describes is only some embodiments recorded in the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the lithographic method flow chart of PAD surface insulation layer bottom CIS product TSV hole;
Fig. 2 is wafer back surface depositing first insulator layer schematic diagram;
Wafer etches TSV schematic diagram to Fig. 3;
Fig. 4 is in TSV hole and the first insulating barrier deposits the second insulating barrier schematic diagram;
Fig. 5 is out that the one side in TSV hole carries out whole etching schematic diagram;
Fig. 6 is that above PAD, insulating barrier removes schematic diagram.
Embodiment
Describe the present invention below with reference to embodiment shown in the drawings.But these execution modes do not limit the present invention, the structure that those of ordinary skill in the art makes according to these execution modes, method or conversion functionally are all included in protection scope of the present invention.
Figure 1 shows that the lithographic method flow chart of PAD surface insulation layer bottom CIS product TSV hole involved in the present invention.
The lithographic method of PAD surface insulation layer bottom a kind of CIS product TSV of the present invention hole, it comprises following concrete steps:
(1), see Fig. 2, first one deck first insulating barrier 2 is deposited to the wafer 1 that will etch TSV hole;
One deck first insulating barrier is first deposited to wanting the TSV wafer face of perforate, this insulating barrier can be the inorganic oxide that the oxide, nitride, nitrogen oxide, carbide etc. deposited by gas phase or liquid phase deposition has insulating capacity, also can be the organic insulation substrate plasma membranes such as coating photoresistance, electrophoretic paint, macromolecule membrane, dry film;
Film thickness is generally at 10nm ~ 10um, the etch rate of the first insulating layer of thin-film material herein in the etching technics in TSV hole is basically identical with the etch rate of silicon, like this in the etching in TSV hole (as shown in Figure 3), etching gas can it goes without doing conversion, the TSV hole inwall carved there will not be obvious interface; But the insulating barrier that this insulating layer material is deposited in TSV hole with second time is preferably different, and two kinds of insulating barriers have larger Selection radio to the PAD surface insulation layer dry etching removed in technique bottom follow-up TSV hole.
(2), see Fig. 3, etch TSV hole 3 by gold-tinted and etch process,
Carry out TSV hole 3 by photoetching and dry etch process to wafer 1 face depositing the first insulating barrier 2 to etch, PAD4 metal is revealed, and gold-tinted comprises the technique such as light blockage coating, exposure imaging, and etching adopts dry etching;
(3), Fig. 4 is seen, the second insulating barrier 5 is deposited in TSV hole 3 and on the first insulating barrier, on wafer 1 surface, TSV hole 3 sidewall and TSV hole 3 bottom deposit first insulating layer 5, this insulating barrier can be the inorganic oxide that oxide, nitride, nitrogen oxide, carbide etc. have insulating capacity, also can be the organic insulation substrate plasma membranes such as coating photoresistance, electrophoretic paint, macromolecule membrane, dry film;
(4), see Fig. 5, Fig. 6, the one side of splitting TSV hole 3 carries out whole etching, is removed by the second insulating barrier 5 above PAD4 in TSV hole 3.
Directly dry etching is carried out to the one side in TSV hole 3, remove the second insulating barrier 5 above PAD4, PAD4 is exposed.In order to ensure that the second insulating barrier can successfully be removed, the mistake etching period of dry etching should be ensured herein.Therefore insulating barrier preferably has higher etching ratio with the insulating barrier that first time deposits herein, such guarantee is in this insulating barrier etching, first insulating barrier of wafer upper surface can be injury-free, do not adopt gold-tinted technique in this step, saved process costs preferably.
This step final result as shown in Figure 6, the insulating barrier on PAD surface is successfully etched away, TSV hole inwall is not by the impact of dry etching, and the second layer insulating barrier of crystal column surface may be left, also may be peelled off completely, what finally play insulating effect when doing back interconnection technology is the first insulating barrier deposited first time.
Those skilled in the art, obviously the invention is not restricted to the details of above-mentioned one exemplary embodiment, and when not deviating from spirit of the present invention or essential characteristic, can realize the present invention in other specific forms.Therefore, no matter from which point, all should embodiment be regarded as exemplary, and be nonrestrictive, scope of the present invention is limited by claims instead of above-mentioned explanation, and all changes be therefore intended in the implication of the equivalency by dropping on claim and scope are included in the present invention.Any Reference numeral in claim should be considered as the claim involved by limiting.
In addition, be to be understood that, although this specification is described according to execution mode, but not each execution mode only comprises an independently technical scheme, this narrating mode of specification is only for clarity sake, those skilled in the art should by specification integrally, and the technical scheme in each embodiment also through appropriately combined, can form other execution modes that it will be appreciated by those skilled in the art that.
In Fig. 4,6 is load wafer.
Claims (8)
1. the lithographic method of PAD surface insulation layer bottom CIS product TSV hole, is characterized in that: it comprises the following steps:
(1), at wafer back surface depositing first insulator layer;
(2), TSV hole is etched by gold-tinted and etch process;
(3), in TSV hole and on first, the second insulating barrier is deposited;
(4) one side of, splitting TSV hole carries out whole etching, by insulating barrier removal above PAD in hole.
2. the lithographic method of PAD surface insulation layer bottom a kind of CIS product TSV hole according to claim 1, it is characterized in that, described first insulating barrier and described second insulating barrier are inorganic oxide or the organic insulation substrate plasma membrane with insulating capacity.
3. the lithographic method of PAD surface insulation layer bottom a kind of CIS product TSV hole according to claim 2, it is characterized in that, described inorganic oxide is oxide, nitride, nitrogen oxide, carbide.
4. the lithographic method of PAD surface insulation layer bottom a kind of CIS product TSV hole according to claim 2, is characterized in that, described insulant plasma membrane is coating photoresistance, electrophoretic paint, macromolecule membrane, dry film.
5. the lithographic method of PAD surface insulation layer bottom a kind of CIS product TSV hole according to claim 1, it is characterized in that, in step (2), gold-tinted technique comprises light blockage coating, exposure imaging technique, and etching adopts dry etching.
6. the lithographic method of PAD surface insulation layer bottom a kind of CIS product TSV hole according to claim 1, is characterized in that, in step (4), whole etching is dry etching.
7. the lithographic method of PAD surface insulation layer bottom a kind of CIS product TSV hole according to claim 1, it is characterized in that, the etch rate of the first insulating barrier is consistent with the etch rate of wafer body.
8., according to the lithographic method of PAD surface insulation layer bottom the arbitrary described a kind of CIS product TSV hole of claim 1-7, it is characterized in that, the first insulating barrier adopts different materials from the second insulating barrier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510048223.XA CN104600026A (en) | 2015-01-30 | 2015-01-30 | Method for etching surface insulation layer of PAD at bottom of TSV hole of CIS product |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510048223.XA CN104600026A (en) | 2015-01-30 | 2015-01-30 | Method for etching surface insulation layer of PAD at bottom of TSV hole of CIS product |
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| CN104600026A true CN104600026A (en) | 2015-05-06 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105405781A (en) * | 2015-12-16 | 2016-03-16 | 华进半导体封装先导技术研发中心有限公司 | Method for manufacturing wafer level encapsulation back lead using CMP process |
| CN105428310A (en) * | 2015-12-16 | 2016-03-23 | 华进半导体封装先导技术研发中心有限公司 | Manufacturing method for TSV hole |
| CN105470147A (en) * | 2015-12-16 | 2016-04-06 | 华进半导体封装先导技术研发中心有限公司 | Method for making adapter plate with CMP process |
| CN105470146A (en) * | 2015-12-16 | 2016-04-06 | 华进半导体封装先导技术研发中心有限公司 | Method for making large-through-hole wafer adapter plate with CMP process |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103441097A (en) * | 2013-08-28 | 2013-12-11 | 华进半导体封装先导技术研发中心有限公司 | Etching method of silicon oxide insulating layer of bottom of deep hole |
| WO2014011615A1 (en) * | 2012-07-09 | 2014-01-16 | Qualcomm Incorporated | Integrating through substrate vias from wafer backside layers of integrated circuits |
| US8691691B2 (en) * | 2011-07-29 | 2014-04-08 | International Business Machines Corporation | TSV pillar as an interconnecting structure |
| KR101422387B1 (en) * | 2013-01-16 | 2014-07-23 | 포항공과대학교 산학협력단 | Fabrication method of next generation cmos image sensors |
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2015
- 2015-01-30 CN CN201510048223.XA patent/CN104600026A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8691691B2 (en) * | 2011-07-29 | 2014-04-08 | International Business Machines Corporation | TSV pillar as an interconnecting structure |
| WO2014011615A1 (en) * | 2012-07-09 | 2014-01-16 | Qualcomm Incorporated | Integrating through substrate vias from wafer backside layers of integrated circuits |
| KR101422387B1 (en) * | 2013-01-16 | 2014-07-23 | 포항공과대학교 산학협력단 | Fabrication method of next generation cmos image sensors |
| CN103441097A (en) * | 2013-08-28 | 2013-12-11 | 华进半导体封装先导技术研发中心有限公司 | Etching method of silicon oxide insulating layer of bottom of deep hole |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105405781A (en) * | 2015-12-16 | 2016-03-16 | 华进半导体封装先导技术研发中心有限公司 | Method for manufacturing wafer level encapsulation back lead using CMP process |
| CN105428310A (en) * | 2015-12-16 | 2016-03-23 | 华进半导体封装先导技术研发中心有限公司 | Manufacturing method for TSV hole |
| CN105470147A (en) * | 2015-12-16 | 2016-04-06 | 华进半导体封装先导技术研发中心有限公司 | Method for making adapter plate with CMP process |
| CN105470146A (en) * | 2015-12-16 | 2016-04-06 | 华进半导体封装先导技术研发中心有限公司 | Method for making large-through-hole wafer adapter plate with CMP process |
| CN105470147B (en) * | 2015-12-16 | 2019-03-05 | 华进半导体封装先导技术研发中心有限公司 | Using the method for CMP process production pinboard |
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Application publication date: 20150506 |