CN104599991A - Wafer detecting method - Google Patents

Wafer detecting method Download PDF

Info

Publication number
CN104599991A
CN104599991A CN201310538455.4A CN201310538455A CN104599991A CN 104599991 A CN104599991 A CN 104599991A CN 201310538455 A CN201310538455 A CN 201310538455A CN 104599991 A CN104599991 A CN 104599991A
Authority
CN
China
Prior art keywords
wafer
test
stress
metal
accelerated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201310538455.4A
Other languages
Chinese (zh)
Inventor
郑岚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuxi CSMC Semiconductor Co Ltd
Original Assignee
Wuxi CSMC Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuxi CSMC Semiconductor Co Ltd filed Critical Wuxi CSMC Semiconductor Co Ltd
Priority to CN201310538455.4A priority Critical patent/CN104599991A/en
Publication of CN104599991A publication Critical patent/CN104599991A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

The invention provides a wafer detecting method. By acquiring an acceleration factor of wafer back metal peeling off in a temperature acceleration environment and acquiring an acceleration factor of the wafer back metal peeling off in a humidity acceleration environment, a comprehensive acceleration factor the wafer back metal peeling off in the acceleration environment of the can be calculated, and storage time of the wafer back metal in a normal environment can be calculated. Therefore, whether a back metallization process meets the requirements can be detected, and the storage time of a wafer which is subject to the back metallization process can be determined, the safety use time of the produced wafer can be early obtained, and the peeling off risk of the back metal can be reduced; and the detecting method is simple, easy, and high in operability.

Description

A kind of wafer detection method
Technical field
The present invention relates to semiconductor fabrication, particularly relate to a kind of wafer detection method.
Background technology
At present, the conducting resistance source of power device is main in source region resistance, channel resistance, JFET resistance, drift layer resistance, resistance substrate.Wherein resistance substrate is the resistance that silicon chip self has, and silicon chip is thinner, and resistance substrate is less.Therefore, carrying out reduction process to silicon chip is the way that industry is general at present; Reduction process is by applying downward pressure to coarse bistrique, carrying out mechanical polishing by the friction of bistrique and silicon chip back side, thus makes part silicon depart from silicon chip entirety, then is cleaned up with pure water.Power device needs to increase layer of metal layer to the contact resistance of the bulk resistance and electrode that reduce device at drain terminal (i.e. silicon chip back side), so that electric current effectively can not produce excessive electric energy loss by power device.Therefore the adhesion of wafer rear metal is the key factor characterizing back metal quality.The adhesion of wafer rear metal determines wafer memory time.
Only had the detection method of back metal adhesion, normally metallized wafer rear sticks blue film overleaf in the past, then carries out scribing to the wafer on blue film, becomes the chip that size is one by one consistent; Chip is separated from blue film, observes on blue film and whether have metal level to remain, if there is metal level to remain, represent that back side metallization technology has to be optimized; If noresidue, represent that back side metallization technology meets the requirements.Wherein, chip is exactly tube core, and encapsulation factory is many chip.
The defect of this method is can only whether fuzzy Judgment back metal adhesion be qualified qualitatively, cannot the actual information of quantitative analysis adhesion, therefore also cannot know how long wafer can store under conventional environment.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of wafer detection method, for overcome above-mentioned wafer detect in cannot quantitative analysis adhesion, the technical problem of wafer conventional environment memory time cannot be known.
For achieving the above object and other relevant objects, the invention provides a kind of wafer detection method, comprising: Metal deposition is carried out to wafer rear; Wafer after back metal deposit is carried out positive mask and scribing; The multiple region of random definition on wafer institute pad pasting after scribing, and accelerated test is carried out to described wafer; Multiple tube cores every the set time from described multiple region extraction wafer, check described tube core and whether occur metal residual on film and record each test duration; Detect the metal residual information of tube core and obtain the test duration occurring metal residual on film in each test first, the wafer life-span namely under each accelerated test respective conditions, and corresponding test data; According to the wafer life-span under each accelerated test respective conditions and corresponding test data, calculate the accelerated factor of described accelerated test; The wafer calculating back metal deposit according to described accelerated factor under conventional environment can memory time.
Preferably, described accelerated test comprises: stress test, humid test, humid test, wherein, described stress test comprises the test under normal stress condition, described humid test comprise be greater than general environmental conditions temperature acceleration temperature, test under normal temperature conditions, described humid test be included in be greater than general environmental conditions humidity acceleration humidity, test under normal humidity condition.
Preferably, the accelerated factor of described accelerated test is that Temperature Accelerating Factor in Life Test is multiplied by humidity accelerated factor.
Preferably, described Temperature Accelerating Factor in Life Test calculates according to Arrhenius model:
T Af = L Use L Stress = exp × [ Ea k × ( 1 T Use - 1 T Stress ) ]
Wherein, L usefor the wafer life-span under normal stress condition, L stressfor accelerating the wafer life-span under temperature conditions, T usefor the absolute temperature under normal temperature conditions, T stressfor accelerating the absolute temperature under temperature conditions, Ea is the activation energy eV reacted that lost efficacy; K is Boltzmann constant, and calculating formula is 8.62 × 10 -5eV/k.
Preferably, described humidity accelerated factor calculates according to Hallberg-Peck model:
H Af = ( RH Stress RH Use ) n
Wherein, RH stressfor accelerating the relative humidity under damp condition, RH usefor the relative humidity under normal humidity condition; N is the acceleration constant of humidity.
Preferably, described Temperature Accelerating Factor in Life Test, humidity accelerated factor are multiplied and obtain the accelerated factor of described accelerated test:
Af=T af× H af, namely Af = exp [ Ea k × ( 1 T Use - 1 T Stress ) ] × ( RH Stress RH Use ) n .
Preferably, also comprise before described wafer carries out back metal deposit: according to predetermined technological requirement, wafer frontside is protected, step that is thinning, roughening is carried out to the described back side.
Preferably, the scribing of described wafer is according to the scribing of actual die size, and described film uses blue film for testing.
Preferably, described wafer is Silicon Wafer, described tube core comprises Metal deposition layer and the silicon layer of extracted same structure and material, and the metal residual information of described detection tube core comprises: detect the step whether occurring metal residual between Metal deposition layer on described tube core and silicon layer.
Preferably, described chip metal deposit forms the complex metal layer that various metals thin layer is formed, described tube core comprises extracted same structure and the complex metal layer of material, and the metal residual information of described detection tube core comprises: whether each metallic film interlayer detected on described tube core occurs the step of metal residual.
A kind of wafer detection method provided by the invention, by knowing the accelerated factor that wafer rear metal peels off in temperature acceleration environment, and know the accelerated factor that wafer rear metal peels off in humidity acceleration environment, thus calculate the comprehensive accelerated factor that wafer rear metal peels off in acceleration environment, thus just can calculate the memory time of wafer rear metal in conventional environment, so, both can detect whether current back side metallization technology meets the requirements, can determine that again the wafer through back side metallization technology can the technical problem of memory time, comparatively early can know produced security wafer service time, thus back metal peeling risk, detection method of the present invention is simple, workable.
Accompanying drawing explanation
Fig. 1 is the steps flow chart schematic diagram of the embodiment of a kind of wafer detection method of the present invention.
Fig. 2 is silicon layer and the metal interlevel structural representation of wafer in embodiments of the invention.
Fig. 3 be wafer in embodiments of the invention multiple layer metal thin layer between structural representation.
Fig. 4 is Ea value Computing Principle schematic diagram in embodiments of the invention.
Fig. 5 is n value Computing Principle schematic diagram in embodiments of the invention.
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 1, the invention provides a kind of wafer detection method, comprising:
Step S1: Metal deposition is carried out to wafer rear;
In the present embodiment, described Metal deposition forms Metal deposition layer, and described metal level can be single metal material, such as, be silver; Also can be the complex metal layer that various metals thin layer is formed; be silver (Ag) thin layer, nickel (Ni) thin layer, titanium (Ti) thin layer in the present embodiment; and described wafer is Silicon Wafer; but also change in other embodiments; not be limited with the present embodiment; conventional; also comprise before described wafer carries out back metal deposit: according to predetermined technological requirement, wafer frontside is protected; step that is thinning, roughening is carried out to the described back side; but visual actual process demand is changed, non-essential.
Step S2: the wafer after back metal deposit is carried out positive mask and scribing;
In the present embodiment, described pad pasting is the blue film of test, and described scribing refers to and utilizes scribing saw (cutter) or line lift-off technology that wafer separate is become one single chip.
Step S3: the multiple region of random definition on the wafer institute pad pasting after scribing, and accelerated test is carried out to described wafer;
In the present embodiment, the multiple region of random definition is conducive to complete detection wafer entirety.
Step S4: the multiple tube cores every the set time from described multiple region extraction wafer;
In the present embodiment, described tube core is the chip that wafer cuts out, wafer is axially cut into pole multi-chip, so identical with wafer axial arrangement, if namely wafer is the structure that metal level adds silicon layer, so described tube core is also identical structure, therefore extracts wafer tube core and is used for detecting, just can understand the Metal deposition quality of whole wafer.
Step S5: check described tube core and whether occur metal residual on film and record each test duration;
In the present embodiment, there is metal residual if there is on film, then illustrate that wafer breaks down, with above-mentioned background technology, indirectly also can think that the wafer life-span expires.
Step S6: the metal residual information detecting tube core, and obtain the test duration occurring metal residual on film in each test first, the wafer life-span namely under each accelerated test respective conditions, and corresponding test data;
Please refer to Fig. 2, in the present embodiment, because described wafer is Silicon Wafer, described tube core comprises Metal deposition layer and the silicon layer of extracted same structure and material, and the metal residual information of described detection tube core comprises: detect the step whether occurring metal residual between Metal deposition layer on described tube core and silicon layer; If (as dotted portion in Fig. 2) metal residual occurs between silicon chip and metal level, then show that the adhesion between silicon layer and metal level needs to optimize.
Please refer to Fig. 3, in the present embodiment, described chip metal deposit forms the complex metal layer that various metals thin layer is formed, described tube core comprises extracted same structure and the complex metal layer of material, and the metal residual information of described detection tube core comprises: whether each metallic film interlayer detected on described tube core occurs the step of metal residual; If described multiple metal film layer as: silver (Ag) thin layer, nickel (Ni) thin layer, between titanium (Ti) thin layer (in as Fig. 2 dotted portion) there is metal residual, then show that the adhesion between described multiple metal film layer needs to optimize.
So, can realize detecting the adhesion situation of wafer after back-metal deposit, thus whether understand processing quality qualified.
Step S7: the accelerated factor calculating described accelerated test according to the wafer life-span under each accelerated test respective conditions and corresponding test data, and the wafer calculating back metal deposit according to described accelerated factor under conventional environment can memory time.
In the present embodiment, described accelerated test completes in climatic chamber, described accelerated test comprises: stress test, humid test, humid test, wherein, described stress test comprises the test under normal stress condition, described humid test comprise be greater than general environmental conditions temperature acceleration temperature, test under normal temperature conditions, described humid test be included in be greater than general environmental conditions humidity acceleration humidity, test under normal humidity condition.
In the present embodiment, the accelerated factor of described accelerated test is that Temperature Accelerating Factor in Life Test is multiplied by humidity accelerated factor.
Described Temperature Accelerating Factor in Life Test can calculate according to Arrhenius model:
T Af = L Use L Stress = exp × [ Ea k × ( 1 T Use - 1 T Stress ) ]
Wherein, L usefor the wafer life-span under normal stress condition, L stressfor accelerating the wafer life-span under temperature conditions, T usefor the absolute temperature under normal temperature conditions, T stressfor accelerating the absolute temperature under temperature conditions, Ea is the activation energy eV reacted that lost efficacy; K is Boltzmann constant, and calculating formula is 8.62 × 10 -5eV/k.
Wherein, concrete computational process is:
Natural logrithm is got on Arrhenius formula both sides obtain: Ln (Life)=(Ea/k) * (1/T); Life corresponding at T temperature meets above-mentioned formula, and, by the form of (X, Y), X=1/T, Y=ln (life), obtain corresponding 3 points, namely as shown in Figure 4 in the temperature of 3 and life-span.
Afterwards, map in the EXCEL that such as can commonly use at graphic hotsopt software, by the curve fitting a straight line of correspondence, the slope obtaining straight line; Namely Ea/k, therefore Ea equals the slope of gained straight line and k(and Boltzmann constant) product.
Preferably, described humidity accelerated factor can calculate according to Hallberg-Peck model:
H Af = ( RH Stress RH Use ) n
Wherein, RH stressfor accelerating the relative humidity under damp condition, RH usefor the relative humidity under normal humidity condition; N is the acceleration constant of humidity, and common n is between 2 ~ 3.
Wherein, concrete computational process is:
Natural logrithm is got on Hallberg-Peck formula both sides obtain: Ln (Life)=n × Ln(RH); Life corresponding under RH humidity meets above-mentioned formula, by the form of (X, Y), X=Ln(RH in the temperature of 3 and life-span), Y=ln (life), obtain corresponding 3 points, namely as shown in Figure 5.
Afterwards, can map in EXCEL, by the curve fitting a straight line of correspondence, the slope obtaining straight line, namely n.
To sum up two calculating, described Temperature Accelerating Factor in Life Test, humidity accelerated factor are multiplied and obtain the accelerated factor of described accelerated test:
Af=T af× H af, namely Af = exp [ Ea k × ( 1 T Use - 1 T Stress ) ] × ( RH Stress RH Use ) n .
According to the accelerated factor of accelerated test, can estimate to obtain the general storage life of wafer under conventional environment, this field technique personnel can obtain in conjunction with the existing calculating of some in industry on the basis of technical scheme provided by the invention, therefore separately do not repeat.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.

Claims (10)

1. a wafer detection method, is characterized in that, comprising:
Metal deposition is carried out to wafer rear;
Wafer after back metal deposit is carried out positive mask and scribing;
The multiple region of random definition on wafer institute pad pasting after scribing, and accelerated test is carried out to described wafer;
Multiple tube cores every the set time from described multiple extracted region wafer;
Check described tube core whether occur metal residual on film and record each test duration;
Detect the metal residual information of tube core and obtain the test duration occurring metal residual on film in each test first, the wafer life-span namely under each accelerated test respective conditions, and corresponding test data;
According to the wafer life-span under each accelerated test respective conditions and corresponding test data, calculate the accelerated factor of described accelerated test;
The wafer calculating back metal deposit according to described accelerated factor under conventional environment can memory time.
2. wafer detection method according to claim 1, it is characterized in that: described accelerated test comprises: stress test, humid test, humid test, wherein, described stress test comprises the test under normal stress condition, described humid test comprise be greater than general environmental conditions temperature acceleration temperature, test under normal temperature conditions, described humid test be included in be greater than general environmental conditions humidity acceleration humidity, test under normal humidity condition.
3. wafer detection method according to claim 2, is characterized in that: the accelerated factor of described accelerated test is that Temperature Accelerating Factor in Life Test is multiplied by humidity accelerated factor.
4. wafer detection method according to claim 3, is characterized in that: described Temperature Accelerating Factor in Life Test calculates according to Arrhenius model:
T Af = L Use L Stress = exp × [ Ea k × ( 1 T Use - 1 T Stress ) ]
Wherein, L usefor the wafer life-span under normal stress condition, L stressfor accelerating the wafer life-span under temperature conditions, T usefor the absolute temperature under normal temperature conditions, T stressfor accelerating the absolute temperature under temperature conditions, Ea is the activation energy eV reacted that lost efficacy; K is Boltzmann constant, and calculating formula is 8.62 × 10 -5eV/k.
5. wafer detection method according to claim 4, is characterized in that: described humidity accelerated factor calculates according to Hallberg-Peck model:
H Af = ( RH Stress RH Use ) n
Wherein, RH stressfor accelerating the relative humidity under damp condition, RH usefor the relative humidity under normal humidity condition; N is the acceleration constant of humidity.
6. wafer detection method according to claim 5, is characterized in that: described Temperature Accelerating Factor in Life Test, humidity accelerated factor are multiplied and obtain the accelerated factor of described accelerated test: Af=T af× H af, namely Af = exp [ Ea k × ( 1 T Use - 1 T Stress ) ] × ( RH Stress RH Use ) n
7. wafer detection method according to claim 1, is characterized in that: also comprise before described wafer carries out back metal deposit: protect wafer frontside according to predetermined technological requirement, carries out step that is thinning, roughening to the described back side.
8. method according to claim 1, is characterized in that, the scribing of described wafer is according to the scribing of actual die size, and described film uses blue film for testing.
9. wafer detection method according to claim 1, it is characterized in that: described wafer is Silicon Wafer, described tube core comprises Metal deposition layer and the silicon layer of extracted same structure and material, and the metal residual information of described detection tube core comprises: detect the step whether occurring metal residual between Metal deposition layer on described tube core and silicon layer.
10. wafer detection method according to claim 1, it is characterized in that: described chip metal deposit forms the complex metal layer that various metals thin layer is formed, described tube core comprises extracted same structure and the complex metal layer of material, and the metal residual information of described detection tube core comprises: whether each metallic film interlayer detected on described tube core occurs the step of metal residual.
CN201310538455.4A 2013-10-31 2013-10-31 Wafer detecting method Pending CN104599991A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310538455.4A CN104599991A (en) 2013-10-31 2013-10-31 Wafer detecting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310538455.4A CN104599991A (en) 2013-10-31 2013-10-31 Wafer detecting method

Publications (1)

Publication Number Publication Date
CN104599991A true CN104599991A (en) 2015-05-06

Family

ID=53125683

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310538455.4A Pending CN104599991A (en) 2013-10-31 2013-10-31 Wafer detecting method

Country Status (1)

Country Link
CN (1) CN104599991A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111856231A (en) * 2020-06-19 2020-10-30 广芯微电子（广州）股份有限公司 Method for analyzing path of moisture entering chip
CN112611703A (en) * 2020-12-01 2021-04-06 上海浦东路桥(集团)有限公司 Method for calculating and testing coupling aging acceleration rate of drainage asphalt pavement

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101211773A (en) * 2006-12-30 2008-07-02 上海先进半导体制造股份有限公司 Method for preventing chip back metal peeling
CN101814450A (en) * 2010-04-29 2010-08-25 上海宏力半导体制造有限公司 Method for detecting adhesive force of metal layer on back of wafer
US8061224B2 (en) * 2008-05-06 2011-11-22 Globalfoundries Singapore Pte. Ltd. Method for performing a shelf lifetime acceleration test
CN102495345A (en) * 2011-12-06 2012-06-13 上海集成电路研发中心有限公司 Method for determining service life of hot carrier injection device
CN103063995A (en) * 2011-10-21 2013-04-24 北京大学 Method for predicating reliability service life of silicon on insulator (SOI) metal-oxide -semiconductor field effect transistor (MOSFET) device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101211773A (en) * 2006-12-30 2008-07-02 上海先进半导体制造股份有限公司 Method for preventing chip back metal peeling
US8061224B2 (en) * 2008-05-06 2011-11-22 Globalfoundries Singapore Pte. Ltd. Method for performing a shelf lifetime acceleration test
CN101814450A (en) * 2010-04-29 2010-08-25 上海宏力半导体制造有限公司 Method for detecting adhesive force of metal layer on back of wafer
CN103063995A (en) * 2011-10-21 2013-04-24 北京大学 Method for predicating reliability service life of silicon on insulator (SOI) metal-oxide -semiconductor field effect transistor (MOSFET) device
CN102495345A (en) * 2011-12-06 2012-06-13 上海集成电路研发中心有限公司 Method for determining service life of hot carrier injection device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
闫立: "可靠性技术的应用与发展", 《环境技术》 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111856231A (en) * 2020-06-19 2020-10-30 广芯微电子（广州）股份有限公司 Method for analyzing path of moisture entering chip
CN112611703A (en) * 2020-12-01 2021-04-06 上海浦东路桥(集团)有限公司 Method for calculating and testing coupling aging acceleration rate of drainage asphalt pavement
CN112611703B (en) * 2020-12-01 2023-12-01 上海浦东路桥(集团)有限公司 Drainage asphalt pavement coupling aging acceleration rate calculation and aging experiment method

Similar Documents

Publication Publication Date Title
Ogbomo et al. Effect of operating temperature on degradation of solder joints in crystalline silicon photovoltaic modules for improved reliability in hot climates
CN103278270B (en) Silicon-glass micro pressure sensor chip of island membrane self-packaging structure and manufacturing method
CN110114888A (en) Semiconductor device
CN100570495C (en) Whether a kind of check etching liquid effective method
WO2007117153A3 (en) Solar cells and methods for manufacturing same
CN104091808B (en) Array base palte and preparation method thereof and display device
CN104241155B (en) The inspection method of semiconductor device
CN104599991A (en) Wafer detecting method
CN106608615B (en) The manufacturing method of MEMS device
JP6811974B2 (en) Information processing equipment, control methods, and programs
CN103545294B (en) Semiconductor detection structure and detection method
CN204085748U (en) Piezoresistive pressure sensor
US9502315B2 (en) Electrical component testing in stacked semiconductor arrangement
CN107785257A (en) IGBT device back process method and IGBT device
CN103928364B (en) A kind of for detecting the structure of alloying level in eutectic bonding
JP6837649B2 (en) Information processing equipment, control methods, and programs
CN106093471B (en) Piezoresistance type acceleration sensor and its manufacturing method in a kind of face containing self-checking function
CN104752233A (en) Welding pad manufacturing method
CN103943527A (en) Method for adopting capacitive test structure to detect polysilicon-gate etching defects
JP2021002987A (en) Information processing apparatus, control method, and program
CN103904000B (en) The method using electric capacity contrast test structure detection polysilicon bottom bridging defect
CN106887468A (en) Thin film transistor (TFT), array base palte and its manufacture method and display panel
CN104835803A (en) Device and method for testing integrated circuit plate and integrated circuit metal layer
CN103646897B (en) The monitoring method of aluminium thin-film technique whisker defect
CN101728229A (en) Method for forming metal pad

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20150506

RJ01 Rejection of invention patent application after publication