CN104598310A - Low-power consumption scheduling method based on FPGA (Field Programmable Gate Array) some dynamic reconfigurable technical module division - Google Patents
Low-power consumption scheduling method based on FPGA (Field Programmable Gate Array) some dynamic reconfigurable technical module division Download PDFInfo
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Abstract
The invention relates to a low-power consumption scheduling method based on FPGA (Field Programmable Gate Array) some dynamic reconfigurable technical module division. The method comprises the steps: (1) constructing a task scheduling diagram based on the FPGA some dynamic reconfigurable technical module division; (2) establishing a power consumption measurement and evaluation model based on the FPGA some dynamic reconfigurable technical module division, measuring chip power consumption and reconfigurable power consumption of each functional module, and evaluating total power consumption under different scheduling policies according to the power consumption measurement and evaluation model; (3) reducing average chip power consumption of the functional module in the condition that the total task scheduling time delay is reduced according to a low-power consumption scheduling algorithm based on the FPGA some dynamic reconfigurable technical module division, so as to simultaneously reduce the total time delay and the total power and reduce the total power consumption. By using the method, the total power consumption on a FPGA chip can be effectively reduced, and the method has important meanings for guiding low-power consumption real-time scheduling of a FPGA some dynamic reconfigurable technical task.
Description
Technical field
The present invention relates to the power consumption assessment of FPGA partial dynamic Reconfiguration Technologies, refer to a kind of low-power consumption scheduling method based on FPGA partial dynamic Reconfiguration Technologies Module Division particularly.
Background technology
In recent years, FPGA is short with its field-programmable characteristic, construction cycle, the advantage such as high integration, low cost, and reconfigurable characteristic makes it be widely used on the design and implimentation of digital display circuit, but, along with FPGA integrated level and speed raising caused by day by day serious power problems, become an important bottleneck of its development of restriction, power problems always is many-sided key factors such as determining product size, weight, performance.So many researchists are mainly placed on reduction FPGA power consumption aspect focus gradually these years, it is also proposed the technology that some clock gating, clock scaling etc. reduce FPGA dynamic power consumption.
But along with the reduction of integrated circuit technology characteristic dimension, chip manufacturing process reaches below 90nm, quiescent dissipation becomes the subject matter of FPGA power consumption, because Dynamic Reconfigurable Technique can reduce resource utilization, configuration feature module more flexibly, so there is people to propose the quiescent dissipation wishing to be reduced FPGA by Reconfiguration Technologies.More existing documents demonstrate Reconfiguration Technologies by experiment can reduce quiescent dissipation, its series of experiments is by rating unit Reconfiguration Technologies and clock gating technology, thus demonstrate when closing idle logical block, partial reconfigurable technology further can save power consumption compared to clockgating technology, and when closing clock, (not having dynamic power consumption) reconstructs low-power consumption module and can further reduce FPGA power consumption to replace original high power consumption module.But, for FPGA flow for dynamic reconfigurable system during operation, how to utilize Dynamic Reconfigurable Technique to reduce the research of the quiescent dissipation aspect of FPGA also seldom, the research of this respect contributes to improving Reconfiguration Technologies and is reducing the practicality in quiescent dissipation.
Consider the power consumption calculation model lacking dynamic reconfigurable, some people proposes a kind of power consumption model and feasible experimental technique carrys out measurements and calculations restructural power consumption.But their power consumption strategies is only the simple module of low-power consumption being replaced with not in the power consumption of use, but they do not consider the different impact of module design task scheduling on power consumption.
Also some are had to research and propose dispatching algorithm, scholar is had to propose the dispatching algorithm of a kind of leakage aware to reduce SRAM power consumption thus to reduce reconstruct power consumption, but he does not consider that different scheduling meetings has an impact to power consumption when running, and power consumption when running causes the principal element of power consumption on total sheet.
Some other technologies are also had to improve restructural performance and reduce restructural power consumption, some researchists are by the power consumption in balance same task serial or parallel computation process, find out a kind of strategy reducing power consumption, but, it is identical that this model is limited to hardware module task, and do not have data dependence relation between task, so vary in size for task, dependence is complicated, and so this model well can not process the power consumption of dynamic reconfigurable.
Summary of the invention
Power consumption on the sheet that the object of the invention is to utilize the enough technology of dynamic reconfigurable to reduce FPGA further.
The technical scheme realizing the object of the invention employing is a kind of low-power consumption scheduling method based on FPGA partial dynamic Reconfiguration Technologies Module Division, and the method comprises:
1) structure is based on the task scheduling graph of a relation of FPGA partial dynamic Reconfiguration Technologies Module Division;
2) measurement of power loss based on FPGA partial dynamic Reconfiguration Technologies Module Division and assessment models is set up, on the sheet measuring each functional module, power consumption and reconstruct power consumption, evaluate the total power consumption under different scheduling strategy according to described measurement of power loss and assessment models;
3) according to the low-power consumption scheduling algorithm based on FPGA partial dynamic Reconfiguration Technologies Module Division, when reducing task scheduling overall delay, power on the average sheet of reduction functional module, thus reduce overall delay and general power simultaneously, realize reducing total power consumption.
In technique scheme, described task scheduling graph of a relation reconstructs node and two-way choice limit describe by the competitive relation between reconstruct time delay and reconstruct construct in task data flow diagram, and the critical path depth of the task scheduling dependency graph of structure represents the overall delay that all task schedulings complete.
In technique scheme, described reconstruct node comprises:
Node V
iand V
jrepresent the task in same restructural region, and V
iat V
jperform, node RV before
jv is added in as reconstruct node
iand V
jbetween, RV
jv
jthe time delay consumed is done in reconstruct, upgrades connection task node V
iand V
jlimit be connection task node and reconstruct node between limit (V
i, RV
j), (RV
j, V
j).
In technique scheme, described two-way choice limit is RE=<RV
i| RV
j>, this two-way choice limit is made up of the limit of a pair reverse direction, RV
i->RV
jor RV
j->RV
i, different sensings represents the dispatching sequence that counterweight structure node is different, and this pair contrary limit is XOR relation.
In technique scheme, estimate FPGA general power according to described measurement of power loss and assessment models and comprise:
Divided restructural region at one piece, distribute on the fpga chip of module, set up power consumption model, total power consumption is:
E
total＝E
cfgs+E
tasks
In formula, E
totalgross energy when referring to operation, chip consumed, E
cfgsowing to reconstructing the gross energy of hardware resource consumption, E when referring to operation
tasksrefer to the gross energy consumed when performing hardware task;
Due to E
cfgswith total reconstruct time delay T
cfglinear, so obtain E by following formula
cfgs:
E
cfgs＝P
cfg*T
cfgs＝P
cfg*∑t
cfgi
E
tasks＝∑P
i*t
i
In formula, P
cfgreconstruct power, t
cfgirepresent the time of each reconstruct respectively, P
ifor the power that each hardware task is shared on chip, t
irepresent the time that i-th task is shared on chip; So:
E
total＝P
cfg*∑t
cfgi+∑P
i*t
i＝P
avg*t
total
P
avg, t
totalaverage power when being chip operation respectively and T.T..
In technique scheme, reduce average power on FPGA sheet while reducing task scheduling overall delay and comprise:
Create the list of two-way limit, for depositing all two-way limits, then each only taking-up two-way limit, two kinds of selections on each more two-way limit, select better situation in current task scheduling graph, the situation that namely overall delay is minimum, retain the limit in this direction, cut the limit of other direction; Circulation like this is gone down, till to the last not having two-way limit in list; At every turn choosing two-way limit, before beta pruning, need start time st and the reconstruct time delay et of the relevant reconstruct node recalculated in current task scheduling graph, thus reduce the overall delay of task scheduling;
On the basis of the shortest critical path algorithm, keep critical path depth, by comparing the power on non-critical path between node and front and back node, on the sheet of task of making power larger, the time reduces, thus reduces average power on sheet.
The inventive method effectively can reduce the total power consumption on fpga chip, has great significance to instructing FPGA partial dynamic Reconfiguration Technologies task low-power consumption Real-Time Scheduling.
Accompanying drawing explanation
Fig. 1 is the process flow diagram of the low-power consumption scheduling method that the present invention is based on FPGA partial dynamic Reconfiguration Technologies Module Division.
Fig. 2 is the present invention task scheduling figure used.
Fig. 3 is the present embodiment task scheduling figure used, and the node of same shape represents it is node in same restructural region, and black node represents reconstruct time delay.
Fig. 4 is the task scheduling figure after beta pruning.
Fig. 5 is task scheduling figure (a) and task power consumption diagram (b) under flow for dynamic reconfigurable system.
Fig. 6 (a) is the shortest critical path scheduling result, and Fig. 6 (b) is low-power consumption scheduling result.
Fig. 7 is two kinds of dispatching algorithm task power consumption diagram, and (a) is the shortest critical path scheduling power consumption diagram, and (b) is low-power consumption scheduling power consumption diagram.
Embodiment
Below in conjunction with accompanying drawing and specific experiment example the present invention is described in further detail.
The present embodiment verifies feasibility and the validity of the low-power consumption scheduling method that the present invention is based on FPGA partial dynamic Reconfiguration Technologies Module Division by the FPGA platform of reality, by contrast and experiment, can show that low-power consumption scheduling algorithm has obvious optimization to power consumption and time delay.
The present embodiment experiment porch used is xc5vlx110t development board, developing instrument is xilinx Tools12.4 (ISE+PlanAhead+EDK), and experiment realizes dynamic reconfigurable on xc5vlx110t development board, mainly contains two key points, first: dynamically, second: restructural; For dynamically, plan to adopt the soft core of microblaze to control each parts as processor, thus reach dynamic object; For restructural, xilinx proposes oneself a set of solution-planahead instrument, this instrument can realize in restructural region, add the reconfigurable module for reconstruct very easily, and can generate the partial reconfigurable configuration file of each module, allows experiment difficulty reduce.Experiment porch details is as follows:
1, hardware is built, and this step uses the XPS in EDK, needs to observe various operation in experiment, because being employed herein serial communication UART; Need to add loading reconstruction bit, employ ICAP; File needed for planning of experiments is stored by CF, controls because being employed herein systemACE; Line module user logic is as restructural region in addition, and this part will make the user logic ip core of oneself by template IP core.Meanwhile, bus is the plb v46 adopted.In this step, user logic is a black box, is used as restructural region, therefore can't generates bit in this step.Next step, will divide restructural by planahead instrument, thus generate bit, completely realize building of hardware.
2, restructural divides, and this step uses planahead instrument.The main task of this step adds for the module bit at this regional restructuring in each restructural region, and each module bit generates in ISE, and ensures that the title of each module is the same with pin name.Finally each has configured run and generate bit operation and has generated the whole bit file of each configuration and the bit file of reconfigurable module, and the time of this step is a little long.After completing hardware components, namely next step be by the loading of each bit of program deployment and the work of other peripheral hardwares in the SDK in EDK.
3, realize dynamically, this step uses the SDK in EDK.The corresponding information of the hardware that loading generates above, the API (except user logic ip) of each module can be found in SDK, can easily be completed dynamically and the work of other peripheral hardwares by the API provided, the algorithm realization that also can add oneself in SDK is allocated accordingly.
4, the associated documents that a few step generates above convert the corresponding file layout of CF card to, and need to use Xilinx Bash shell instrument, corresponding script command can inquire about cygwin tool command.This step generates the bit of system.ace and other modules.
5, change xc5vlx110t development board start-up mode, be adjusted to from CF card start-up.
6, be placed in CF card by the file generated in 4, start power, development board can according to the idea work of oneself.Arrive this, whole flow process completes.
In addition, by vivado HLS, not only can obtain the VHDL of C language conversion, can also be helped by the Schedule Graph comprehensively gone out to analyze the data dependence relation between modules and time delay.The measurement of power consumption can use multiple voltage table to coordinate amplification circuit measuring.What Fig. 7 showed is the experiment flow realized to last sheet from High Level Synthesis.
As shown in Figure 1, the low-power consumption scheduling method that the present invention is based on FPGA partial dynamic Reconfiguration Technologies Module Division comprises:
S100, construct task scheduling graph of a relation based on FPGA partial dynamic Reconfiguration Technologies Module Division.
S200, set up measurement of power loss based on FPGA partial dynamic Reconfiguration Technologies Module Division and assessment models, on the sheet measuring each functional module, power consumption and reconstruct power consumption, evaluate the total power consumption under different scheduling strategy according to described measurement of power loss and assessment models.
S300, basis are based on the low-power consumption scheduling algorithm of FPGA partial dynamic Reconfiguration Technologies Module Division, when reducing task scheduling overall delay, power on the average sheet of reduction functional module, thus reduce overall delay and general power simultaneously, realize the object reducing total power consumption.
Hardware task scheduling problem is abstracted into the task scheduling figure based on module by the present invention, be described with the example of six modules, as shown in Figure 2, in Fig. 2 (a), node is hardware task node, correspond to scheduling sequential chart, task execution time section in Fig. 2 (b), when not considering reconstruct time delay, the time that on sheet, application program performs depends on the total duration in task scheduling graph key path.
Task scheduling figure G=(V, E, HW, R) represents execution sequence and the time period of each task, performs sequence and retrains by the Collision of reconstruct between data dependence relation and different restructural region.V=(est, lst, et, p) is node set, and each node represents hardware task execution time section or reconstitution time section, and wherein est represents earliest start time, and lst represents late start time, and et represents the execution time, and p represents the power of dissipation.E={ (Vi, Vj) | Vi and Vj is two nodes } be the set on limit in figure, wherein every bar limit represents data dependence relation or Collision of reconstruct.HW represents the set of hardware task node, and R represents the set of reconstruct node, HW and R belongs to V.
In the present embodiment, suppose node V
iand V
jrepresent the task in same restructural region, and V
iat V
jperform, node RV before
jv should be added in as reconstruct node
iand V
j. between, RV
jv
jthe time delay consumed is done in reconstruct, upgrades connection task node V
iand V
jlimit be connection task node and reconstruct node between limit (V
i, RV
j), (RV
j, V
j).Suppose that modules A and module B are at restructural region PRR
1in, module C and module D is at restructural region PRR
2in, in order to represent the reconstruct time delay in each restructural region, introduce RB
1and RD
1to in task dependence graph, original directed edge A
1->B
1become A
1->RB
1->B
1, original C->D
1become C->RD
1->D
1.
But, because synchronization only has a restructural region to be reconstructed, namely reconstruct between node and there is competitive relation, so need to introduce special relation limit to represent this Reconstruction Constraints.
Two-way choice limit RE=<RV
i| RV
j>, this two-way choice limit is made up of the limit of a pair reverse direction, RV
i->RV
jor RV
j->RV
idifferent sensings represents the dispatching sequence that counterweight structure node is different, and this pair contrary limit is XOR relation, namely can only select a limit pointed in two-way change in task scheduling graph, because only a kind of dispatching sequence may be there is between any two reconstruct nodes.
After setting up task scheduling figure, power on the sheet measuring each functional module, and FPGA general power can be estimated according to model, concrete steps are as follows:
Divide restructural region at one piece, distributed on the fpga chip of module, set up power consumption model.Because total power consumption is made up of, so there is following equation the power consumption of executing the task and reconstruct power consumption two parts:
E
total＝E
cfgs+E
tasks
E
totalgross energy when referring to operation, chip consumed, E
cfgsowing to reconstructing the gross energy of hardware resource consumption, E when referring to operation
tasksrefer to the gross energy consumed when performing hardware task.Due to E
cfgswith total reconstruct time delay T
cfglinear, so E can be obtained by following equalities
cfgs.
E
cfgs＝P
cfg*T
cfgs＝P
cfg*∑t
cfgi
Owing to lacking for the power estim ation model to each hardware task in flow for dynamic reconfigurable system, so go out P by circuit measuring as shown below
cfg, P
cfgreconstruct power, t
cfgirepresent the time of each reconstruct respectively.
By measuring reconstruct power P
cfgand the power P that each hardware task is shared on chip
i.Assuming that when chip does not have loading tasks, and power when not reconstructing is zero, so E
taskscan be obtained by following equation.
E
tasks＝∑P
i*t
i
Wherein t
irepresent the time that i-th task is shared on chip.The total energy consumption model of comprehensive above-mentioned equation can be expressed as:
E
total＝P
cfg*∑t
cfgi+∑P
i*t
i＝P
avg*t
total
Wherein distinguish P
avg, t
totalaverage power when being chip operation and T.T..Target be exactly by reduce P
avgand t
total, thus reduce total power consumption.
Therefore, side of the present invention makes also to reduce power on average sheet while the time on the sheet that minimizing is total, so just can reduce total power consumption.
First, create the list of two-way limit, for depositing all two-way limits, then each only taking-up a two-way limit, at every turn two kinds of selections on more two-way limit, select better situation in current task scheduling graph, namely the situation that overall delay is minimum, retains the limit in this direction, cuts the limit of other direction.Circulation like this is gone down, till to the last not having two-way limit in list.At every turn choosing two-way limit, before beta pruning, need start time st and the reconstruct time delay et of the relevant reconstruct node recalculated in current task scheduling graph.So just can reduce the overall delay of task scheduling.
In order to reduce average power on sheet, basic ideas reduce the time of task on sheet as far as possible, allows the time on the larger task piece of power shorten as far as possible.Because critical path depth represents total length, in order to not extend T.T. and power consumption, the node in critical path is not adjusted, the node on non-critical path is adjusted, can not T.T. be extended.Therefore, the main thought of low-power consumption scheduling algorithm is exactly, and on the basis of the shortest critical path algorithm, keeps critical path depth, and by comparing the power on non-critical path between node and front and back node, on the sheet of task of making power larger, the time reduces.
The present embodiment adopts the shortest critical path algorithm, and reduce the time on total sheet, as shown in Figure 3, modules A, module B and module C share restructural region PRR1, and module C, module D and module E share restructural region PRR2.In order to represent reconstruct time delay, introduce RA3, RB, RC1, RD, RE2 and RF1 herein in task scheduling graph, at this moment directed edge A2->B becomes A2->RB->B, build two-way limit <RB|RE2> between reconstruct node RB and RE2, two-way limit provides different choice RB->RE2 or RE2->RB.
Weight sum in critical path represents the time on sheet total in reconfigurable system, and the shortest critical path algorithm can find out the as far as possible short schedule sequences of a kind of critical path, thus reduces the time on total sheet.After the beta pruning of two-way limit, the schedule sequences obtained as shown in Figure 4.
Then, when reducing time delay on sheet, reduce average power on sheet simultaneously.In experimentation, by measuring the power consumption of modules, can find that the energy ezpenditure of each hardware task terminated before reconstruct next task from this task of reconstruct, comprising power consumption when running and reconstruct power, reconstruct power is almost a constant, and the energy ezpenditure of reconstruction stage is by power consumption sum when reconstruct power consumption and operation.
Fig. 5 shows the scheduling result of the shortest critical path algorithm, and corresponding task power consumption diagram, and dash area represents power when task run or reconstruct, and color is darker, illustrates that power is larger, can find out the time period of each task energy ezpenditure from this figure.
In order to reduce average power on sheet, the present embodiment reduces the time of task on sheet as far as possible, allows the time on the larger task piece of power shorten as far as possible.Because critical path depth represents total length, in order to not extend T.T. and power consumption, the node in critical path is not adjusted, the node on non-critical path is adjusted, can not T.T. be extended.Therefore, the main thought of low-power consumption scheduling algorithm is exactly, and on the basis of the shortest critical path algorithm, keeps critical path depth, and by comparing the power on non-critical path between node and front and back node, on the sheet of task of making power larger, the time reduces.
Specific algorithm is: because it is considered that task run time power consumption, so power consumption when hypothesis FPGA does not reconstruct any task is zero, with this as the starting point, the power consumption model saved by upper calculates.1) compare the task node on non-critical path and the watt level between its previous task node and a rear task node, find out the task node of minimum power; 2) repeat step 1, until the node of non-critical path the preceding paragraph continuous adjacent all compares end, find out the task node of minimum power on this section of non-critical path; 3) on this section of non-critical path, the reconstruct as far as possible early of the node before minimum power task node (comprising this node) runs, the reconstruct operation that the node after this node is slow as far as possible.4) may vacate a period of time after minimum power task node does not have tasks carrying (also to have task in now due to restructural region, so this task still has power consumption), if be greater than the time needed for reconstruct idle task (sky is put in restructural region) during this period of time, the task power consumption then more do not run and the power consumption of reconstruct needed for idle task, if the power consumption needed for reconstruct idle task is less, so again power consumption can be reduced by reconstruct idle task.5) in addition, non-critical path has two kinds of task node situations relatively more special, one is the task of starting to be configured to restructural region most, due on non-critical path, when not extending critical path, slow is as far as possible reconfigured in restructural region.Another kind is exactly the task of being finally reconfigured to restructural region, even if do not need but owing to being also trapped on sheet, still can consume power consumption, so can process according to the method for similar step 4.
As shown in Figure 6, A
1, C
2, RE
2, E
2, RF
1and F
1all the node on non-critical path, A
1a node, and on non-critical path, so scheduling A slow as far as possible
1, namely according to A
1late start time dispatches .{D, RE
2, E
2, RF
1, F
1, F
2some row continuous print nodes on non-critical path, wherein find E
2the task node of minimum power, so by RF
1, F
1in late start time scheduling, due at E
2and RF
1between there is one period of time period not having a task run, but be less than reconstruct time delay, in order to not extend overall delay, so do not reconstruct idle task due to this time period.C
2the task of last reconstruct, and on most non-critical path, so unexpectedly may scheduling C early
2.So just vacating one period of sufficiently long time period reconstructs idle task, and according to initial setting, the power of idle task is zero, and reconstruction task C
2required power dissipation ratio task C
2on sheet in this section of free time section, power consumption is little, therefore can reduce power consumption by sky is put in restructural region.
Fig. 7 represents it is low-power consumption scheduling result, easily can find that low-power consumption scheduling algorithm is by reducing with the minimizing unnecessary power consumption of high power consumption tasks on sheet, reach the object reducing power consumption, this algorithm not only effectively reduces on sheet the time by scheduling, and effectively reduces power consumption on sheet.
Claims (6)
1., based on a low-power consumption scheduling method for FPGA partial dynamic Reconfiguration Technologies Module Division, it is characterized in that, comprising:
1) structure is based on the task scheduling graph of a relation of FPGA partial dynamic Reconfiguration Technologies Module Division;
2) measurement of power loss based on FPGA partial dynamic Reconfiguration Technologies Module Division and assessment models is set up, on the sheet measuring each functional module, power consumption and reconstruct power consumption, evaluate the total power consumption under different scheduling strategy according to described measurement of power loss and assessment models;
3) according to the low-power consumption scheduling algorithm based on FPGA partial dynamic Reconfiguration Technologies Module Division, when reducing task scheduling overall delay, power on the average sheet of reduction functional module, thus reduce overall delay and general power simultaneously, realize reducing total power consumption.
2. according to claim 1 based on the low-power consumption scheduling method of FPGA partial dynamic Reconfiguration Technologies Module Division, it is characterized in that: described task scheduling graph of a relation reconstructs node and two-way choice limit describe by the competitive relation between reconstruct time delay and reconstruct construct in task data flow diagram, and the critical path depth of the task scheduling dependency graph of structure represents the overall delay that all task schedulings complete.
3., according to claim 2 based on the low-power consumption scheduling method of FPGA partial dynamic Reconfiguration Technologies Module Division, it is characterized in that described reconstruct node comprises:
Node V
iand V
jrepresent the task in same restructural region, and V
iat V
jperform, node RV before
jv is added in as reconstruct node
iand V
jbetween, RV
jv
jthe time delay consumed is done in reconstruct, upgrades connection task node V
iand V
jlimit be connection task node and reconstruct node between limit (V
i, RV
j), (RV
j, V
j).
4., according to claim 3 based on the low-power consumption scheduling method of FPGA partial dynamic Reconfiguration Technologies Module Division, it is characterized in that described two-way choice limit is RE=<RV
i| RV
j>, this two-way choice limit is made up of the limit of a pair reverse direction, RV
i->RV
jor RV
j->RV
i, different sensings represents the dispatching sequence that counterweight structure node is different, and this pair contrary limit is XOR relation.
5., according to claim 4 based on the low-power consumption scheduling method of FPGA partial dynamic Reconfiguration Technologies Module Division, it is characterized in that estimating FPGA general power according to described measurement of power loss and assessment models comprises:
Divided restructural region at one piece, distribute on the fpga chip of module, set up power consumption model, total power consumption is:
E
total＝E
cfgs+E
tasks
In formula, E
totalgross energy when referring to operation, chip consumed, E
cfgsowing to reconstructing the gross energy of hardware resource consumption, E when referring to operation
tasksrefer to the gross energy consumed when performing hardware task;
Due to E
cfgswith total reconstruct time delay T
cfglinear, so obtain E by following formula
cfgs:
E
cfgs＝P
cfg*T
cfgs＝P
cfg*∑t
cfgi
E
tasks＝∑P
i*t
i
In formula, P
cfgreconstruct power, t
cfgirepresent the time of each reconstruct respectively, P
ifor the power that each hardware task is shared on chip, t
irepresent the time that i-th task is shared on chip; So:
E
total＝P
cfg*∑t
cfgi+∑P
i*t
i＝P
avg*t
total
P
avg, t
totalaverage power when being chip operation respectively and T.T..
6., according to claim 5 based on the low-power consumption scheduling algorithm of FPGA partial dynamic Reconfiguration Technologies Module Division, reduce average power on FPGA sheet while it is characterized in that reducing task scheduling overall delay and comprise:
Create the list of two-way limit, for depositing all two-way limits, then each only taking-up two-way limit, two kinds of selections on each more two-way limit, select better situation in current task scheduling graph, the situation that namely overall delay is minimum, retain the limit in this direction, cut the limit of other direction; Circulation like this is gone down, till to the last not having two-way limit in list; At every turn choosing two-way limit, before beta pruning, need start time st and the reconstruct time delay et of the relevant reconstruct node recalculated in current task scheduling graph, thus reduce the overall delay of task scheduling;
On the basis of the shortest critical path algorithm, keep critical path depth, by comparing the power on non-critical path between node and front and back node, on the sheet of task of making power larger, the time reduces, thus reduces average power on sheet.
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106648883A (en) * | 2016-09-14 | 2017-05-10 | 上海鲲云信息科技有限公司 | FPGA-based dynamic reconfigurable hardware acceleration method and system |
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| CN113886196A (en) * | 2021-12-07 | 2022-01-04 | 上海燧原科技有限公司 | On-chip power consumption management method, electronic device and storage medium |
| CN114527862A (en) * | 2022-02-14 | 2022-05-24 | 贵州电网有限责任公司 | Method, equipment and medium for adjusting power consumption of chip special for electric power |
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