CN104596553B - Phase-shift pulse generation device for time division multiplexing FBG sensor network - Google Patents

Phase-shift pulse generation device for time division multiplexing FBG sensor network Download PDF

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CN104596553B
CN104596553B CN201410834580.4A CN201410834580A CN104596553B CN 104596553 B CN104596553 B CN 104596553B CN 201410834580 A CN201410834580 A CN 201410834580A CN 104596553 B CN104596553 B CN 104596553B
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姜德生
胡宸源
文泓桥
白巍
罗志会
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Wuhan University of Technology WUT
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Abstract

本发明公开了一种时分复用FBG传感网络的相移脉冲产生装置,其结构是:高精度相位移动电脉冲信号控制光信号选择传感网络上的FBG,完成大规模光纤光栅时分复用,其结构包括以电信号相连的配置信息解析单元、脉宽信息单元、脉宽周期信息单元、第一级时延控制单元、第二级时延控制单元、脉冲控制单元、光栅位置信息存储控制单元、OSERDES并串转换单元。本发明的相移脉冲产生装置及其方法不但解决了商用信号发生器不能自动扫描光纤光栅阵列的问题,而且大大提高了脉冲相移精度,成本低,集成度高,系统结构简单,可靠性好,可方便进行空分多路光栅阵列扩展。

The invention discloses a phase-shift pulse generating device for a time-division multiplexing FBG sensor network. The structure is: a high-precision phase-shift electric pulse signal controls an optical signal to select an FBG on the sensor network, and completes large-scale fiber grating time-division multiplexing. Its structure includes a configuration information analysis unit, a pulse width information unit, a pulse width period information unit, a first-level time delay control unit, a second-level time delay control unit, a pulse control unit, and a grating position information storage control unit connected by electrical signals. Unit, OSERDES and serial conversion unit. The phase-shift pulse generation device and method thereof of the present invention not only solve the problem that the commercial signal generator cannot automatically scan the fiber grating array, but also greatly improve the pulse phase-shift accuracy, low cost, high integration, simple system structure, and good reliability , which can facilitate the expansion of the space division multiplex grating array.

Description

时分复用FBG传感网络的相移脉冲产生装置Phase shift pulse generation device for time division multiplexing FBG sensor network

技术领域technical field

本发明涉及光纤光栅传感网络领域,尤其涉及一种时分复用FBG传感网络的相移脉冲产生方法,可实现时分复用FBG检测或者调制解调系统的光开关电信号的控制。The invention relates to the field of fiber grating sensor networks, in particular to a phase-shift pulse generation method for a time-division multiplexing FBG sensor network, which can realize time-division multiplexing FBG detection or control of optical switch electrical signals of a modulation and demodulation system.

背景技术Background technique

弱光纤光栅传感网络的优势在于串扰小、复用能力强和性价比高等优势,有望在油田、隧道、楼宇健康监测等恶劣环境中实现准分布式检测。目前,“光栅在线刻写”技术能在光纤拉制过程中间隔一定距离自动刻写光栅阵列。这个技术不但避免了传统光栅熔接成阵列时的接点损耗,而且光栅的空间分布密集度、传感器阵列的容量都有了质的提升。所以对于时分复用FBG的检测或者传感网络系统就提出来更高的要求。时分复用技术利用传感器的反射信号在时域上的间隔特性,能有效地抑制光栅的串扰和灵活监控每个传感器的状态,是时分复用FBG传感系统中行之有效的一种应用方法。在时分复用系统中,每个传感光栅都有不同的延时,控制光脉冲进出光栅阵列的高速光开关的信号发生器直接影响到监控系统的测量精度和性能。因此,研究时分复用FBG传感网络的相移脉冲产生方法很有必要。The advantages of weak fiber grating sensor networks are small crosstalk, strong multiplexing capability and high cost performance. It is expected to realize quasi-distributed detection in harsh environments such as oil fields, tunnels, and building health monitoring. At present, the "on-line grating writing" technology can automatically write the grating array at a certain distance during the fiber drawing process. This technology not only avoids the contact loss when the traditional grating is welded into an array, but also improves the spatial distribution density of the grating and the capacity of the sensor array. Therefore, higher requirements are put forward for the detection of time-division multiplexing FBG or the sensor network system. The time-division multiplexing technology utilizes the interval characteristics of the reflected signal of the sensor in the time domain, which can effectively suppress the crosstalk of the grating and flexibly monitor the status of each sensor. It is an effective application method in the time-division multiplexing FBG sensor system. In a time-division multiplexing system, each sensing grating has a different delay, and the signal generator of the high-speed optical switch that controls the light pulses entering and exiting the grating array directly affects the measurement accuracy and performance of the monitoring system. Therefore, it is necessary to study the phase-shift pulse generation method of time-division multiplexed FBG sensor network.

文献“An interrogation system for a sensor array with 1310nm bandultra-weak fiber Bragg gratings”(Optical Engineer,J.)提出了一种利用两个SOA高速光电开关实现时分复用FBG传感网络的调制和解调系统。在调制模块中,一个SOA高速光电开关与小宽带光源连接,对光源信号进行调制和放大;另一个SOA高速光电开关在取样模块中对从环行器输出的经光栅反射回来的光脉冲进行选择和分离,完成解调功能。相位延时不同的两路周期性电脉冲信号来控制这两个SOA高速光电开关。这个延时就对应于光栅和环行器距离的两倍光程。由于该系统采用的是商用的信号发生器,系统只能手动控制产生光脉冲控制信号,不具备在线控制扫描光栅阵列、自动循环扫描等功能,严重阻碍了系统的产品化进程。另外,商用信号发生器只能产生纳秒级的脉冲延时,在精度上也满足不了系统日益增长的性能需求。The document "An interrogation system for a sensor array with 1310nm bandultra-weak fiber Bragg gratings" (Optical Engineer, J.) proposed a modulation and demodulation system using two SOA high-speed photoelectric switches to realize time-division multiplexing FBG sensor network . In the modulation module, a SOA high-speed photoelectric switch is connected with a small broadband light source to modulate and amplify the light source signal; another SOA high-speed photoelectric switch selects and amplifies the light pulse reflected from the grating output from the circulator in the sampling module. Separated to complete the demodulation function. Two periodic electrical pulse signals with different phase delays are used to control the two SOA high-speed photoelectric switches. This delay corresponds to twice the distance between the grating and the circulator. Since the system uses a commercial signal generator, the system can only be manually controlled to generate light pulse control signals, and does not have the functions of on-line control scanning grating array, automatic cycle scanning, etc., which seriously hinders the productization process of the system. In addition, commercial signal generators can only generate nanosecond-level pulse delays, which cannot meet the increasing performance requirements of the system in terms of accuracy.

发明内容Contents of the invention

本发明要解决的技术问题在于:针对现有时分复用时分复用FBG传感网络系统中无法在线自动产生目标光脉冲控制信号的问题,提供一种时分复用FBG传感网络的相移脉冲产生装置,该装置可实现时分复用FBG传感器全自动定位、存储,并且脉冲的脉宽、周期等参数完全可在线重配的皮秒级相位延时脉冲。The technical problem to be solved by the present invention is: aiming at the problem that the target optical pulse control signal cannot be automatically generated online in the existing time-division multiplexing FBG sensor network system, a phase-shift pulse of the time-division multiplexing FBG sensor network is provided. A generation device, which can realize fully automatic positioning and storage of time-division multiplexed FBG sensors, and a picosecond-level phase-delayed pulse whose parameters such as pulse width and cycle can be completely reconfigured online.

本发明解决其技术问题所采用的技术方案是:The technical solution adopted by the present invention to solve its technical problems is:

本发明提供的时分复用FBG传感网络的相移脉冲产生装置,其结构是:高精度相位移动电脉冲信号控制光信号选择传感网络上的FBG,完成大规模光纤光栅时分复用,包括以电信号相连的配置信息解析单元、脉宽信息单元、脉宽周期信息单元、第一级时延控制单元、第二级时延控制单元、脉冲控制单元、光栅位置信息存储控制单元、OSERDES并串转换单元。The phase-shift pulse generating device of the time-division multiplexing FBG sensor network provided by the present invention has a structure: a high-precision phase-shift electrical pulse signal controls an optical signal to select the FBG on the sensor network, and completes large-scale fiber grating time-division multiplexing, including The configuration information analysis unit, pulse width information unit, pulse width period information unit, first-level time delay control unit, second-level time delay control unit, pulse control unit, grating position information storage control unit, OSERDES and String conversion unit.

所述的配置信息解析单元,用于和上位机通讯并获取脉冲配置信息,该单元解析完毕的脉宽由脉宽信息单元存储,该单元由包括USB、网口、串口控制逻辑和ASCII码私有配置协议组成,由FPGA逻辑实现。The configuration information analysis unit is used to communicate with the host computer and obtain pulse configuration information. The pulse width analyzed by the unit is stored by the pulse width information unit, which is composed of USB, network port, serial port control logic and ASCII code private The configuration protocol is composed and implemented by FPGA logic.

所述的脉宽信息单元用于存储目标脉宽信息,由FPGA分布式RAM组成。The pulse width information unit is used to store target pulse width information and is composed of FPGA distributed RAM.

所述的脉冲控制单元用于控制和管理BRAM,由FPGA逻辑组成。The pulse control unit is used to control and manage BRAM, and is composed of FPGA logic.

所述的脉宽周期信息单元由FPGA内部分布式RAM组成,用于存储经配置信息解析单元解析完毕的脉冲周期。The pulse width period information unit is composed of FPGA internal distributed RAM, which is used to store the pulse period analyzed by the configuration information analysis unit.

所述第一级时延信息单元,用于存储经配置信息解析单元解析完毕的第一级时延,该第一级时延信息单元由FPGA内部分布式RAM组成;所述第二级时延信息单元为ODELAY第二级时延信息单元,用于存储经配置信息解析单元解析完毕的第二级时延,该单元由FPGA内部分别式RAM组成。The first-level time delay information unit is used to store the first-level time delay resolved by the configuration information analysis unit, and the first-level time delay information unit is composed of FPGA internal distributed RAM; the second-level time delay The information unit is the ODELAY second-level time delay information unit, which is used to store the second-level time delay analyzed by the configuration information analysis unit. This unit is composed of separate RAMs inside the FPGA.

所述的OSERDES并串转换单元由FPGA内部IO专用并串转换器OSERDES原语组成,一个OSERDES原语可以完成一个4:1的串并转换。The OSERDES parallel-to-serial conversion unit is composed of OSERDES primitives for IO-specific parallel-to-serial converters inside the FPGA, and one OSERDES primitive can complete a 4:1 serial-to-parallel conversion.

所述的光栅位置信息存储控制单元,用于产生脉冲信号,该单元由脉冲控制逻辑和FPGA内部BRAM阵列组成。The grating position information storage control unit is used to generate pulse signals, and the unit is composed of pulse control logic and FPGA internal BRAM array.

本发明提供的上述时分复用FBG传感网络的相移脉冲产生装置,其在实现时分复用FBG检测或者调制解调系统的光开关电信号的控制中的应用。The above-mentioned phase-shift pulse generating device of the time-division multiplexed FBG sensor network provided by the present invention is applied in the control of the optical switch electric signal of the time-division multiplexed FBG detection or modulation and demodulation system.

本发明装置应用时,采用以下步骤实现时分复用FBG检测或者调制解调系统的光开关电信号的控制:When the device of the present invention is applied, the following steps are adopted to realize the time division multiplexing FBG detection or the control of the optical switch electric signal of the modulation and demodulation system:

(1)上位机通过USB或者网口或者串口配置脉宽信息、脉宽周期信息、第一级时延、第二级时延;(1) The host computer configures pulse width information, pulse width cycle information, first-level delay, and second-level delay through USB, network port or serial port;

(2)依据步骤(1)所设置,产生两路延时脉冲信号,控制两路SOA的开关时间;这个延时时间对应于光在传感网络上的不同位置FBG的一次往返反射光程差,从而每个单独的FBG的反射信号就被送到CCD解调,而其他FBG的同阶反射信号就会被过滤。(2) According to the settings in step (1), two delayed pulse signals are generated to control the switching time of the two SOAs; this delayed time corresponds to the round-trip reflection optical path difference of the FBG at different positions of the light on the sensor network , so that the reflected signal of each individual FBG is sent to the CCD for demodulation, while the reflected signals of other FBGs of the same order are filtered.

本发明与现有技术相比具有以下主要的优点:Compared with the prior art, the present invention has the following main advantages:

1.能产生高精度的时延周期脉冲,控制SOA高速光开关分离并放大时分复用FBG阵列中的单个光栅的反射信号,同时准确定位单个光栅相对于环行器的准确空间位置。1. It can generate high-precision time-delay periodic pulses, control the SOA high-speed optical switch to separate and amplify the reflection signal of a single grating in the time-division multiplexed FBG array, and at the same time accurately locate the exact spatial position of a single grating relative to the circulator.

2.能在线光栅位置的自动扫描、存储;灵活获取任意单个光栅的状态;针对不同光栅阵列在线配置不同的扫描周期和脉宽。2. It can automatically scan and store the online grating position; flexibly obtain the state of any single grating; configure different scanning periods and pulse widths online for different grating arrays.

3.手动灵活操作单个光栅,进行光栅的在线检测,包括检测单个光栅的反射率,检查光栅铺设质量,分析光栅阵列或成缆光栅上的各种故障,并定位故障的位置。3. Manually and flexibly operate a single grating for on-line detection of the grating, including detecting the reflectivity of a single grating, checking the laying quality of the grating, analyzing various faults on the grating array or cabled grating, and locating the fault location.

4.经过简单复制,就可以产生多路时延脉冲对,可以直接应用于大规模空分复用系统,为实现大规模或超大规模的时分复用FBG传感网络系统产业化奠定了坚实的基础。4. After simple replication, multiple time-delayed pulse pairs can be generated, which can be directly applied to large-scale space-division multiplexing systems, laying a solid foundation for the industrialization of large-scale or ultra-large-scale time-division multiplexing FBG sensor network systems Base.

5.为大规模光栅阵列在线刻写工艺参数的监控,或野外施工质量的检查,以及时分复用FBG传感系统产业化迈开了关键的一步。5. It is a key step for the monitoring of large-scale grating array on-line writing process parameters, or the inspection of field construction quality, and the industrialization of time-division multiplexed FBG sensing systems.

总之,本发明解决了时分复用FBG传感网络的商用信号发生器不能自动扫描光纤光栅阵列的问题,而且大大提高了脉冲相移精度,成本低,集成度高,系统结构简单,可靠性好,可方便进行空分多路光栅阵列扩展。In a word, the present invention solves the problem that the commercial signal generator of the time-division multiplexing FBG sensor network cannot automatically scan the fiber grating array, and greatly improves the pulse phase shift accuracy, low cost, high integration, simple system structure, and good reliability , which can facilitate the expansion of the space division multiplex grating array.

附图说明Description of drawings

图1为本发明的基于Xilinx FPGA的时分复用光栅传感网络的相位延时脉冲产生方法的结构框图。Fig. 1 is the structural block diagram of the phase delay pulse generation method of the Xilinx FPGA-based time-division multiplexing grating sensor network of the present invention.

图2为本发明相位延时脉冲产生方法的初始化光栅阵列自动扫描模式示意图。FIG. 2 is a schematic diagram of the automatic scanning mode of the initialized grating array of the method for generating phase-delayed pulses of the present invention.

图3为本发明相位延时脉冲产生方法的正常工作模式示意图。FIG. 3 is a schematic diagram of a normal working mode of the method for generating phase-delayed pulses of the present invention.

图4为本发明相位延时脉冲产生方法的单个光栅调试/状态查询模式示意图。FIG. 4 is a schematic diagram of a single grating debugging/status query mode of the phase delay pulse generation method of the present invention.

图5为本发明较佳实施案例的功能结构图。Fig. 5 is a functional structural diagram of a preferred embodiment of the present invention.

图6为本发明的应用系统框图。Fig. 6 is a block diagram of the application system of the present invention.

具体实施方式detailed description

本发明公开了一种时分复用FBG传感网络的相移脉冲产生装置,该装置采用两级时延控制单元,能产生多路周期、脉宽可实时重配置的高精度延时脉冲控制光通路信号。第一级时延控制单元通过把脉冲波形映射到BRAM中完成,读出BRAM中的数据,串并转换到I/O接口;此级的精度最高达到0.625纳秒;第二级时延控制单元的精度为单步长78皮秒/52皮秒,共32阶可调,调节总时延为2.496纳秒/1.664纳秒。The invention discloses a phase-shift pulse generating device for a time-division multiplexing FBG sensor network. The device adopts a two-stage delay control unit and can generate a high-precision time-delay pulse control light with multiple channels and pulse widths that can be reconfigured in real time. pathway signal. The first-level delay control unit completes by mapping the pulse waveform to the BRAM, reads the data in the BRAM, and serially converts it to the I/O interface; the accuracy of this level can reach up to 0.625 nanoseconds; the second-level delay control unit The accuracy of the single step is 78 picoseconds/52 picoseconds, a total of 32 steps are adjustable, and the total adjustment delay is 2.496 nanoseconds/1.664 nanoseconds.

以下结合实施例及附图,对本发明作进一步详细说明。应当理解,此处所描述的具体实施例仅用以解释本发明,并不限定本发明。The present invention will be described in further detail below in conjunction with the embodiments and accompanying drawings. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

本实施例提供的时分复用FBG传感网络的相移脉冲产生装置,是一种基于XilinxFPGA的Virtex6系列和7系列而设计为高精度时延可调、脉冲周期和脉宽可重配的高速光开关控制的装置,该装置既适用于单个光栅的检测,也适用于具有大规模的时分复用FBG阵列,其结构如图1所示,包括上位机,以及以电信号相连的配置信息解析单元、脉宽信息单元、脉冲周期信息单元、第一级时延控制单元、第二级时延控制单元、脉冲控制单元、光栅位置信息存储控制单元、OSERDES,其中:配置信息解析单元把上位机的脉宽、周期、第一级时延和第二级时延信息分别发送到对应的脉冲控制单元、脉冲周期控制单元、第一级时延控制单元、第二级时延控制单元。配置信息解析单元将单个光栅的空间位置时延信息解析之后发送给光栅位置信息存储控制单元。上位机通过USB、网口、串口等常用接口把已采用私有协议定义的配置数据包发送到信号发生器。The phase-shift pulse generating device of the time-division multiplexing FBG sensor network provided in this embodiment is a high-speed high-speed device designed based on the Virtex6 series and 7 series of XilinxFPGA as high-precision time delay adjustable, pulse period and pulse width reconfigurable A device controlled by an optical switch. This device is suitable for both the detection of a single grating and a large-scale time-division multiplexing FBG array. Its structure is shown in Figure 1, including a host computer and an analysis of configuration information connected by electrical signals unit, pulse width information unit, pulse period information unit, first-level time delay control unit, second-level time delay control unit, pulse control unit, grating position information storage control unit, OSERDES, wherein: the configuration information analysis unit converts the upper computer The pulse width, period, first-level time delay and second-level time delay information are sent to the corresponding pulse control unit, pulse period control unit, first-level time delay control unit, and second-level time delay control unit respectively. The configuration information analysis unit analyzes the spatial position delay information of a single grating and sends it to the grating position information storage control unit. The upper computer sends the configuration data packet defined by the private protocol to the signal generator through common interfaces such as USB, network port, and serial port.

所述配置信息解析单元,用于和上位机通讯并获取脉冲配置信息,该单元解析完毕的脉宽由脉宽信息单元存储,该单元由USB、网口、串口等常用接口控制逻辑和ASCII码私有配置协议组成,由FPGA逻辑实现。The configuration information analysis unit is used to communicate with the host computer and obtain pulse configuration information. The pulse width analyzed by the unit is stored by the pulse width information unit. The unit is controlled by commonly used interfaces such as USB, network port, and serial port. Composed of private configuration protocols, implemented by FPGA logic.

所述脉宽信息单元由FPGA分布式RAM组成,用于存储目标脉宽信息。The pulse width information unit is composed of FPGA distributed RAM for storing target pulse width information.

所述脉冲控制单元用于控制和管理BRAM,由FPGA逻辑组成,完成BRAM的读写控制,实现脉冲时间上的波形映射到BRAM存储空间中。The pulse control unit is used to control and manage the BRAM, which is composed of FPGA logic, completes the read and write control of the BRAM, and realizes the waveform mapping of the pulse time to the BRAM storage space.

所述脉冲控制单元产生第一级时延精度为1纳秒,即I/O端口速度为1GHz。由两个OSERDES(FPGA IO专用并串转换单元)组成8:1的数据转换。BRAM中的数据宽度为8比特,对应的工作时钟为125MHz。如果设置脉冲周期为10微秒,则对应的BRAM的深度就是10×103/8=1250;如果设置脉宽为20纳秒,则1#脉冲控制单元写入连续20个“1”到BRAM,地址0和地址1写入数据8’bFF,地址2写入数据8’bF0。1#脉冲控制单元只要循环读取BRAM地址0~1249,中的数据,并且发送到OSERDES单元进行串并转换成1GHz的数据流,就产生了1#脉冲。类似的步骤产生2#脉冲。由于2#脉冲需要产生相对延时,这个时延信息是通过BRAM中的数据反映出来。比如,如果2#脉冲相对1#脉冲需要时延1纳秒,那么需要向2#脉冲的BRAM阵列中写入如下数据,地址0写入数据8’b7F,地址1写入数据8’bFF,地址2写入数据8’bF8。同步1#脉冲控制单元和2#脉冲控制单元的读地址,1纳秒的时延脉冲对就产生了。The pulse control unit generates the first-level time delay with an accuracy of 1 nanosecond, that is, the I/O port speed is 1 GHz. 8:1 data conversion is composed of two OSERDES (FPGA IO dedicated parallel-to-serial conversion unit). The data width in the BRAM is 8 bits, and the corresponding working clock is 125MHz. If the pulse period is set to 10 microseconds, the depth of the corresponding BRAM is 10×103/8=1250; if the pulse width is set to 20 nanoseconds, the 1# pulse control unit writes 20 consecutive “1”s to the BRAM, Address 0 and address 1 write data 8'bFF, address 2 write data 8'bF0. The 1# pulse control unit only needs to cyclically read the data in BRAM address 0~1249, and send it to the OSERDES unit for serial parallel conversion into The 1GHz data stream generates 1# pulse. Similar steps generate 2# pulse. Since the 2# pulse needs to generate a relative delay, this delay information is reflected by the data in the BRAM. For example, if the 2# pulse needs a delay of 1 nanosecond relative to the 1# pulse, then the following data needs to be written into the BRAM array of the 2# pulse, address 0 writes data 8'b7F, address 1 writes data 8'bFF, Address 2 writes data 8'bF8. Synchronize the read addresses of the 1# pulse control unit and the 2# pulse control unit, and a 1 nanosecond delay pulse pair is generated.

所述脉冲周期信息单元,用于存储经配置信息解析单元解析完毕的脉冲周期,该脉冲周期信息单元由FPGA内部分布式RAM组成。The pulse period information unit is used to store the pulse period analyzed by the configuration information analysis unit, and the pulse period information unit is composed of distributed RAM inside the FPGA.

所述第一级时延信息单元,用于存储经配置信息解析单元解析完毕的第一级时延,该第一级时延信息单元由FPGA内部分布式RAM组成。The first-level delay information unit is used to store the first-level delay analyzed by the configuration information analysis unit, and the first-level delay information unit is composed of distributed RAM inside the FPGA.

所述第二级时延信息单元为ODELAY第二级时延信息单元,用于存储经配置信息解析单元解析完毕的第二级时延,该第二级时延信息单元由FPGA内部分别式RAM组成。由于第一级时延精度为1纳秒,故该第二级时延单元只需要配置0~12拍的延时。The second-level time delay information unit is an ODELAY second-level time delay information unit, which is used to store the second-level time delay resolved by the configuration information analysis unit, and the second-level time delay information unit is composed of FPGA internal separate RAM composition. Since the accuracy of the first-level delay is 1 nanosecond, the second-level delay unit only needs to configure a delay of 0-12 beats.

所述ODELAY第二级时延信息单元,用于第二级微调时延控制脉冲信号,该单元由ODELAY控制逻辑和FPGA内部ODELAY原语组成。控制ODELAY原语的延时拍数,就可以进行时延的微调。根据最新Xilinx FGPA 7系列器件特性,此级时延步长为78皮秒/52皮秒,共32阶可调,调节总时延为2.496纳秒/1.664纳秒。随着FGPA器件IO接口速度的提升,此级时延精度可进一步提高。The ODELAY second-level delay information unit is used for the second-level fine-tuning delay control pulse signal, and the unit is composed of ODELAY control logic and FPGA internal ODELAY primitives. By controlling the number of delay beats of the ODELAY primitive, the delay can be fine-tuned. According to the characteristics of the latest Xilinx FGPA 7 series devices, the delay step of this stage is 78 picoseconds/52 picoseconds, with a total of 32 adjustable steps, and the total adjusted delay is 2.496 nanoseconds/1.664 nanoseconds. With the improvement of the IO interface speed of FPGA devices, the delay accuracy of this level can be further improved.

所述OSERDES并串转换单元,是FPGA内部IO专用并串转换器OSERDES原语组成。一个OSERDES原语可以完成一个4:1的串并转换。The OSERDES parallel-to-serial conversion unit is composed of OSERDES primitives dedicated to the internal IO of the FPGA. An OSERDES primitive can complete a 4:1 serial-to-parallel conversion.

所述光栅位置信息存储控制单元,用于产生脉冲信号,该单元由脉冲控制逻辑和FPGA内部BRAM阵列组成。当在某一时延下,CCD波长峰值检测到最大值时,上位机就把对应的光栅编号和时延信息写入配置信息解析单元。光栅位置信息存储控制单元接收到信号之后,分别写入BRAM和外部Flash的数据区。1#脉冲控制单元和2#脉冲控制单元根据不同工作模式分别读取对应光栅时延数据,写入到各自的BRAM阵列中。The grating position information storage control unit is used to generate pulse signals, and the unit is composed of pulse control logic and FPGA internal BRAM array. When the CCD wavelength peak value detects the maximum value under a certain time delay, the host computer writes the corresponding grating number and time delay information into the configuration information analysis unit. After receiving the signal, the grating position information storage control unit writes it into the data area of BRAM and external Flash respectively. The 1# pulse control unit and the 2# pulse control unit respectively read the corresponding grating delay data according to different working modes, and write them into their respective BRAM arrays.

所述上位机采用通用个人电脑或者工作站,安装串口/USB/网络调试工具等测试软件,传递命令信息。The upper computer adopts a general-purpose personal computer or a workstation, installs testing software such as serial port/USB/network debugging tools, and transmits command information.

本实施例提供的时分复用FBG传感网络的相移脉冲产生装置,其外部设有电信号连接的flash非易失存储器用来上电配置FPGA程序,以及掉电保存单个光纤光栅的信息,包括空间位置、反射率等。The phase-shift pulse generating device of the time-division multiplexing FBG sensor network provided by this embodiment is provided with a flash non-volatile memory connected by an electric signal to be used for power-on configuration FPGA program, and to save the information of a single fiber grating when power-off. Including spatial position, reflectivity, etc.

本实施例提供的时分复用FBG传感网络的相移脉冲产生装置,其工作过程由以下三种典型的工作模式实现:The phase-shift pulse generating device of the time-division multiplexing FBG sensor network provided by this embodiment, its working process is realized by the following three typical working modes:

初始化光栅阵列自动扫描模式(图2):接收到上位机的进入初始化光栅阵列自动扫描模式指令后,相位延时脉冲工作在指定的工作模式。脉冲周期和脉宽参数随时都可以被上位机重新设置,如果没有配置,则使用默认参数,脉冲周期100KHz和脉宽20纳秒。根据第一级时延精度1纳秒,2#脉冲移动1纳秒延时;根据CCD的布拉格波长反射,是否存在波长峰值对应的时延数值,如果不是波长峰值,则增加一个时延步长1纳秒,继续判断是否存在局部峰值波长;如果是波长峰值,则进入第二级峰值波长时延值微调。原理类似第一级时延调节,配置第二级时延的拍数,递归找到峰值波长对应的精确时延数值。这个时延数值通过光栅位置信息存储控制单元写入BRAM阵列和外部Flash数据区。如果1#和2#时延值超过一个周期则全部的光栅已经扫描完毕,推出初始化光栅阵列自动扫描模式。Initialize grating array automatic scanning mode (Fig. 2): After receiving the instruction from the host computer to enter the initializing grating array automatic scanning mode, the phase delay pulse works in the specified working mode. The pulse period and pulse width parameters can be reset by the host computer at any time, if not configured, use the default parameters, pulse period 100KHz and pulse width 20 nanoseconds. According to the first-level delay accuracy of 1 nanosecond, the 2# pulse moves 1 nanosecond delay; according to the Bragg wavelength reflection of the CCD, whether there is a delay value corresponding to the wavelength peak, if it is not the wavelength peak, add a delay step 1 nanosecond, continue to judge whether there is a local peak wavelength; if it is a wavelength peak, enter the second level of fine-tuning of the peak wavelength delay value. The principle is similar to the first-level delay adjustment, configure the beats of the second-level delay, and recursively find the exact delay value corresponding to the peak wavelength. This delay value is written into the BRAM array and the external Flash data area through the grating position information storage control unit. If the delay value of 1# and 2# exceeds one cycle, all the gratings have been scanned, and the automatic scanning mode of the initialized grating array is launched.

正常工作模式(图3):接收到上位机进入正常工作指令后,相位延时脉冲发生器工作在指定的工作模式。脉冲控制单元从光栅位置信息存储控制单元里顺序读出单个光栅的位置信息,根据读出的数值,配置两路时延脉冲。从CCD的采样值中计算出峰值波长,完成之后,光栅标号加1,进入下一个光栅检测。如果由于系统误差导致峰值波长没有一次计算出,可以再发送当前光栅的延时脉冲,继续计算本光栅的峰值波长。Normal working mode (Figure 3): After receiving the host computer to enter the normal working order, the phase delay pulse generator works in the specified working mode. The pulse control unit sequentially reads the position information of a single grating from the grating position information storage control unit, and configures two delay pulses according to the read values. Calculate the peak wavelength from the sampled value of the CCD. After completion, add 1 to the grating label and enter the next grating detection. If the peak wavelength is not calculated once due to system error, you can send the delayed pulse of the current grating to continue calculating the peak wavelength of this grating.

单个光栅调试/状态查询模式(图4):接收到上位机进入单个光栅调试/状态查询模式指令后,相位延时脉发生器工作在指定的工作模式。这个模式相位延时脉冲发生器是从模式,根据上位机配置的时延数值,发出两路对应的脉冲。上位机可以手动测试/调试单个光栅传感器。Single grating debugging/status query mode (Figure 4): After receiving the command from the host computer to enter single grating debugging/status querying mode, the phase delay pulse generator works in the specified working mode. In this mode, the phase delay pulse generator is a slave mode, and sends out two corresponding pulses according to the delay value configured by the host computer. The host computer can manually test/debug a single grating sensor.

应当理解的是,对本领域普通技术人员来说,可以根据上述说明加以改进或变换,比如更换FPGA器件,而所有这些改进和变换都应属于本发明所附权利要求的保护范围。It should be understood that those skilled in the art can make improvements or transformations based on the above description, such as replacing the FPGA device, and all these improvements and transformations should fall within the protection scope of the appended claims of the present invention.

Claims (10)

1.一种时分复用FBG传感网络的相移脉冲产生装置,其特征是高精度相位移动电脉冲信号控制光信号选择传感网络上的FBG,完成大规模光纤光栅时分复用,其结构包括上位机,以及以电信号相连的配置信息解析单元、脉宽信息单元、脉宽周期信息单元、第一级时延控制单元、第二级时延控制单元、脉冲控制单元、光栅位置信息存储控制单元、OSERDES并串转换单元,其中:配置信息解析单元把上位机的脉宽、周期、第一级时延和第二级时延信息分别发送到对应的脉冲控制单元、脉冲周期信息单元、第一级时延控制单元、第二级时延控制单元;配置信息解析单元将单个光栅的空间位置时延信息解析之后发送给光栅位置信息存储控制单元。1. A phase-shift pulse generating device for a time-division multiplexing FBG sensor network, characterized in that the high-precision phase-shift electric pulse signal controls the optical signal to select the FBG on the sensor network, and completes the time-division multiplexing of large-scale fiber gratings. Its structure Including the upper computer, and the configuration information analysis unit, pulse width information unit, pulse width period information unit, first-level delay control unit, second-level delay control unit, pulse control unit, and grating position information storage unit connected by electrical signals Control unit, OSERDES parallel-serial conversion unit, wherein: the configuration information analysis unit sends the pulse width, period, first-level delay and second-level delay information of the upper computer to the corresponding pulse control unit, pulse period information unit, The first-level delay control unit, the second-level delay control unit; the configuration information analysis unit analyzes the spatial position delay information of a single grating and sends it to the grating position information storage control unit. 2.根据权利要求1所述的时分复用FBG传感网络的相移脉冲产生装置,其特征是所述的配置信息解析单元,用于和上位机通讯并获取脉冲配置信息,该单元解析完毕的脉宽由脉宽信息单元存储,该单元由包括USB、网口、串口控制逻辑和ASCII码私有配置协议组成,由FPGA逻辑实现。2. the phase-shift pulse generating device of time division multiplexing FBG sensor network according to claim 1, is characterized in that described configuration information analyzing unit, is used for and upper computer communication and obtains pulse configuration information, and this unit has analyzed The pulse width is stored by the pulse width information unit, which is composed of USB, network port, serial port control logic and ASCII code private configuration protocol, and is implemented by FPGA logic. 3.根据权利要求1所述的时分复用FBG传感网络的相移脉冲产生装置,其特征是所述的脉宽信息单元用于存储目标脉宽信息,由FPGA分布式RAM组成。3. The phase-shift pulse generating device of the time-division multiplexing FBG sensor network according to claim 1, wherein the pulse width information unit is used for storing target pulse width information and is composed of FPGA distributed RAM. 4.根据权利要求1所述的时分复用FBG传感网络的相移脉冲产生装置,其特征是所述的脉冲控制单元用于控制和管理FPGA内部BRAM,由FPGA逻辑组成。4. The phase-shift pulse generating device of time-division multiplexing FBG sensor network according to claim 1, characterized in that said pulse control unit is used for controlling and managing FPGA internal BRAM, and is made up of FPGA logic. 5.根据权利要求1所述的时分复用FBG传感网络的相移脉冲产生装置,其特征是所述的脉宽周期信息单元由FPGA内部分布式RAM组成,用于存储经配置信息解析单元解析完毕的脉冲周期。5. the phase-shift pulse generation device of time division multiplexing FBG sensor network according to claim 1, it is characterized in that described pulse width period information unit is made up of distributed RAM in FPGA, is used for storing through configuration information analysis unit The parsed pulse period. 6.根据权利要求1所述的时分复用FBG传感网络的相移脉冲产生装置,其特征是所述第一级时延信息单元,用于存储经配置信息解析单元解析完毕的第一级时延,该第一级时延信息单元由FPGA内部分布式RAM组成;所述第二级时延信息单元为ODELAY第二级时延信息单元,用于存储经配置信息解析单元解析完毕的第二级时延,该单元由FPGA内部分布式RAM组成。6. the phase-shift pulse generation device of time-division multiplexing FBG sensor network according to claim 1, is characterized in that described first-level time delay information unit, is used for storing the first level that has resolved through configuration information analysis unit Delay, the first-level delay information unit is composed of FPGA internal distributed RAM; the second-level delay information unit is the ODELAY second-level delay information unit, which is used to store the first-order information unit that has been parsed by the configuration information analysis unit Second-level delay, the unit is composed of distributed RAM inside the FPGA. 7.根据权利要求1所述的时分复用FBG传感网络的相移脉冲产生装置,其特征是所述的OSERDES并串转换单元由FPGA内部IO专用并串转换器OSERDES原语组成,一个OSERDES原语可以完成一个4:1的串并转换。7. the phase-shift pulse generation device of time-division multiplexing FBG sensor network according to claim 1 is characterized in that described OSERDES parallel-serial conversion unit is made up of special-purpose parallel-serial converter OSERDES primitive language of IO inside FPGA, an OSERDES The primitive can complete a 4:1 serial-to-parallel conversion. 8.根据权利要求1所述的时分复用FBG传感网络的相移脉冲产生装置,其特征是所述的光栅位置信息存储控制单元,用于产生脉冲信号,该单元由脉冲控制逻辑和FPGA内部BRAM阵列组成。8. the phase-shift pulse generation device of time-division multiplexing FBG sensor network according to claim 1, is characterized in that described grating position information storage control unit, is used for generating pulse signal, and this unit is made up of pulse control logic and FPGA internal BRAM array composition. 9.权利要求1至8中任一权利要求所述时分复用FBG传感网络的相移脉冲产生装置的应用,其特征是在实现时分复用FBG检测或者调制解调系统的光开关电信号的控制中的应用。9. The application of the phase-shift pulse generating device of the time-division multiplexing FBG sensor network according to any one of claims 1 to 8, characterized in that it realizes the optical switch electrical signal of the time-division multiplexing FBG detection or modulation and demodulation system applications in the control. 10.根据权利要求9所述的应用,其特征是应用时,采用以下步骤实现时分复用FBG检测或者调制解调系统的光开关电信号的控制:10. application according to claim 9, it is characterized in that during application, adopt the following steps to realize the control of the optical switch electrical signal of time division multiplexing FBG detection or modulation and demodulation system: (1)上位机通过USB或者网口或者串口配置脉宽信息、脉宽周期信息、第一级时延、第二级时延;(1) The host computer configures pulse width information, pulse width cycle information, first-level delay, and second-level delay through USB, network port or serial port; (2)依据步骤(1)所设置,产生两路延时脉冲信号,控制两路SOA的开关时间;该两路SOA的开关时间差对应于光在传感网络上的不同位置FBG的一次往返反射光程差,从而每个单独的FBG的反射信号就被送到CCD解调,而其他FBG的同阶反射信号就会被过滤。(2) According to the setting in step (1), two-way delay pulse signals are generated to control the switching time of the two SOAs; the switching time difference of the two SOAs corresponds to a round-trip reflection of light at different positions of the FBG on the sensor network The optical path difference, so that the reflected signal of each individual FBG is sent to the CCD for demodulation, while the reflected signals of other FBGs of the same order are filtered.
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