CN104596553A - Phase-shift pulse generation device for time division multiplexing FBG sensor network - Google Patents
Phase-shift pulse generation device for time division multiplexing FBG sensor network Download PDFInfo
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Abstract
The invention discloses a phase-shift pulse generation device for a time division multiplexing FBG sensor network. The device is characterized in that an FBG on the sensor network is elected through a high-precision phase-shift electric pulse signal controlling an optical signal so as to finish the time division multiplexing of large-scale optical fibers. The device comprises a configuration information analyzing unit, a pulse width information unit, a pulse width cycle information unit, a first-stage time delay control unit, a second-stage time delay control unit, a pulse control unit, a FBG position information storing control unit and an OSERDES parallel-serial conversion unit which are connected through electric signals. According to the pulse-shift pulse generation device and method, the problem that the FBG cannot be automatically scanned through a commercial signal generator can be solved; in addition, the pulse phase shift precision can be greatly improved; the cost is low; the integrity is high; the system structure is simple; the reliability is high; the time division multi-way FBG array expansion can be carried out conveniently.
Description
Technical field
The present invention relates to optical fiber grating sensing network field, particularly relate to a kind of phase-shifted pulse production method of time division multiplex FBG sensing network, the control of the photoswitch electric signal of time division multiplex FBG detection or modulation demodulation system can be realized.
Background technology
The advantage of weak optical fiber Bragg grating sensing network is that crosstalk is little, multiplexing capacity is strong and the advantage such as cost performance is high, is expected to realize quasi-distributed detection in the rugged surroundings such as oil field, tunnel, building health monitoring.At present, " grating is inscribed online " technology can keep at a certain distance away and automatically inscribe grating array in fiber draw process.This technology not only avoids contact loss when traditional raster is fused into array, and the space distribution closeness of grating, the capacity of sensor array have had the lifting of matter.So just put forward higher requirement for the detection of time division multiplex FBG or sensing network system.Time-division multiplex technology utilizes the interval characteristics of the reflected signal of sensor in time domain, and effectively can suppress the state of the crosstalk of grating and each sensor of flexible monitoring, be effective a kind of application process in time division multiplex FBG sensor-based system.In time division multiplex system, each sensing grating has different time delays, and the signal generator controlling the high-speed optical switch of light pulse turnover grating array directly has influence on measuring accuracy and the performance of supervisory system.Therefore, the phase-shifted pulse production method studying time division multiplex FBG sensing network is necessary.
Document " An interrogation system for a sensor array with 1310nm band ultra-weak fiber Bragggratings " (Optical Engineer, J.) proposes and a kind ofly utilizes two SOA high speed optoelectronic switches to realize the modulation and demodulation system of time division multiplex FBG sensing network.In modulation module, a SOA high speed optoelectronic switch is connected with little wideband light source, modulates and amplify light signal; Another SOA high speed optoelectronic switch is selected the light pulse of returning through optical grating reflection exported from circulator and is separated in sampling module, completes demodulation function.The different two-way of phase delay periodically electric impulse signal controls this two SOA high speed optoelectronic switches.This time delay just corresponds to the twice light path of grating and circulator distance.What adopt due to this system is commercial signal generator, and system can only produce light pulse control signal by Non-follow control, does not possess the functions such as On-line Control raster array, automatic cycle scanning, seriously hinders the commercialization process of system.In addition, Commercial signal generators can only produce the pulse delay of nanosecond, and precision also can not meet the growing performance requirement of system.
Summary of the invention
The technical problem to be solved in the present invention is: for cannot the problem of on-line automatic generation target light pulse control signal in existing time division multiplex time division multiplex FBG sensing network system, a kind of phase-shifted pulse generation device of time division multiplex FBG sensing network is provided, this device can realize time division multiplex FBG sensor automatic location, storage, and the parameters such as the pulsewidth of pulse, cycle completely can the picosecond phase delay pulse of reprovision online.
The technical solution adopted for the present invention to solve the technical problems is:
The phase-shifted pulse generation device of time division multiplex FBG sensing network provided by the invention, its structure is: high-precision phase position moves the FBG on electric impulse signal control light signal selection sensing network, complete large-scale optical fiber grating time division multiplex, comprise the configuration information resolution unit, pulse width information unit, pulse width period message unit, first order time delay control unit, second level time delay control unit, pulse control unit, stop position information storage control unit, the OSERDES parallel serial conversion unit that are connected with electric signal.
Described configuration information resolution unit, for obtaining pulse configuration information with upper machine communication, the complete pulsewidth of this unit resolves is stored by pulse width information unit, and this unit forms by comprising USB, network interface, serial ports steering logic and the privately owned configuration protocol of ASCII character, is realized by fpga logic.
Described pulse width information unit, for storing target pulse width information, is made up of the distributed RAM of FPGA.
Described pulse control unit is used for control and management BRAM, is made up of fpga logic.
Described pulse width period message unit is made up of the inner distributed RAM of FPGA, is configured the information analysis unit resolves complete recurrence interval for storing.
Described first order Delay unit, is configured the complete first order time delay of information analysis unit resolves for storing, and this first order Delay unit is made up of the inner distributed RAM of FPGA; Described second level Delay unit is ODELAY second level Delay unit, is configured the complete second level time delay of information analysis unit resolves for storing, this unit by FPGA inside respectively formula RAM form.
Described OSERDES parallel serial conversion unit is made up of the inner IO of FPGA special parallel-to-serial converter OSERDES primitive, and an OSERDES primitive can complete the serioparallel exchange of a 4:1.
Described stop position information storage control unit, for generation of pulse signal, this unit is made up of Pulse Width Control logic and the inner BRAM array of FPGA.
The phase-shifted pulse generation device of above-mentioned time division multiplex FBG sensing network provided by the invention, its realize time division multiplex FBG detect or modulation demodulation system photoswitch electric signal control in application.
During apparatus of the present invention application, following steps are adopted to realize the control of the photoswitch electric signal of time division multiplex FBG detection or modulation demodulation system:
(1) host computer is by USB or network interface or serial ports configuration pulse width information, pulse width period information, first order time delay, second level time delay;
(2) according to set by step (1), produce two-way delay pulse signal, control the switching time of two-way SOA; This delay time corresponds to the once round reflected light path difference of the diverse location FBG of light on sensing network, thus the reflected signal of each independent FBG is just sent to CCD demodulation, and the same order reflected signal of other FBG will be filtered.
The present invention compared with prior art has following main advantage:
1. can produce high-precision delay period pulse, control SOA high-speed optical switch is separated and amplifies the reflected signal of the single grating in time division multiplex FBG array, accurately locates the exact space position of single grating relative to circulator simultaneously.
2. can the autoscan of online stop position, storage; The state of any single grating of flexible acquisition; The scan period different for different grating array Configuration Online and pulsewidth.
3. the single grating of manual flexible operating, carries out the on-line checkingi of grating, comprises the reflectivity detecting single grating, checks grating laying quality, analyzes the various faults on grating array or stranding grating, and the position of localizing faults.
4. through simple copy, just can producing multiple delay pulse pair, extensive SDM system can be directly applied to, having established solid foundation for realizing extensive or ultra-large time division multiplex FBG sensing network system industrialization.
5. be the monitoring of the online scribing process parameter of extensive grating array, or the inspection of field construction quality, and the industrialization of time division multiplex FBG sensor-based system has taken a crucial step.
In a word, the Commercial signal generators that the invention solves time division multiplex FBG sensing network can not the problem of autoscan optical fiber optical grating array, and substantially increase pulse Phase shift precision, cost is low, integrated level is high, system architecture is simple, and good reliability, can conveniently carry out the expansion of space division multiplexing grating array.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the phase delay method for generating pulse of the time division multiplex grating sensing network based on Xilinx FPGA of the present invention.
Fig. 2 is the initialization grating array autoscan pattern diagram of phase delay method for generating pulse of the present invention.
Fig. 3 is the normal mode of operation schematic diagram of phase delay method for generating pulse of the present invention.
Fig. 4 is the single grating debugging/status poll pattern diagram of phase delay method for generating pulse of the present invention.
Fig. 5 is the functional structure chart of the better case study on implementation of the present invention.
Fig. 6 is application system block diagram of the present invention.
Embodiment
The invention discloses a kind of phase-shifted pulse generation device of time division multiplex FBG sensing network, this device adopts two-stage time delay control unit, can produce the multichannel cycle, pulsewidth the high precision delay pulse of Runtime reconfiguration can control light-path signal.First order time delay control unit completes by pulse waveform is mapped in BRAM, and read the data in BRAM, serioparallel exchange is to I/O interface; The precision of this grade was up to for 0.625 nanosecond; The precision of second level time delay control unit is long 78 psec/52 psecs of single step, and totally 32 rank are adjustable, regulate overall delay be 2.496 nanosecond/1.664 nanoseconds.
Below in conjunction with embodiment and accompanying drawing, the present invention is described in further detail.Should be appreciated that specific embodiment described herein only in order to explain the present invention, do not limit the present invention.
The phase-shifted pulse generation device of the time division multiplex FBG sensing network that the present embodiment provides, a kind of Virtex6 based on Xilinx FPGA series and 7 serial and to be designed to high-precision time-delay adjustable, recurrence interval and pulsewidth can the devices that control of the high-speed optical switch of reprovision, this device had both been applicable to the detection of single grating, also be applicable to that there is large-scale time division multiplex FBG array, its structure as shown in Figure 1, comprise host computer, and with the configuration information resolution unit that electric signal is connected, pulse width information unit, recurrence interval message unit, first order time delay control unit, second level time delay control unit, pulse control unit, stop position information storage control unit, OSERDES, wherein: configuration information resolution unit is the pulsewidth of host computer, cycle, first order time delay and second level Delay are sent to corresponding pulse control unit respectively, recurrence interval control module, first order time delay control unit, second level time delay control unit.Configuration information resolution unit sends to stop position information storage control unit after being resolved by the locus Delay of single grating.Host computer is sent to signal generator by common interfaces such as USB, network interface, serial ports the configuration data bag adopting proprietary protocol to define.
Described configuration information resolution unit, for obtaining pulse configuration information with upper machine communication, the complete pulsewidth of this unit resolves is stored by pulse width information unit, and this unit is made up of the common interfaces steering logics such as USB, network interface, serial ports and the privately owned configuration protocol of ASCII character, is realized by fpga logic.
Described pulse width information unit is made up of the distributed RAM of FPGA, for storing target pulse width information.
Described pulse control unit is used for control and management BRAM, and be made up of fpga logic, complete the Read-write Catrol of BRAM, the waveform realized on the burst length is mapped in BRAM storage space.
It was 1 nanosecond that described pulse control unit produces first order time delay precision, and namely I/O port speed is 1GHz.The data being made up of 8:1 two OSERDES (the special parallel serial conversion unit of FPGA IO) are changed.Data width in BRAM is 8 bits, and corresponding work clock is 125MHz.If arranging the recurrence interval is 10 microseconds, then the degree of depth of corresponding BRAM is exactly 10 × 103/8=1250; If arranging pulsewidth was 20 nanoseconds, then 1# pulse control unit write continuous 20 " 1 " is to BRAM, and address 0 and address 1 write data 8 ' bFF, and address 2 writes data 8 ' bF0.As long as BRAM address 0 ~ 1249 is read in the circulation of 1# pulse control unit, in data, and be sent to OSERDES unit and carry out the data stream that serioparallel exchange becomes 1GHz, just create 1# pulse.Similar step produces 2# pulse.Because 2# pulse needs to produce relative time delay, this Delay is reflected by the data in BRAM.Such as, if 2# pulsion phase needs time delay 1 nanosecond to 1# pulse, so need to write following data in the BRAM array of 2# pulse, address 0 writes data 8 ' b7F, and address 1 writes data 8 ' bFF, and address 2 writes data 8 ' bF8.Synchronous 1# pulse control unit and 2# pulse control unit read address, the time delay pulse of 1 nanosecond is to just creating.
Described recurrence interval message unit, is configured the information analysis unit resolves complete recurrence interval for storing, and this recurrence interval message unit is made up of the inner distributed RAM of FPGA.
Described first order Delay unit, is configured the complete first order time delay of information analysis unit resolves for storing, and this first order Delay unit is made up of the inner distributed RAM of FPGA.
Described second level Delay unit is ODELAY second level Delay unit, is configured the complete second level time delay of information analysis unit resolves for storing, this second level Delay unit by FPGA inside respectively formula RAM form.Because first order time delay precision was 1 nanosecond, therefore the time delay that this second level time delay elements only needs configuration 0 ~ 12 to clap.
Described ODELAY second level Delay unit, for second level fine setting timing_delay estimation pulse signal, this unit is made up of ODELAY steering logic and the inner ODELAY primitive of FPGA.The time delay umber of beats of control ODELAY primitive, just can carry out the fine setting of time delay.According to up-to-date Xilinx FGPA 7 family device characteristic, this grade of time delay step-length is 78 psec/52 psecs, and totally 32 rank are adjustable, regulate overall delay be 2.496 nanosecond/1.664 nanoseconds.Along with the lifting of FGPA device I/O interface speed, this grade of time delay precision can further improve.
Described OSERDES parallel serial conversion unit is the inner IO of FPGA special parallel-to-serial converter OSERDES primitive composition.An OSERDES primitive can complete the serioparallel exchange of a 4:1.
Described stop position information storage control unit, for generation of pulse signal, this unit is made up of Pulse Width Control logic and the inner BRAM array of FPGA.When under a certain time delay, when CCD wavelength peak detects maximal value, host computer is just the grating of correspondence numbering and Delay write configuration information resolution unit.After stop position information storage control unit receives signal, write the data field of BRAM and outside Flash respectively.1# pulse control unit and 2# pulse control unit read corresponding grating delay data respectively according to different working modes, are written in respective BRAM array.
Described host computer adopts general purpose personal computer or workstation, installs the testing softwares such as serial ports/USB/ Networked E-Journals instrument, transferring command information.
The phase-shifted pulse generation device of the time division multiplex FBG sensing network that the present embodiment provides, its outside is provided with flash nonvolatile memory that electric signal connects and is used for powering on configuration FPGA program, and the information of single fiber grating is preserved in power down, comprises locus, reflectivity etc.
The phase-shifted pulse generation device of the time division multiplex FBG sensing network that the present embodiment provides, its course of work is realized by following three kinds of typical mode of operations:
Initialization grating array autoscan pattern (Fig. 2): receive host computer enter initialization grating array autoscan mode instruction after, the mode of operation that phase delay pulsed operation is being specified.Recurrence interval and width parameter are reset by host computer at any time, if not configuration, then use default parameters, recurrence interval 100KHz and pulsewidth 20 nanosecond.According to first order time delay precision 1 nanosecond, the time delay of 1 nanosecond is moved in 2# pulse; Bragg wavelength according to CCD reflects, and whether there is the time delay numerical value that wavelength peak is corresponding, if not wavelength peak, then increases time delay step-length 1 nanosecond, continues to judge whether to there is local peaking's wavelength; If wavelength peak, then enter second level peak wavelength time delay value fine setting.The similar first order delay adjusting of principle, the umber of beats of configuration second level time delay, the precise delay numerical value that recurrence finds peak wavelength corresponding.This time delay numerical value is by stop position information storage control unit write BRAM array and outside Flash data district.If 1# and 2# time delay value exceedes one-period, whole gratings is scanned, releases initialization grating array autoscan pattern.
Normal mode of operation (Fig. 3): receive after host computer enters normal work order, phase delay pulse producer is operated in the mode of operation of specifying.Pulse control unit sequentially reads the positional information of single grating from stop position information storage control unit, according to the numerical value read, and the pulse of configuration two-way time delay.From the sampled value of CCD, calculate peak wavelength, after completing, grating label adds 1, enters next Grating examinations.If because systematic error causes peak wavelength once not calculate, the delay pulse of current raster can be sent again, continue the peak wavelength calculating this grating.
Single grating debugging/status poll pattern (Fig. 4): receive after host computer enters single grating debugging/status poll mode instruction, phase delay arteries and veins generator is operated in the mode of operation of specifying.This modal phase delay pulse generator is from pattern, according to the time delay numerical value of host computer configuration, sends the pulse that two-way is corresponding.Host computer can manual test/debug single grating sensor.
Should be understood that, for those of ordinary skills, can be improved according to the above description or convert, such as change FPGA device, and all these improve and convert the protection domain that all should belong to claims of the present invention.
Claims (10)
1. the phase-shifted pulse generation device of a time division multiplex FBG sensing network, it is characterized in that high-precision phase position moves the FBG on electric impulse signal control light signal selection sensing network, complete large-scale optical fiber grating time division multiplex, its structure comprises the configuration information resolution unit, pulse width information unit, pulse width period message unit, first order time delay control unit, second level time delay control unit, pulse control unit, stop position information storage control unit, the OSERDES parallel serial conversion unit that are connected with electric signal.
2. the phase-shifted pulse generation device of time division multiplex FBG sensing network according to claim 1, it is characterized in that described configuration information resolution unit, for obtaining pulse configuration information with upper machine communication, the complete pulsewidth of this unit resolves is stored by pulse width information unit, this unit forms by comprising USB, network interface, serial ports steering logic and the privately owned configuration protocol of ASCII character, is realized by fpga logic.
3. the phase-shifted pulse generation device of time division multiplex FBG sensing network according to claim 1, is characterized in that described pulse width information unit is for storing target pulse width information, is made up of the distributed RAM of FPGA.
4. the phase-shifted pulse generation device of time division multiplex FBG sensing network according to claim 1, is characterized in that described pulse control unit is for control and management BRAM, is made up of fpga logic.
5. the phase-shifted pulse generation device of time division multiplex FBG sensing network according to claim 1, is characterized in that described pulse width period message unit is made up of the inner distributed RAM of FPGA, being configured the information analysis unit resolves complete recurrence interval for storing.
6. the phase-shifted pulse generation device of time division multiplex FBG sensing network according to claim 1, it is characterized in that described first order Delay unit, be configured the complete first order time delay of information analysis unit resolves for storing, this first order Delay unit is made up of the inner distributed RAM of FPGA; Described second level Delay unit is ODELAY second level Delay unit, is configured the complete second level time delay of information analysis unit resolves for storing, this unit by FPGA inside respectively formula RAM form.
7. the phase-shifted pulse generation device of time division multiplex FBG sensing network according to claim 1, it is characterized in that described OSERDES parallel serial conversion unit is made up of the inner IO of FPGA special parallel-to-serial converter OSERDES primitive, an OSERDES primitive can complete the serioparallel exchange of a 4:1.
8. the phase-shifted pulse generation device of time division multiplex FBG sensing network according to claim 1, is characterized in that described stop position information storage control unit, and for generation of pulse signal, this unit is made up of Pulse Width Control logic and the inner BRAM array of FPGA.
9. the application of the phase-shifted pulse generation device of time division multiplex FBG sensing network described in arbitrary claim in claim 1 to 8, it is characterized in that realize time division multiplex FBG detect or modulation demodulation system photoswitch electric signal control in application.
10. application according to claim 9, when it is characterized in that application, adopts following steps to realize the control of the photoswitch electric signal of time division multiplex FBG detection or modulation demodulation system:
(1) host computer is by USB or network interface or serial ports configuration pulse width information, pulse width period information, first order time delay, second level time delay;
(2) according to set by step (1), produce two-way delay pulse signal, control the switching time of two-way SOA; This delay time corresponds to the once round reflected light path difference of the diverse location FBG of light on sensing network, thus the reflected signal of each independent FBG is just sent to CCD demodulation, and the same order reflected signal of other FBG will be filtered.
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