CN104576771A - Solar cell and manufacture method thereof - Google Patents
Solar cell and manufacture method thereof Download PDFInfo
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- CN104576771A CN104576771A CN201310493029.3A CN201310493029A CN104576771A CN 104576771 A CN104576771 A CN 104576771A CN 201310493029 A CN201310493029 A CN 201310493029A CN 104576771 A CN104576771 A CN 104576771A
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- 238000000034 method Methods 0.000 title claims description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 88
- 239000000758 substrate Substances 0.000 claims abstract description 83
- 230000000149 penetrating effect Effects 0.000 claims abstract description 58
- 239000004020 conductor Substances 0.000 claims description 20
- 238000005245 sintering Methods 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 5
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- 239000005297 pyrex Substances 0.000 claims description 4
- 229920000642 polymer Polymers 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 abstract description 10
- 239000010410 layer Substances 0.000 description 99
- 230000005684 electric field Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000002310 reflectometry Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010422 painting Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000010248 power generation Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- KMWBBMXGHHLDKL-UHFFFAOYSA-N [AlH3].[Si] Chemical compound [AlH3].[Si] KMWBBMXGHHLDKL-UHFFFAOYSA-N 0.000 description 1
- UMVBXBACMIOFDO-UHFFFAOYSA-N [N].[Si] Chemical compound [N].[Si] UMVBXBACMIOFDO-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000001012 protector Effects 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Electromagnetism (AREA)
- Sustainable Development (AREA)
- Sustainable Energy (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Life Sciences & Earth Sciences (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Photovoltaic Devices (AREA)
Abstract
The invention discloses a solar cell which comprises a semiconductor substrate, an emitter layer, at least one first electrode, at least one second electrode and a dielectric layer, wherein the semiconductor substrate is provided with a first surface, a second surface opposite to the first surface as well as at least one through channel penetrating through the first surface and the second surface; the emitter layer is formed on the first surface, the second surface and the through channel of the semiconductor substrate; a pn junction is formed between the semiconductor substrate and the emitter layer; the first electrode is formed on the through channel, the first surface and the second surface and is contacted with the emitter layer; the second electrode is formed on the second surface and electrically connected with the semiconductor substrate; the dielectric layer is formed in the through channel and located between the emitter layer and the first electrode to isolate the first electrode from the pn junction, so that the conversion efficiency of the solar cell is increased.
Description
Technical field
The present invention relates to a kind of photovoltaic and beat assembly and manufacture method thereof, be specially a kind of solar cell and manufacture method thereof.
Background technology
The rise of global energy prices and the promotion of resource sustainable application, make green energy resource become an important ring of development in science and technology, wherein, the environmental limits of solar power generation is lower, is comparatively easy to universal.Transform light energy is electric energy by solar cell (Solar Cell) by solar power generation, therefore, promotes the conversion efficiency of solar cell, and then provides more and more cheap electric energy, for this reason the Main way that develops at present of industry.
Consult Fig. 1, it is the structural representation commonly using solar cell.The manufacturing process commonly using solar cell 1 is summarized as follows: first, semiconductor substrate 10 is provided, such as p-type semiconductor substrate, and surface coarsening (texturing) is carried out to the first surface S1 of semiconductor substrate 10, form rough surface, irradiate reflectivity in first surface S1 to reduce incident light.Then, the first surface S1 of semiconductor substrate 10 is adulterated (dopping) and spreads (diffusion) technique, to form emitter layer 11 in the first surface S1 of semiconductor substrate 10, wherein form pn junction (pnjunction) between semiconductor substrate 10 and emitter layer 11.In this step, also can form dielectric layer (not shown) in the outer surface of emitter layer 11, such as phosphorosilicate glass layer (Phosphorus Silicate Glass, PSG) or Pyrex layer according to the raw material used during doping simultaneously.Then, the mode of recycling etching (etching) removes dielectric layer.Afterwards; utilize the mode such as depositing (deposition); form anti-reflecting layer 12 (the Anti-Reflective Coating be made up of silicon nitride (SiNx); ARC) on the first surface S1 of semiconductor substrate 10 (namely on emitter layer 11), to reduce reflectivity and to protect emitter layer 11.
Then, on the first surface S1 utilizing such as screen painting (screen printing) mode electric conducting material to be formed at respectively semiconductor substrate 10 and second surface S2, and carry out co-sintering (cofiring) program, form in the first surface S1 of semiconductor substrate 10 the first electrode 13 contacted through anti-reflecting layer 12 and with emitter layer 11 thus, and on the second surface S2 of semiconductor substrate 10 formation second electrode 14.In addition, back surface electric field 15 (Back SurfaceField is also formed at the second surface S2 of semiconductor substrate 10, BSF), wherein the second electrode 14 contacts with the back surface electric field 15 of semiconductor substrate 10, to make the second electrode 14 be electrically connected at semiconductor substrate 10 through back surface electric field 15, thus complete the manufacture of solar cell 1.
But, first electrode 13 of the solar cell 1 commonly used is arranged on sensitive surface (i.e. first surface S1), the portion of the emitter layer 11 of solar cell 1 is covered by lighttight first electrode 13, and then reduce the area that emitter layer 11 reality can accept light, the conversion efficiency of solar cell is reduced.For solving foregoing problems, metal-through type solar cell (metal wrap through solar cell) (or claiming the back of the body to connect formula solar cell) is so developed.Metal-through type solar cell can form penetrating via in its semiconductor substrate, and electric conducting material is filled in penetrating via, using as sensitive surface to the electric current carrying pathway of shady face.Though the first electrode can be arranged at on the shady face of the second electrode same side by the metal-through type solar cell commonly used, with the area that the sensitive surface reducing solar cell is covered by metal electrode, the conversion efficiency of solar cell is improved, but the metal-through type solar cell commonly used easily causes the filling electrode of its penetrating via to burn emitter layer in sintering process, and contact with emitter layer and semiconductor substrate, cause problem such as electric leakage (leakage) or short circuit etc. simultaneouslyIn addition, the metal-through type solar cell commonly used also exists conversion efficiency and production reliability the problem such as effectively cannot to promote.
In view of this, how to develop a kind of solar cell and manufacture method thereof, to solve the problem of prior art, real is the current problem in the urgent need to address of correlative technology field person.
Summary of the invention
The object of the present invention is to provide a kind of solar cell and manufacture method thereof, it is by being formed at the shady face of solar cell by electrode, to increase sensitive surface actual area accepting light in unit are of solar cell, and then promote the conversion efficiency of solar cell.
Another object of the present invention is to provide a kind of solar cell and manufacture method thereof, the emitter layer surface of penetrating via is remained in by the dielectric layer of self-assembling formation in doping and diffusion process, make dielectric layer by the electrode in penetrating via and pn junction isolated, the protection of dielectric layer can be utilized thus to avoid the electrode in sintering process in penetrating via to burn emitter layer and to contact with semiconductor substrate and produce the problem of leaking electricity, and by the electrode in the completely isolated penetrating via of dielectric layer and pn junction, conduct in electrode with making current efficient in penetrating via, thus promote conversion efficiency and the reliability of solar cell.
For reaching above-mentioned purpose, a wider execution mode of the present invention is for providing a kind of solar cell, it comprises: semiconductor substrate, has first surface and the second surface relative with first surface, and semiconductor substrate has at least one penetrating via runs through first surface and second surface; Emitter layer, is formed at the first surface of semiconductor substrate, second surface and penetrating via, wherein forms a pn junction between semiconductor substrate and emitter layer; At least one first electrode, each this first electrode part is formed at penetrating via, part is formed at first surface, and part is formed at second surface, and contacts with emitter layer; At least one second electrode, is formed at second surface, and is electrically connected at semiconductor substrate, wherein forms open circuit between the first electrode and the second electrode; And dielectric layer, to be formed in penetrating via, and between emitter layer and the first electrode, with make the first electrode and pn junction isolated.
For reaching above-mentioned purpose, another wider execution mode of the present invention is for providing a kind of manufacture method of solar cell, it comprises step: (a) provides semiconductor substrate, semiconductor substrate has first surface, second surface and at least one penetrating via, wherein first surface is relative with second surface, and penetrating via is through the first surface of semiconductor substrate and second surface; B () forms emitter layer in the first surface of semiconductor substrate, second surface and penetrating via, and form dielectric layer in the outer surface of emitter layer, wherein forms pn junction between semiconductor substrate and emitter layer; C () forms packed layer in penetrating via, and remove and be positioned at the first surface of semiconductor substrate and the dielectric layer of second surface; D () removes packed layer, the dielectric layer being formed at penetrating via is exposed to the open air; And (e) forms at least one first electrode, wherein each this first electrode part is formed at penetrating via, and part is formed at first surface, and part is formed at second surface, and contacts with emitter layer; And form at least one second electrode in second surface, and be electrically connected at semiconductor substrate, wherein form open circuit between the first electrode and the second electrode.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing solar cell;
Fig. 2 is the structural representation of the solar cell of present pre-ferred embodiments;
Fig. 3 A to Fig. 3 H is the structure flow chart of the manufacture method of the solar cell of present pre-ferred embodiments.
1,2: solar cell
10,20: semiconductor substrate
11,21: emitter layer
12,23: anti-reflecting layer
13,24: the first electrodes
14,25: the second electrodes
15: back surface electric field
22: dielectric layer
26: local back surface field
201: penetrating via
202: packed layer
S1, S3: first surface
S2, S4: second surface.
Embodiment
Some exemplary embodiments embodying feature & benefits of the present invention describe in detail in the explanation of back segment.Be understood that the present invention can have various changes in different aspects, it neither departs from the scope of the present invention, and explanation wherein and accompanying drawing are in itself when the use explained, but not for limiting the present invention.
Refer to Fig. 2, it is the structural representation of the solar cell of present pre-ferred embodiments.Solar cell 2 of the present invention can be metal-through type solar cell, and comprises semiconductor substrate 20, emitter layer 21, dielectric layer 22, anti-reflecting layer 23, at least one first electrode 24 and at least one second electrode 25.Semiconductor substrate 20 has first surface S3, the second surface S4 relative with first surface S3 and at least one penetrating via 201, and wherein penetrating via 201 runs through first surface S3 and second surface S4.Emitter layer 21 is formed at first surface S3, second surface S4 and the penetrating via 201 of semiconductor substrate 20, wherein forms pn junction between semiconductor substrate 20 and emitter layer 21.First electrode 24 part is formed at penetrating via 201, part is positioned at first surface S3, and part is positioned at second surface S4.Second electrode 25 is formed at the second surface S4 of semiconductor substrate 20, wherein the first electrode 24 contacts with emitter layer 21, second electrode 25 is electrically connected at semiconductor substrate 20, and form open circuit between the first electrode 24 and the second electrode 25, to avoid being short-circuited between the first electrode 24 and the second electrode 25.Dielectric layer 22 is positioned at penetrating via 201, and is formed between emitter layer 21 and the first electrode 24, with make pn junction and the first electrode 24 isolated.
In the present embodiment, semiconductor substrate 20 can be p-type semiconductor or n-type semiconductor, and emitter layer 21 can conjunction with semiconductors substrate 20 semiconductor kenel and be n-type semiconductor or p-type semiconductor, to form pn junction.
In the present embodiment; dielectric layer 22 is an insulating barrier or protective layer; it has higher resistance; for the non-conductor of electricity; therefore; isolate by dielectric layer 22 between emitter layer 21 in penetrating via 201 and the first electrode 24, that is dielectric layer 22 can make the first electrode 24 completely isolated with pn junction, and photoinduction electric current can be made thus efficiently to change and conduct.
In some embodiments, solar cell 2 more comprises an anti-reflecting layer 23, and be positioned at the first surface S3 of semiconductor substrate 20, and be formed at the outer surface of emitter layer 21, wherein emitter layer 21 is formed between anti-reflecting layer 23 and semiconductor substrate 20.
Refer to Fig. 3 A to Fig. 3 H, wherein Fig. 3 A to Fig. 3 H is the structure flow chart of the manufacture method of the solar cell of present pre-ferred embodiments.The manufacture method of solar cell 2 of the present invention is summarized as follows: first, as shown in Figure 3A, semiconductor substrate 20 is provided, such as p-type semiconductor substrate or n-type semiconductor substrate, wherein semiconductor substrate 20 has first surface S3, second surface S4 and at least one penetrating via 201, wherein first surface S3 is relative with second surface S4, and penetrating via 201 runs through first surface S3 and the second surface S4 of semiconductor substrate 20.In the present embodiment, the mode of such as laser can be utilized to hole to semiconductor substrate 20, make semiconductor substrate 20 form multiple penetrating vias 201 of uniformly dispersing or array arrangement.Then, as shown in Figure 3 B, surface coarsening is carried out in the first surface S3 of semiconductor substrate 20 and second surface S4, to form the surface with Z-Correct bump mapping Z-correct, so as to reducing the reflectivity on surface and increasing the absorptivity of light.
Subsequently, as shown in Figure 3 C, form first surface S3, the second surface S4 of emitter layer 21 in semiconductor substrate 20 and the internal face of penetrating via 201, and form dielectric layer 22 in the outer surface of emitter layer 21, wherein form pn junction (not shown) between semiconductor substrate 20 and emitter layer 21, and emitter layer 21 is arranged between semiconductor substrate 20 and dielectric layer 22.
In the present embodiment, the step forming emitter layer 21 can utilize doping and diffusion technology to realize.In other words, can by dopant, such as phosphorus or boron, be implanted in semiconductor substrate 20, and drive in mode with thermal diffusion and make semiconductor substrate 20 form emitter layer 21, and the surface of emitter layer 21 also can be formed naturally dielectric medium 22 simultaneously, its dielectric layer 22 covers emitter layer 21 in first surface S3, second surface S4 and penetrating via 201, and according to different dopants, forms different dielectric mediums 22, such as phosphorosilicate glass or Pyrex, but not as limit.
Then, as shown in Figure 3 D, form packed layer 202 in penetrating via 201, and remove and be positioned at the first surface S3 of semiconductor substrate 20 and the dielectric layer 22 of second surface S4.Then, as shown in FIGURE 3 E, remove packed layer 202, the dielectric layer 22 being formed at penetrating via 201 is exposed to the open air.In the present embodiment, the step removing dielectric layer 22 realizes by etching mode.In other words; chemical etching liquor can be utilized to remove be positioned at the dielectric layer 22 of first surface S3 and second surface S4; now because the material of packed layer 202 is be not chemically etched liquid corrosion to carve the material removed; such as but not limited to high molecular polymer; therefore; the dielectric layer 22 be formed in penetrating via 201 can retain and do not removed by etching, make the emitter layer 21 in penetrating via 201 still be covered by dielectric layer 22 and protect.
Then, as illustrated in Figure 3 F, anti-reflecting layer 23 is formed in the first surface S3 of semiconductor substrate 20, to reduce reflectivity and to protect emitter layer 21.In an embodiment, anti-reflecting layer 23 can be nitrogen silicon compound (SiNx) or silica (SiO
2), and such as chemical vapour deposition technique can be utilized anti-reflecting layer 23 to be formed at the first surface S3 of semiconductor substrate 20, to cover the emitter layer 21 being positioned at first surface S3.
Then, as shown in Figure 3 G, the first electric conducting material is formed in penetrating via 201, on a part of region of first surface S3 and a part of region of second surface S4; And form the second electric conducting material on another part region of second surface S4, be wherein formed at the second electric conducting material on second surface S4 and the first electric conducting material be formed on second surface S4 is separated from each other and does not directly contact.In the present embodiment, the step forming the first electric conducting material and the second electric conducting material can utilize the such as mode such as screen painting (screen printing) or coating to realize.In some embodiments, the first electric conducting material can be but is not limited to elargol, and the second electric conducting material can be but be not limited to aluminium glue.In addition, the first electric conducting material and being formed in penetrating via 201 being formed at first surface S3 can the mode such as screen painting or coating carry out from first surface S3 and second surface S4 respectively with first electric conducting material of second surface S4, but not as limit.
Then, as shown in figure 3h, carry out sintering process altogether, at least one first electrode 24 and at least one second electrode 25 is formed respectively to make the first electric conducting material and the second electric conducting material, wherein each first electrode 24 part is formed in penetrating via 201, partly and is formed at first surface S3, and part is formed at second surface S4, and the first electrode 24 contacts with emitter layer 21; And each second electrode 25 is positioned at second surface S4, and be electrically connected at semiconductor substrate 20.Then, the mode of such as laser is utilized to make to form open circuit between the first electrode 24 and the second electrode 25, to avoid being short-circuited between the first electrode 24 and the second electrode 25.By abovementioned steps, the making of solar cell 2 of the present invention can be completed.
Referring again to Fig. 3 H, first electrode 24 of part is formed and is positioned at first surface S3 take framework as finger electrode, to be formed and be positioned at second surface S4 take framework as bus to first electrode 24 of part, and the first electrode 24 of part is formed at penetrating via 201 and isolated with the emitter layer 21 in penetrating via 201 by dielectric layer 22.In some embodiments, the first electrode 24 is contacted with emitter layer 21 by the part of its bus.In some embodiments, the second electric conducting material is formed on the subregion of second surface S4 of semiconductor substrate 20.In after co-sintering technique, the second surface S4 of semiconductor substrate 20 corresponds to this subregion of the second electric conducting material, aluminium-silicon melt will be formed and form heavy doping, the local back surface field 26 of such as P+, wherein this local back surface field 26 can reduce minority carrier in the probability of back side compound.In addition, after co-sintering technique, the second electrode 25 is worn and is burnt emitter layer 21, and contacts with semiconductor substrate 20 and local back surface field 26 thereof.In the present embodiment; by dielectric layer 22 being remained in penetrating via 201 and covering emitter layer 21; dielectric layer 22 is made to be arranged between the first electrode 24 and emitter layer 21; to protect the emitter layer 21 in penetrating via 201 can not be burnt by the first electrode 24 after co-sintering step, the first electrode 24 is contacted with semiconductor substrate 20; the first electrode 24 so can be avoided to contact with semiconductor substrate 20 and occur electronics electricity hole be combined and produce the problem of electric leakage again, to promote the conversion efficiency of solar cell 2.
In sum, solar cell of the present invention and manufacture method thereof, it is by being formed at the shady face of solar cell by electrode, to increase sensitive surface actual area accepting light in unit are of solar cell, and then promote the conversion efficiency of solar cell.In addition; the emitter layer surface of penetrating via is remained in by the dielectric layer of self-assembling formation in doping and diffusion process; make dielectric layer by the electrode in penetrating via and pn junction isolated; the protection of dielectric layer can be utilized thus to avoid the electrode in sintering process in penetrating via to burn emitter layer and to contact with semiconductor substrate and produce the problem of leaking electricity; and by the electrode in the completely isolated penetrating via of dielectric layer and pn junction; conduct in electrode with making current efficient in penetrating via, promote conversion efficiency and the reliability of solar cell.
The present invention must be thought by the personage Ren Shi craftsman haveing the knack of this technology and modify as all, so neither de-if attached claims institute is for Protector.
Claims (10)
1. a solar cell, comprising:
Semiconductor substrate, has a first surface and a second surface relative with described first surface, and described semiconductor substrate has at least one penetrating via runs through described first surface and described second surface;
One emitter layer, is formed at the described first surface of described semiconductor substrate, described second surface and described at least one penetrating via, forms a pn junction between wherein said semiconductor substrate and described emitter layer;
At least one first electrode, described in each, the first electrode part is formed at described penetrating via, part is formed at described first surface, and part is formed at described second surface, and contacts with described emitter layer;
At least one second electrode, is formed at described second surface, and is electrically connected at described semiconductor substrate, forms open circuit between wherein said first electrode and described second electrode; And
One dielectric layer, is formed in described at least one penetrating via, and between described emitter layer and described first electrode, with make described first electrode and described pn junction isolated.
2. solar cell according to claim 1, wherein, also comprises an anti-reflecting layer, is positioned at described first surface, and is formed at an outer surface of described emitter layer.
3. solar cell according to claim 1, wherein said dielectric layer is made up of phosphorosilicate glass or Pyrex.
4. solar cell according to claim 1, wherein said semiconductor substrate also comprises a local back surface field, is positioned at described second surface and corresponds to described second electrode.
5. a manufacture method for solar cell, comprises step:
A () provides semiconductor substrate, described semiconductor substrate has a first surface, a second surface and at least one penetrating via, wherein said first surface is relative with described second surface, and described at least one penetrating via is through the described first surface of described semiconductor substrate and described second surface;
B () forms an emitter layer in the described first surface of described semiconductor substrate, described second surface and described at least one penetrating via, and form a dielectric layer in an outer surface of described emitter layer, form a pn junction between wherein said semiconductor substrate and described emitter layer;
C () forms a packed layer in described at least one penetrating via, and remove and be positioned at the described first surface of described semiconductor substrate and the described dielectric layer of described second surface;
D () removes described packed layer, the described dielectric layer being formed at described penetrating via is exposed to the open air; And
E () forms at least one first electrode, wherein described in each, the first electrode part is formed at described penetrating via, and part is formed at described first surface, and part is formed at described second surface, and contacts with described emitter layer; And form at least one second electrode in described second surface, and be electrically connected at described semiconductor substrate, form open circuit between wherein said first electrode and described second electrode.
6. the manufacture method of solar cell according to claim 5, more comprises step after wherein said step (a): (a1) carries out a surface coarsening to the described first surface of described semiconductor substrate and described second surface.
7. the manufacture method of solar cell according to claim 5, wherein said step (b) realizes with a doping and diffusion technology, and described dielectric layer is made up of phosphorosilicate glass or Pyrex; And wherein in described step (c), described packed layer is a high molecular polymer.
8. the manufacture method of solar cell according to claim 5, also comprises step after wherein said step (d): (d1) forms an anti-reflecting layer in the described first surface of described semiconductor substrate.
9. the manufacture method of solar cell according to claim 5, wherein said step (e) comprises step:
(e1) one first electric conducting material is formed in described penetrating via, on a part of region of described first surface and a part of region of described second surface; And form one second electric conducting material on another part region of described second surface;
(e2) carry out sintering process altogether, form described at least one first electrode and described at least one second electrode respectively to make described first electric conducting material and described second electric conducting material; And
(e3) make to form open circuit between described first electrode and described second electrode in a laser mode.
10. the manufacture method of solar cell according to claim 9, wherein in described step (e2), also comprise step: form a local back surface field in described semiconductor substrate, wherein said local back surface field is positioned at described second surface and corresponds to described second electrode.
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