CN104576653B - Thin film transistor array substrate and method of manufacturing the same - Google Patents

Thin film transistor array substrate and method of manufacturing the same Download PDF

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Publication number
CN104576653B
CN104576653B CN201410543622.9A CN201410543622A CN104576653B CN 104576653 B CN104576653 B CN 104576653B CN 201410543622 A CN201410543622 A CN 201410543622A CN 104576653 B CN104576653 B CN 104576653B
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electrode
layer
gate electrode
thin film
film transistor
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CN104576653A (en
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李旺宇
高武恂
金度衡
禹珉宇
李一正
李正浩
朴永佑
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Samsung Display Co Ltd
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Samsung Display Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors

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  • Thin Film Transistor (AREA)
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Abstract

The application discloses a thin film transistor array substrate and a method of manufacturing the same. The thin film transistor array substrate includes: a first thin film transistor including a first active layer, a gate electrode, a first source electrode, and a first drain electrode; a second thin film transistor including a second active layer, a floating gate electrode, a control gate electrode, a second source electrode, and a second drain electrode; a capacitor including a first electrode and a second electrode; and a capping layer contacting a portion of the first electrode, the capping layer and the second electrode being on the same layer.

Description

Thin film transistor array substrate and method of manufacturing the same
Technical Field
One or more aspects of embodiments of the present disclosure relate to a thin film transistor array substrate and a method of manufacturing the same.
Background
A display device is a device for displaying an image. Recently, organic light emitting display devices have attracted attention.
The organic light emitting display device has a self-light emitting characteristic without a separate light source, unlike a liquid crystal display device requiring a separate light source. Accordingly, the thickness and weight of the organic light emitting display device may be reduced as compared to the liquid crystal display device. In addition, the organic light emitting display device exhibits high definition characteristics such as low power consumption, high luminance, and high reaction speed.
Disclosure of Invention
One or more aspects of embodiments of the present disclosure are directed to a thin film transistor array substrate on which a high-resolution display device may be implemented.
Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present embodiments.
According to one or more embodiments of the present disclosure, a Thin Film Transistor (TFT) array substrate includes: a first thin film transistor including a first active layer, a gate electrode, a first source electrode, and a first drain electrode; a second thin film transistor including a second active layer, a floating gate electrode, a control gate electrode, a second source electrode, and a second drain electrode; a capacitor including a first electrode and a top electrode; and a capping layer contacting a portion of the first electrode, the capping layer and the top electrode being on the same layer.
The TFT array substrate may further include: a first insulating layer between the first active layer and the gate electrode and between the second active layer and the floating gate electrode; and a second insulating layer between the floating gate electrode and the control gate electrode.
The first electrode and the gate electrode of the capacitor may be on the same layer, and the top electrode and the control gate electrode of the capacitor may be on the same layer.
The first electrode may comprise a low resistivity material.
The low resistivity material may include an aluminum alloy.
The cap layer may comprise molybdenum.
The second insulating layer may be between the first electrode and the second electrode of the capacitor, and the cap layer may be electrically connected to the first electrode through a contact hole in the second insulating layer.
The first insulating layer and the second insulating layer may each include an inorganic insulating material, an organic insulating material, or a structure in which an inorganic insulating material and an organic insulating material are alternated.
The high dielectric constant material may be included in at least a portion between the first electrode and the second electrode of the capacitor.
The TFT array substrate may further include a connection interconnection layer electrically connected to the cap layer through the contact hole.
According to one or more embodiments of the present disclosure, a method of manufacturing a TFT array substrate includes: forming a first active layer of the first TFT and a second active layer of the second TFT; forming a gate electrode over the first active layer, a floating gate electrode over the second active layer, and a first electrode of the capacitor; and forming a control gate electrode over the floating gate electrode, a top electrode over the first electrode, and a capping layer contacting a portion of the first electrode.
The manufacturing method may further include: forming a first insulating layer between the first active layer and the gate electrode and between the second active layer and the floating gate electrode; and forming a second insulating layer between the floating gate electrode and the control gate electrode.
The manufacturing method may further include: the first active layer and the second active layer are doped and heat-treated between the formation of the gate electrode and the floating gate electrode and the formation of the control gate electrode.
The first electrode may include a low resistivity material, and the low resistivity material may include an aluminum alloy.
The cap layer may comprise molybdenum.
Forming the second insulating layer may include forming the second insulating layer between a bottom electrode and a top electrode of the capacitor, and forming the capping layer may include: forming a first contact hole exposing a portion of the first electrode in the second insulating layer; and forming a capping layer electrically connected to the first electrode through a first contact hole formed in the second insulating layer.
The manufacturing method may further include: forming a third insulating layer on the cap layer; forming a second contact hole exposing a portion of the cap layer in the third insulating layer; and forming a connection line electrically connected to the cap layer through the second contact hole.
Forming the second contact hole may include: coating a photoresist material on the third insulating layer; dry etching the photoresist material to form a second contact hole; and cleaning the second contact hole.
Simultaneously with or after forming the first contact hole exposing a portion of the first electrode, the method may further include: forming an opening in the second insulating layer to expose another portion of the first electrode; and forming a high dielectric constant material layer in the opening before forming the cover layer.
Drawings
These and/or other aspects will become apparent and more readily appreciated from reference to the following description, taken in conjunction with the accompanying drawings, in which:
fig. 1 is an equivalent circuit diagram of a pixel of a display device according to an embodiment of the present disclosure;
fig. 2 is a schematic plan view illustrating the pixel of fig. 1 according to an embodiment of the present disclosure;
fig. 3 is a schematic cross-sectional view of the thin film transistor array substrate of fig. 2 taken along lines a-a 'and B-B';
fig. 4 is a flowchart schematically illustrating a manufacturing process of a thin film transistor array substrate according to an embodiment of the present disclosure;
fig. 5 to 9 are sectional views schematically illustrating a process of manufacturing the thin film transistor array substrate shown in fig. 2;
fig. 10 is a graph showing a change in sheet resistance value according to doping and heat treatment; and
fig. 11 is a cross-sectional view schematically illustrating a thin film transistor array substrate according to another embodiment of the present disclosure.
Detailed Description
Reference will now be made to certain embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout, and some duplicative explanation is not provided. As will be recognized by those skilled in the art, the described embodiments may be modified in numerous ways and may have different forms, and should not be construed as limiting. Accordingly, the embodiments are described below by referring to the drawings only for explaining aspects of the present description.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.
It will be understood that when a layer, region or component is referred to as being "on" or "formed on" another layer, region or component, it can be directly on the other layer, region or component, or be indirectly on the other layer, region or component or be indirectly formed on the other layer, region or component with one or more intervening elements interposed therebetween. For example, intervening layers, regions, or components may be present.
The size of elements in the drawings may be exaggerated for convenience of explanation. In other words, since the sizes and thicknesses of components in the drawings may be arbitrarily illustrated for convenience of explanation, the following embodiments are not limited thereto.
While certain embodiments may be practiced differently, the specific process sequence may be performed differently than that described. For example, two processes described in succession may be executed concurrently (or substantially concurrently), or in reverse order to that described.
As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. When a statement such as "at least one of" precedes a list of elements, the entire list of elements is modified without modifying each element in the list. Furthermore, the use of "may" when describing an embodiment of the disclosure refers to one or more embodiments of the disclosure.
Fig. 1 is an equivalent circuit diagram of a pixel of a display device according to an embodiment of the present disclosure.
The pixel 1 of the display device according to the embodiment of the present disclosure includes a pixel circuit 2, and the pixel circuit 2 includes a plurality of Thin Film Transistors (TFTs) T1 to T6 and a storage capacitor Cst. The pixel 1 further includes an Organic Light Emitting Diode (OLED) that receives a driving current through the pixel circuit 2 and emits light.
The plurality of TFTs T1 to T6 are first to sixth TFTs.
The pixel 1 includes a first scan line SLn transmitting a first scan signal Sn to the second TFT T2 and the third TFT T3, and a second scan line SLn-1 transmitting a second scan signal Sn-1, which is a previous scan signal, to the fourth TFT T4. The pixel 1 further includes an emission control line EMLn that transmits an emission control signal EMn to the fifth and sixth TFTs T5 and T6 and a data line DLm that crosses the first scan line SLn and transmits a data signal Dm. The pixel 1 further includes a driving voltage line PL formed almost in parallel (or substantially in parallel) with the data line DLm and delivering the first power supply voltage ELVDD and an initialization voltage line VL delivering an initialization voltage VINT for initializing the first tft t 1.
The gate electrode G1 of the first TFT T1 is connected to the first electrode Cst1 of the capacitor Cst. The source electrode S1 of the first TFT T1 is connected to the driving voltage line PL via the fifth TFT T5. The drain electrode D1 of the first TFT T1 is electrically connected to the anode electrode of the OLED via the sixth TFT T6. The first TFT T1 receives the data signal Dm according to the switching operation of the second TFT T2 to supply the driving current Ioled to the OLED.
The gate electrode G2 of the second TFT T2 is connected to the first scan line SLn. The source electrode S2 of the second TFT T2 is connected to the data line DLm. The drain electrode D2 of the second TFT T2 is connected to the source electrode S1 of the first TFT T1 and to the driving voltage line PL via the fifth TFT T5. The second TFT T2 is turned on according to the first scan signal Sn received through the first scan line SLn, and performs a switching operation of transferring the data signal Dm received through the data line DLm to the source electrode S1 of the first TFT T1.
The gate electrode G3 of the third TFT T3 is connected to the first scan line SLn. The source electrode S3 of the third TFT T3 is connected to the drain electrode D1 of the first TFT T1 and to the anode electrode of the OLED via the sixth TFT T6. The drain electrode D3 of the third TFT T3 is connected together with the first electrode Cst1 of the capacitor Cst, the drain electrode D4 of the fourth TFT T4, and the gate electrode G1 of the first TFT T1. The third TFT T3 is turned on according to the first scan signal Sn received through the first scan line SLn, thereby diode-connecting (diode-connecting) the first TFT T1 by connecting the gate electrode G1 and the drain electrode D1 of the first TFT T1 through the third TFT T3.
The gate electrode G4 of the fourth TFT T4 is connected to the second scan line SLn-1. The source electrode S4 of the fourth TFT T4 is connected to the initialization voltage line VL. The drain electrode D4 of the fourth TFT T4 is connected together with the first electrode Cst1 of the capacitor Cst, the drain electrode D3 of the third TFT T3, and the gate electrode G1 of the first TFT T1. The fourth TFT T4 is turned on according to the second scan signal Sn-1 received through the second scan line SLn-1, and when turned on, initializes the voltage of the gate electrode G1 of the first TFT T1 by transferring an initialization voltage VINT to the gate electrode G1 of the first TFT T1.
The gate electrode G5 of the fifth TFT T5 is connected to the emission control line EMLn. The source electrode S5 of the fifth TFT T5 is connected to the driving voltage line PL. The drain electrode D5 of the fifth TFT T5 is connected to the source electrode S1 of the first TFT T1 and the drain electrode D2 of the second TFT T2.
The gate electrode G6 of the sixth TFT T6 is connected to the emission control line EMLn. The source electrode S6 of the sixth TFT T6 is connected to the drain electrode D1 of the first TFT T1 and the source electrode S3 of the third TFT T3. The drain electrode D6 of the sixth TFT T6 is electrically connected to the anode electrode of the OLED. The fifth TFT T5 and the sixth TFT T6 are simultaneously (or together) turned on according to the emission control signal EMn received through the emission control line EMLn, and transfer the first power supply voltage ELVDD to the OLED when turned on. Then, the driving current Ioled flows to the OLED.
The second electrode Cst2 of the capacitor Cst is connected to the driving voltage line PL. The first electrode Cst1 is connected with the gate electrode G1 of the first TFT T1, the drain electrode D3 of the third TFT T3, and the drain electrode D4 of the fourth TFT T4.
The cathode electrode of the OLED is connected to a second power supply voltage ELVSS. The OLED displays an image by receiving a driving current Ioled from the first TFT T1 and emitting light.
Fig. 2 is a schematic plan view illustrating the pixel of fig. 1 according to an embodiment of the present disclosure.
As shown in fig. 2, the pixel 1 of the display device according to the embodiment of the present disclosure includes a first scan line SLn, a second scan line SLn-1, an emission control line EMLn, and an initialization voltage line VL that extend in a horizontal direction and apply (e.g., supply) a first scan signal Sn, a second scan signal Sn-1, an emission control signal EMn, and an initialization voltage VINT to the pixel 1, respectively. In fig. 2, the pixel 1 further includes a data line DLm and a driving voltage line PL crossing each of the first scan line SLn, the second scan line SLn-1, the emission control line EMLn, and the initialization voltage line VL. The data line DLm and the driving voltage line PL apply (e.g., supply) the data signal Dm and the first power supply voltage ELVDD to the pixel 1, respectively.
In this embodiment, the first scan line SLn, the second scan line SLn-1, the emission control line EMLn, the first electrode Cst1 of the capacitor Cst, and the floating gate electrode (e.g., the second gate electrode) of the first TFT T1 are formed of the same (or substantially the same) first conductive material on the same layer. The second electrode Cst2 of the capacitor Cst, the gate electrode G1 (e.g., the first gate electrode) of the first TFT T1, and the cap layer of the capacitor Cst are formed of the same (or substantially the same) second conductive material on the same layer.
The wiring formed of the first conductive material and the wiring formed of the second conductive material are located on different layers (for example, distinct layers) with the insulating layer therebetween. The distance between adjacent wirings located on different layers may be narrower than the distance between other adjacent wirings located on the same layer. Therefore, a large number of pixels can be formed over the same area as compared with other wirings. For example, a high-resolution display device may be formed using (with) the embodiments of the present disclosure.
The pixel 1 according to the embodiment of the present disclosure has the first to sixth TFTs T1 to T6 and the capacitor Cst formed therein. The OLED may be at a region corresponding to the VIA.
As shown in fig. 2, the first TFT T1 includes a first gate electrode G11 (which is a control electrode), a second gate electrode G12 (which is a floating electrode), a source electrode S1, and a drain electrode D1. The source electrode S1 corresponds to a source region in which impurities are doped into the semiconductor layer, and the drain electrode D1 corresponds to a drain region in which impurities are doped into the semiconductor layer. The first gate electrode G11 is connected to the first electrode Cst1 of the capacitor Cst, the drain electrode D3 of the third TFT T3, and the drain electrode D4 of the fourth TFT T4 through the connection member 40 via the contact holes 41 to 44.
The second TFT T2 includes a gate electrode G2, a source electrode S2, and a drain electrode D2. The source electrode S2 corresponds to a source region in which impurities are doped into the semiconductor layer, and the drain electrode D2 corresponds to a drain region in which impurities are doped into the semiconductor layer. The source electrode S2 is connected to the data line DLm through the contact hole 46. The drain electrode D2 is connected to the source electrode S1 of the first TFT T1 and the drain electrode D5 of the fifth TFT T5. The gate electrode G2 is formed of a portion of the first scan line SLn (or corresponds to a portion of the first scan line SLn).
The third TFT T3 includes a gate electrode G3, a source electrode S3, and a drain electrode D3. The source electrode S3 corresponds to a source region in which impurities are doped into the semiconductor layer, and the drain electrode D3 corresponds to a drain region in which impurities are doped into the semiconductor layer. The gate electrode G3 is formed of a portion of the first scan line SLn (or corresponds to a portion of the first scan line SLn).
The fourth TFT T4 includes a gate electrode G4, a source electrode S4, and a drain electrode D4. The source electrode S4 corresponds to a source region in which impurities are doped into the semiconductor layer, and the drain electrode D4 corresponds to a drain region in which impurities are doped into the semiconductor layer. The source electrode S4 may be connected to the initialization voltage line VL through a contact hole 45 (on the left in fig. 2). The gate electrode G4 is formed of (or corresponds to) a portion of the second scan line SLn-1 as a dual gate electrode and prevents (or reduces) leakage current.
The fifth TFT T5 includes a gate electrode G5, a source electrode S5, and a drain electrode D5. The source electrode S5 corresponds to a source region in which impurities are doped into the semiconductor layer, and the drain electrode D5 corresponds to a drain region in which impurities are doped into the semiconductor layer. The source electrode S5 may be connected to the driving voltage line PL through a contact hole 47. The gate electrode G5 is formed of a part of the emission control line EMLn.
The sixth TFT T6 includes a gate electrode G6, a source electrode S6, and a drain electrode D6. The source electrode S6 corresponds to a source region in which impurities are doped into the semiconductor layer, and the drain electrode D6 corresponds to a drain region in which impurities are doped into the semiconductor layer. The drain electrode D6 is connected to the anode electrode of the OLED through a VIA hole VIA connected to the contact hole 48. The gate electrode G6 is formed of a part of (or corresponds to a part of) the emission control line EMLn.
The first electrode Cst1 of the capacitor Cst is connected to the cap layer 53 on the top surface thereof, and the cap layer 53 is connected together with the drain electrode D3 of the third TFT T3, the drain electrode D4 of the fourth TFT T4, and the first gate electrode G11 of the first TFT T1 through the connection member 40 via the contact hole 43. The connection member 40 is on (e.g., formed on) the same layer as the data line DLm.
The second electrode Cst2 of the capacitor Cst is connected to the driving voltage line PL through the contact hole 49 and receives the first power supply voltage ELVDD from the driving voltage line PL.
Fig. 3 is a schematic cross-sectional view of the TFT array substrate of fig. 2 taken along lines a-a 'and B-B'.
The TFT array substrate includes a plurality of scan lines SLn and SLn-1 and a plurality of data lines DLm in a plurality of pixels 1. An array of the TFT, the light emitting device, and the capacitor included in each of the plurality of pixels 1 is referred to as a TFT array.
The TFT array substrate 100 may include first to sixth TFTs T1 to T6 and a capacitor Cst. Hereinafter, the first TFT T1 is denoted as (or referred to as) a driving TFT DT, and the second to sixth TFTs T2 to T6 are denoted as (or referred to as) a switching TFT st. For convenience, fig. 3 illustrates the driving TFT DT corresponding to the first TFT T1, the switching TFT ST corresponding to the third TFT T3 among the second to sixth TFTs T2 to 6, and the capacitor Cst.
The driving TFT DT may include: an active layer 31 which is a semiconductor layer; a floating gate electrode 33 corresponding to the second gate electrode G12 of the first TFT T1; a control gate electrode 35 corresponding to the first gate electrode G11; and source/drain electrodes 31S/31D corresponding to the source/drain electrodes S1/D1. The first insulating layer GI1 may be between the active layer 31 of the driving TFT DT and the floating gate electrode 33, and the second insulating layer GI2 may be between the floating gate electrode 33 and the control gate electrode 35. Source/drain regions into which impurities are doped are located (e.g., formed) on both edges of the active layer 31 and serve as source/drain electrodes 31s/31 d. The floating gate electrode 33 may include (e.g., be formed of) a single layer or multiple layers including a low-resistance material (e.g., a low-resistivity material). The control gate electrode 35 is formed of a material different from that of the floating gate electrode 33, and may include (e.g., be formed of) a single layer or a plurality of layers including a material having excellent heat resistance or chemical resistance.
The switching TFT ST may include: an active layer 11 which is a semiconductor layer; a gate electrode 13 corresponding to the gate electrode G3 of the third TFT T3; and source/drain electrodes 11S/11D corresponding to the source/drain electrodes S3/D3. The first insulating layer GI1 may be between the active layer 11 and the gate electrode 13 of the switching tft st. The source/drain regions into which impurities are doped are located (e.g., formed) on both edges of the active layer 11 and serve as source/drain electrodes 11s/11 d. The gate electrode 13 may include (e.g., be formed of) a single layer containing a low-resistance material (e.g., a low-resistivity material) or a multilayer containing a low-resistance material (e.g., a low-resistivity material).
The capacitor Cst includes a first electrode (e.g., a bottom electrode) 51 and a second electrode (e.g., a top electrode) 55 (e.g., formed of the first electrode 51 and the second electrode 55) corresponding to the first electrode Cst1 and the second electrode Cst2, respectively, and includes a second insulating layer GI2 between the first electrode 51 and the second electrode 55. The bottom electrode 51 may be located (e.g., formed) on the same layer as the gate electrode 13 of the switching TFT ST and the floating gate electrode 33 of the driving TFT DT. The bottom electrode 51 may include (e.g., be formed of) a single layer or multiple layers including (e.g., of) a low-resistance material (e.g., a low-resistivity material). The top electrode 55 may be (e.g., formed on) the same layer as the control gate electrode 35 of the driving TFT DT. The top electrode 55 may be formed of a material different from that of the bottom electrode 51, and may include (e.g., be formed of) a single layer or a plurality of layers including a material having excellent heat resistance or chemical resistance. A portion of the bottom electrode 51 may contact the cap layer 53 to be electrically connected to the cap layer 53. The capping layer 53 may be formed of the same (or substantially the same) material and on the same layer as the top electrode 55. The cap layer 53 may be connected to the connection member (wiring) 40 through the contact hole 43, and the connection member (wiring) 40 may be on (e.g., formed on) the third insulating layer 102. Accordingly, the bottom electrode 51 may be electrically connected to the drain electrode 11d of the switching TFT ST through the contact hole 42 via the connection member 40. Further, the bottom electrode 51 is electrically connected to the control gate electrode 35 of the driving TFT DT through the connection member 40 and the contact hole 41. In addition, the capacitor Cst may include a high dielectric constant (high K) material between the bottom electrode 51 and the top electrode 55 instead of the second insulating layer GI 2.
The fourth insulating layer 103 and the fifth insulating layer 104 may be on (e.g., formed on) the driving TFT DT, the switching TFT ST, and the capacitor Cst. The driving voltage line PL electrically connected to the top electrode 55 of the capacitor Cst through the contact hole 49 may be between the fourth insulating layer 103 and the fifth insulating layer 104.
The OLED may be located on the fifth insulating layer 104 in the region of (or formed on) the VIA, as shown in fig. 2. The OLED includes a pixel electrode (anode electrode), an opposite electrode (cathode electrode) facing the pixel electrode, and an intermediate layer therebetween. The pixel electrode may be connected to one of the first to sixth TFTs T1 to T6. The intermediate layer includes an organic emission layer. As a non-limiting example, the intermediate layer includes an organic emission layer, and may further include at least one of a hole injection layer HIL, a hole transport layer HTL, an electron transport layer ETL, and an electron injection layer EIL. However, the present disclosure is not limited thereto, and the intermediate layer may include an organic emission layer and also include other various functional layers. The opposite electrode may be on (e.g., formed on) the entire surface of the TFT array substrate 100 to serve as a common electrode.
Further, the source and drain electrodes of each of the first to sixth TFTs T1 to T6 according to the embodiment of the present disclosure are source and drain regions into which impurities are doped, but the source and drain electrodes are not limited thereto. The source and drain electrodes of each of the first to sixth TFTs T1 to T6 according to another embodiment of the present disclosure may be connected to source and drain regions on a layer different from the active layer (or connected to source and drain regions of a layer different from the active layer).
Fig. 4 is a flowchart schematically illustrating a manufacturing process of a TFT array substrate according to an embodiment of the present disclosure. Fig. 5 to 9 are sectional views schematically illustrating a process of manufacturing the TFT array substrate of fig. 3. Hereinafter, a manufacturing process of the TFT array substrate shown in fig. 5 to 9 is schematically described.
Referring to fig. 4 and 5, the active layer 11 of the switching TFT ST and the active layer 31 of the driving TFT DT are formed on a TFT array substrate (hereinafter, referred to as an "array substrate") 100 (operation S201).
The array substrate 100 may be formed of SiO2A glass material containing the transparent material of (2) as a main component. However, the array substrate 100 is not limited thereto, and substrates of various materials, such as transparent plastic or metal, may be used (utilized).
An auxiliary layer 101 (also shown in fig. 5) such as a barrier layer, a blocking layer, and/or a buffer layer may be formed on the array substrate 100, the auxiliary layer 101 preventing impurity ionsDiffuse (or reduce such diffusion), prevent moisture or air penetration (or reduce such penetration), and make the surface thereof flat. The auxiliary layer 101 may be formed by using (utilizing) SiO2And/or SiNx, by various suitable deposition methods. The auxiliary layer 101 may be omitted.
The active layer 11 of the switching TFT ST and the active layer 31 of the driving TFT DT are formed on the auxiliary layer 101. The active layers 11 and 31 may be formed by patterning the amorphous silicon layer. The active layers 11 and 31 may include a semiconductor or an oxide semiconductor.
The first insulating layer GI1 is formed on the array substrate 100 on which the active layers 11 and 31 are formed. The first insulating layer GI1 may include (e.g., be formed from) SiO2、SiNx、Al2O3、CuOx、Tb4O7、Y2O3、Nb2O5And Pr2O3An inorganic insulating material selected among them, or at least one organic insulating material selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin, or a multilayer structure in which the organic insulating material and the inorganic insulating material are alternated.
Then, referring to fig. 4 and 6, the first conductive wiring is formed on the first insulating layer GI1 (operation S202).
The first conductive wiring may include the gate electrode 13 of the switching TFT ST, the floating gate electrode 33 of the driving TFT DT, and the bottom electrode 51 of the capacitor Cst. The first conductive wiring may include (e.g., be formed of) a single layer containing a low-resistance metal material (e.g., a low-resistivity material) such as aluminum (Al), an aluminum alloy (Al alloy), or copper (Cu), or a structure having a multilayer containing one or more metals selected from among platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), and tungsten (W). For example, the first conductive wiring may include (e.g., be formed of) a single layer of aluminum alloy or a multilayer structure of aluminum alloy/TiN or TiN/aluminum alloy/TiN.
In realizing a high-resolution display such as a display capable of full high definition or ultra high definition, low-impedance wiring is suitable for reducing scan delay.
When the first conductive wiring includes (or is formed of) an aluminum alloy having high heat resistance such as AlNd (e.g., an aluminum neodymium alloy), problems such as protrusion (or growth that may cause short circuits between layers) are prevented from occurring (or reduced from occurring) in (or during) a heat treatment suitable for a Low Temperature Polysilicon (LTPS) process.
After the first conductive wiring is formed, the active layers 11 and 31 are doped and heat-treated (operation S203).
In the embodiment of the present disclosure, the gate electrode 13 of the switching TFT ST and the floating gate electrode 33 of the driving TFT DT are formed together (e.g., together or simultaneously), and then the active layers 11 and 31 are doped and heat-treated.
Doping and heat treatment of the active layers 11 and 31 after forming the cap layer 53 and the control gate electrode 35 of the driving TFT DT, which will be described later, cause discoloration (discolouration) and an increase in resistivity between the bottom electrode 51 and the cap layer 53 of the capacitor Cst. In the embodiment of the present disclosure, the doping and the heat treatment are performed on the active layers 11 and 31 before the cap layer 53 and the control gate electrode 35 of the driving TFT DT are formed, and thus the occurrence of such a situation can be reduced.
On the other hand, the driving TFT DT includes a floating gate electrode 33 as (e.g., formed as) a nonvolatile memory device. Accordingly, the driving TFT DT stores (e.g., can store) a compensation value for the threshold voltage in the floating gate electrode 33 to compensate for the threshold voltage of the driving TFT DT.
n-type or p-type impurities are doped into the active layers 11 and 31 by using the gate electrode 13 of the switching TFT ST and the floating gate electrode 33 of the driving TFT DT, respectively, as self-aligned masks. Accordingly, source/drain regions 11s/11d are formed at edges of the active layer 11 corresponding to both sides (e.g., both sides) of the gate electrode 13 of the switching TFT ST, and a channel region 11c (also shown in fig. 3) is formed between the source/drain regions 11s/11 d. The source/drain regions 11s/11d function as source/drain electrodes. In addition, source/drain regions 31s/31d are formed at edges of the active layer 31 corresponding to both sides (e.g., both sides) of the floating gate electrode 33 of the driving TFT DT, and a channel region 31c (also shown in fig. 3) is formed between the source/drain regions 31s/31 d. The source/drain regions 11s/11d and 31s/31d may function as source/drain electrodes.
The active layers 11 and 31 may be formed as p-type layers when a group III element (e.g., a group III element) such as boron (B) is doped in the active layers 11 and 31, and the active layers 11 and 31 may be formed as N-type layers when a group V element (e.g., a group V element) such as nitrogen (N) is doped in the active layers 11 and 31. In some embodiments, an n-type or p-type impurity is injected into the bottom electrode 51 of the capacitor Cst by one time doping, and the bottom electrode 51 of the capacitor Cst and the active layers 11 and 31 may be doped simultaneously (or together).
After the active layers 11 and 31 are doped, the amorphous silicon layers of the active layers 11 and 31 are crystallized into crystalline silicon layers by heat-treating the active layers 11 and 31. The crystallization of the active layers 11 and 31 is performed by a heat treatment at a temperature of about 580 deg.c or higher through various methods, such as a Rapid Thermal Annealing (RTA) method, a Solid Phase Crystallization (SPC) method, an Excimer Laser Annealing (ELA) method, a Metal Induced Crystallization (MIC) method, a Metal Induced Lateral Crystallization (MILC) method, a Sequential Lateral Solidification (SLS) method, and/or an Advanced Sequential Lateral Solidification (ASLS) method, but the present disclosure is not limited thereto.
The bottom electrode 51 of the capacitor Cst may be sequentially electrically connected to the drain electrode of the switching TFT ST and the gate electrode of the driving TFT DT. For this, a contact hole is formed to expose a portion of the bottom electrode 51 of the capacitor Cst.
However, because the aluminum alloy has no (or substantially no or little) acid resistance to hydrofluoric acid or Buffered Oxide Etchant (BOE) used alone or in combination in cleaning, the aluminum alloy can be damaged or etched (or completely etched) by the cleaning process. Therefore, in the embodiment of the present disclosure, the cap layer is formed to protect the aluminum alloy, as described later.
Fig. 10 is a graph showing a change in sheet resistance value according to doping and heat treatment.
The left side of fig. 10 is a graph showing a change in sheet resistance according to doping and heat treatment of a single film (e.g., a single layer) of an aluminum alloy. The right side of fig. 10 is a graph showing a change in sheet resistance according to doping and heat treatment of an aluminum alloy/molybdenum double film (e.g., a film including two layers) having molybdenum as a cap layer.
Referring to the left graph of fig. 10, after amorphous silicon deposition (AS-Depo) and doping are performed, AS the heat treatment temperature increases, the sheet resistance (Rs) of the aluminum alloy single film becomes lower. On the other hand, referring to the right graph of fig. 10, after the AS-Depo and doping are performed, when the temperature is increased to 480 ℃, the sheet resistance (Rs) of the aluminum alloy/molybdenum double film becomes reduced. Also, as the temperature is further increased, the sheet resistance becomes higher, resulting in discoloration and an increase in sheet resistance due to the reaction of the aluminum alloy with molybdenum at the heat treatment temperature of 580 ℃.
Therefore, in the embodiment of the present disclosure, the single film (e.g., the aluminum alloy single film) of the first conductive wiring is subjected to heat treatment before the cap layer is formed.
Then, a second insulating layer GI2 is formed on the array substrate 100. The second insulating layer GI2 may include (e.g., be formed from) SiO2、SiNx、Al2O3、CuOx、Tb4O7、Y2O3、Nb2O5And Pr2O3An inorganic insulating material selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin, or a multilayer structure in which the organic insulating material and the inorganic insulating material are alternated.
Then, referring to fig. 4 and 7, a contact hole H1 is formed in the second insulating layer GI2, exposing a portion of the bottom electrode 51 of the capacitor Cst (operation S204).
After a photoresist material is uniformly coated on the entire second insulating layer GI2, the contact hole H1 is formed through a mask process of exposure through a mask (e.g., mask exposure) and development, etching, and stripping or ashing, but the present disclosure is not limited thereto. For example, the etching may be dry etching, but the present disclosure is not limited thereto.
Then, referring to fig. 4 and 8, a second conductive wiring is formed on the second insulating layer GI2 (operation S205).
The second conductive wiring may include the control gate electrode 35 of the driving TFT DT, the capping layer 53, and the top electrode 55 of the capacitor Cst. The second conductive wiring may be formed to have a single-layer or multi-layer structure including one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). For example, the second conductive wiring may be formed to include a single-layer structure including molybdenum or a multi-layer structure including aluminum alloy/molybdenum (e.g., an aluminum alloy layer and a molybdenum layer) or molybdenum/aluminum alloy/molybdenum (e.g., a first molybdenum layer, an aluminum alloy layer, and a second molybdenum layer).
In the embodiment of the present disclosure, in the driving TFT DT, the insulating layer between the active layer 31 and the control gate electrode 35 is formed thicker than the insulating layer between the active layer 11 and the gate electrode 13. For example, in the driving TFT DT, the first insulating layer GI1 is between the active layer 31 and the floating gate electrode 33, and the second insulating layer GI2 is between the floating gate electrode 33 and the control gate electrode 35. In the switching TFT ST, only the first insulating layer GI1 is between the active layer 11 and the gate electrode 13.
When the driving TFT DT includes a thick gate insulating layer and light emitted from the light emitting device is represented as black and white according to a driving current flowing through the light emitting device, a driving range of the gate voltage Vgs applied to the gate electrode of the driving TFT DT is widened. For example, when the driving range of the driving TFT DT is wide, light emitted from the light emitting device may be controlled to have rich gray scales (gradation) by varying (e.g., changing) the magnitude of the gate voltage Vgs applied to the gate electrode of the driving TFT DT.
As Pixels Per Inch (PPI) of the display apparatus increases and a high resolution display apparatus is realized, it is advantageous for the high driving range to have a rich gray scale for light emitted from the light emitting device.
Accordingly, in the embodiment of the present disclosure, since the first and second insulating layers GI1 and GI2 are between the active layer 31 and the control gate electrode 35 of the driving tft dt to form a thick insulating layer, the light emitting device is controlled to emit light having a rich gray scale. For example, according to an embodiment of the present disclosure, a display device is provided to have high resolution and improved display quality.
The capping layer 53 fills the contact hole H1 and contacts the bottom electrode 51 of the capacitor Cst to be electrically connected to the bottom electrode 51, and is formed on the same layer as the top electrode 55 of the capacitor Cst. The capping layer 53 protects the bottom electrode 51 of the capacitor Cst, including (e.g., formed of) the low-impedance wiring, from dry etching and cleaning.
Since the cap layer 53 is damaged by dry etching when the contact hole is subsequently formed, a metal having an appropriate selection ratio is suitable for the cap layer 53. As an example, molybdenum having excellent heat resistance and chemical resistance may be used (applied) to the cap layer 53.
The capacitor Cst includes a bottom electrode 51 formed of a first conductive wiring and a top electrode 55 formed of a second conductive wiring. Accordingly, because the capacitor Cst does not need to have polysilicon with a non-uniform (e.g., non-flat) surface profile, the storage capacity is not undesirably changed with an undesirable change in the surface area of the electrode. For example, the capacitor Cst can store an initially designed (or set) accurate storage capacity, and thus prevent (or reduce) deterioration of display quality by accurately controlling the driving current controlled by the driving TFT DT. For example, according to an embodiment of the present disclosure, a display device may be provided to have high resolution and improved display quality.
In some embodiments, the capacitor Cst has a thin insulating layer by including only a single second insulating layer GI2 as an insulating layer between the bottom electrode 51 and the top electrode 55 to improve storage capacity.
A third insulating layer 102 is formed on the array substrate 100 on which the second conductive wiring is formed. The third insulating layer 102 is formed of one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin by a spin coating method, but the third insulating layer 102 is not limited thereto. The third insulating layer 102 may be formed of not only an organic insulating material but also SiO2、SiNx、Al2O3、CuOx、Tb4O7、Y2O3、Nb2O5And Pr2O3The inorganic insulating material selected in (1), but the third insulating layer is not limited thereto. Further, the third insulating layer 102 may be formed by alternating the organic insulating material and the inorganic insulating material.
Then, referring to fig. 4 and 9, a plurality of contact holes 41, 42, 43, and 49 are formed in the third insulating layer 102 (operation S206). The contact holes 41, 42, 43, and 49 expose a portion of the control gate electrode 35 of the driving TFT DT, a portion of the drain region 11d of the switching TFT ST, a portion of the cap layer 53, and a portion of the top electrode 55 of the capacitor Cst, respectively.
The contact holes 41, 42, 43, and 49 may be formed through a mask process of uniformly coating a photoresist material on the entire array substrate 100, exposing a mask, and developing, etching, and stripping or ashing, but the present disclosure is not limited thereto. For example, the etching may be dry etching.
The contact hole 42 may be formed by etching the first insulating layer GI1, the second insulating layer GI2, and the third insulating layer 102 at the same (or substantially the same) time as or after the formation of the other contact holes 42, 43, and 49.
The contact holes 41, 42, 43, and 49 are cleaned by using (using) hydrofluoric acid (HF) or a Buffered Oxide Etchant (BOE) (operation S207). For example, a natural oxide film formed by stacking an inorganic layer on the active layer 11 may be removed by cleaning the contact hole 42 exposing a portion of the drain region of the active layer 11.
Since the capping layer 53, the top electrode 55 of the capacitor Cst, and the control gate electrode 35 of the driving tft dt, which are exposed through the contact holes 43, 49, and 41, respectively, are formed of materials having excellent heat resistance and chemical resistance, damage caused by dry etching and cleaning is small (or negligible). In addition, the cap layer 53 may protect the bottom electrode 51 of the capacitor Cst from the dry etching and cleaning.
Then, the connection member 40 is formed on the third insulating layer 102 by filling the plurality of contact holes 41, 42, 43, and 49 (operation S208). The connection member 40 may be formed in a single-layer or multi-layer structure including one or more materials selected from Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu. The drain electrode 11d of the switching TFT ST, the control gate electrode 35 of the driving TFT DT, and the bottom electrode 51 of the capacitor Cst are electrically connected by a connection member 40.
Fig. 11 is a schematic cross-sectional view of a TFT array substrate according to another embodiment of the present disclosure.
The embodiment shown in fig. 11 is different from the embodiment shown in fig. 9 in that a high dielectric constant (high K) material is located between the bottom electrode 51 and the top electrode 55 of the capacitor Cst. The remaining features of fig. 11 are the same (or substantially the same) as the corresponding features described above. Accordingly, a repeated description of those features will not be provided herein.
Referring to fig. 11, the active layer 11 of the switching TFT ST and the active layer 31 of the driving TFT DT are on (e.g., formed on) the array substrate 100, and the first insulating layer GI1 is on (e.g., formed on) the active layers 11 and 31. The auxiliary layer 101 may also be on (e.g., formed on) the array substrate 100.
Then, the first conductive wiring is on (e.g., formed on) the first insulating layer GI 1. The first conductive wiring may include the gate electrode 13 of the switching TFT ST, the floating gate electrode 33 of the driving TFT dt, and the bottom electrode 51 of the capacitor Cst. The first conductive wire may be formed in a structure including a single layer or multiple layers of a low resistance material (e.g., a low resistance material) such as aluminum (Al), an aluminum alloy (Al alloy), or copper (Cu), but the present disclosure is not limited thereto.
After the first conductive wiring is formed, the active layers 11 and 31 are doped and heat-treated.
Then, a second insulating layer GI2 is formed on the array substrate 100, and a contact hole H1 exposing a portion of the bottom electrode 51 of the capacitor Cst is formed in the second insulating layer GI 2. Further, at the same time (or substantially the same time) as (or after) the formation of the contact hole H1, or after the formation of the contact hole H1, the opening 70 exposing a portion of the bottom electrode 51 of the capacitor Cst is formed by removing the second insulating layer GI2 in the region corresponding to the top electrode 55.
Then, a high dielectric constant (high-K) material such as ZrO is deposited and patterned in the opening 70 by a masking process2、HfO3And Y2O3To form a high dielectric constantLayer 71, but the disclosure is not so limited. The high temperature of the high dielectric constant layer 71 in the heat treatment has no (or substantially no) change in the device characteristics, and can prevent (or reduce) current leakage. Therefore, the characteristic of the capacitor Cst becomes excellent.
Then, a second conductive wiring is formed on the second insulating layer GI2 and the high dielectric constant layer 71. The second conductive wiring may include the control gate electrode 35 of the driving TFT DT, the capping layer 53, and the top electrode 55 of the capacitor Cst. The second conductive wire may be formed to have a single-layer or multi-layer structure and include one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), but the present disclosure is not limited thereto.
Then, a third insulating layer 102 is formed on the array substrate 100 on which the second conductive wiring is formed. In addition, a plurality of contact holes 41, 42, 43, and 49 are formed in the third insulating layer 102 and cleaned. Then, the connection member 40 is formed on the third insulating layer 102 by filling the plurality of contact holes 41, 42, 43, and 49. The drain electrode 11d of the switching TFT ST, the control gate electrode 35 of the driving TFT DT, and the bottom electrode 51 of the capacitor Cst are electrically connected by a connection member 40.
The TFT array substrate according to the above-described embodiments may minimize (or reduce) damage to the low-resistance wiring due to a thermal process, cleaning, and contact hole dry etching process suitable for forming the substrate, by applying the low-resistance wiring to provide a substrate suitable for a high-resolution display device and forming a cap layer on the low-resistance wiring.
The above-described embodiments are not limited to the above-described pixel structure, and may be applied to any suitable pixel structure employing (or including) low-impedance wiring. Each pixel may include a plurality of TFTs and one or more capacitors. The pixel may have a separate wiring formed further and may be formed to have various structures by omitting the existing wiring.
The TFT array substrate according to the above-described embodiments is not limited to the OLED display device including the above-described organic light emitting device, and may be applied to various display devices including, for example, a liquid crystal display device.
As described above, according to one or more aspects of the above embodiments of the present disclosure, a thin film transistor array substrate to which a low resistance interconnect is applied and which is resistant to heat treatment and cleaning can be manufactured.
It should be understood that the exemplary embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects in each embodiment should generally be considered applicable to similar features or aspects in other embodiments.
Although one or more embodiments of the present disclosure have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims and their equivalents.
This application claims priority and benefit from korean patent application No.10-2013-0123594, filed in the korean intellectual property office at 16.10.2013, which is incorporated herein by reference in its entirety.

Claims (17)

1. A thin film transistor array substrate, comprising:
a first thin film transistor including a first active layer, a gate electrode, a first source electrode, and a first drain electrode;
a second thin film transistor including a second active layer, a first gate electrode, a second source electrode, and a second drain electrode, the first gate electrode being a layer between the second active layer and the second gate electrode;
a capacitor including a first electrode and a second electrode on the first electrode; and
a cap layer contacting a portion of the first electrode of the capacitor, the cap layer and the second electrode of the capacitor being on the same layer,
a connection member contacting the cap layer and electrically connected to the second gate electrode of the second thin film transistor and the cap layer,
wherein a first insulating layer is between the gate electrode and the first active layer of the first thin film transistor, and the first and second insulating layers are between the second gate electrode and the second active layer of the second thin film transistor,
wherein the second gate electrode of the second thin film transistor is over and completely overlaps the first gate electrode.
2. The thin film transistor array substrate of claim 1, wherein the first electrode of the capacitor and the gate electrode are on the same layer, and the second electrode of the capacitor and the second gate electrode are on the same layer.
3. The thin film transistor array substrate of claim 1, wherein the first electrode comprises a low resistivity material.
4. The thin film transistor array substrate of claim 3, wherein the low resistivity material comprises an aluminum alloy.
5. The thin film transistor array substrate of claim 1, wherein the cap layer comprises molybdenum.
6. The thin film transistor array substrate of claim 1, wherein the second insulating layer is between the first electrode and the second electrode of the capacitor, and the capping layer is electrically connected to the first electrode through a contact hole in the second insulating layer.
7. The thin film transistor array substrate of claim 1, wherein the first and second insulating layers each comprise an inorganic insulating material, an organic insulating material, or a structure in which an inorganic insulating material and an organic insulating material are alternated.
8. The thin film transistor array substrate of claim 6, further comprising a high dielectric constant material in at least a portion between the first and second electrodes of the capacitor.
9. A method of manufacturing a thin film transistor array substrate, the method comprising:
forming a first active layer of the first thin film transistor and a second active layer of the second thin film transistor;
forming a gate electrode over the first active layer of the first thin film transistor, a first gate electrode over the second active layer of the second thin film transistor, and a first electrode of a capacitor;
forming a second gate electrode over the first gate electrode of the second thin film transistor, a second electrode of the capacitor over the first electrode of the capacitor, and a capping layer contacting a portion of the first electrode; and
forming a connection member contacting the cap layer and electrically connected to the second gate electrode of the second thin film transistor and the cap layer;
forming a first insulating layer between the gate electrode and the first active layer of the first thin film transistor and between the first gate electrode and the second active layer of the second thin film transistor; and
forming a second insulating layer between the first gate electrode and the second gate electrode of the second thin film transistor,
wherein the second gate electrode of the second thin film transistor completely overlaps the first gate electrode.
10. The method of claim 9, further comprising doping and heat treating the first and second active layers between forming the gate electrode and the first gate electrode and forming the second gate electrode.
11. The method of claim 9, wherein the first electrode comprises a low resistivity material.
12. The method of claim 11 wherein said low resistivity material comprises an aluminum alloy.
13. The method of claim 9, wherein the cap layer comprises molybdenum.
14. The method of claim 9, wherein forming the second insulating layer comprises forming the second insulating layer between the first electrode and the second electrode of the capacitor, and
forming the cap layer includes:
forming a first contact hole in the second insulating layer to expose a portion of the first electrode; and
forming a capping layer electrically connected to the first electrode through the first contact hole formed in the second insulating layer.
15. The method of claim 9, further comprising:
forming a third insulating layer on the cap layer;
forming a second contact hole in the third insulating layer to expose a portion of the cap layer; and
forming the connection member electrically connected to the cap layer through the second contact hole.
16. The method of claim 15, wherein forming the second contact hole comprises:
coating a photoresist material on the third insulating layer;
dry etching the photoresist material to form the second contact hole; and
and cleaning the second contact hole.
17. The method of claim 14, wherein, while or after forming the first contact hole to expose a portion of the first electrode, the method further comprises: forming an opening in the second insulating layer to expose another portion of the first electrode, an
Forming a layer of high dielectric constant material in the opening prior to forming the cap layer.
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