CN104576639A - High-voltage ESD protection device with small hysteresis window - Google Patents
High-voltage ESD protection device with small hysteresis window Download PDFInfo
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- CN104576639A CN104576639A CN201410765827.1A CN201410765827A CN104576639A CN 104576639 A CN104576639 A CN 104576639A CN 201410765827 A CN201410765827 A CN 201410765827A CN 104576639 A CN104576639 A CN 104576639A
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Abstract
The invention discloses a high-voltage ESD protection device with a small hysteresis window. The high-voltage ESD protection device can be used for an ESD protection circuit of an on-chip high-voltage IC. The high-voltage ESD protection device mainly comprises a P type substrate, an N type buried layer, an N well, P wells, a plurality of P+ injection regions, a plurality of N+ injection regions, double polysilicon gates and a plurality of field oxide isolation regions. According to the protection device, two ESD current discharge paths consisting of LDMOSs and SCRs are formed under the action of high-voltage ESD pulses; parasitic PNP transistors and N-well resistors form a common branch of the current discharge paths, so that the electron emissivity of the device is reduced, and the maintaining voltage and ESD robustness are improved; in addition, a Zener diode is arranged in the device so as to reduce triggering voltage and realize high-voltage ESD protection with the small hysteresis window.
Description
Technical field
The invention belongs to the electrostatic protection field of integrated circuit, relate to a kind of high-voltage ESD protective device, be specifically related to a kind of high-voltage ESD protective device with little time stagnant window, can be used for the reliability of high pressure IC esd protection in improved sheet.
Background technology
Along with the fast development of Based Power Integrated Circuit Technology, electronic product is day by day miniaturized, complicated, and the demand of portable hard drive, flash card, USB interface and smart mobile phone display touch-screen etc. constantly increases, and on sheet, the integrity problem of high pressure IC product also becomes increasingly conspicuous.The integrity problems such as flash card cannot read data suddenly, USB interface cannot carry out data communication, the unexpected blank screen of display touch-screen more and more cause concern.In these high pressure IC product interface sheet on the high pressure esd protection of IC, be the technological difficulties in whole Circuits System ESD protection Design.
Most current high-voltage ESD protective device is difficult to meet the many requirement of high pressure IC to esd protection scheme: as there being the ME for maintenance higher than operating voltage; have as far as possible lower than the trigger voltage of grid oxygen puncture voltage again, simultaneously also will by the esd protection standard of IEC6001-4-2.In brief, existing high pressure esd protection scheme lacks the ESD protective device that can meet the strong robustness of narrow ESD window.And; due to many high pressure IC products be often operated in the environment comparing " badly " under (as high voltage, big current, strong electromagnetic, frequent plug and high/low temperature operational environment etc.); their esd protection design is made to need consideration more multifactor; embody a concentrated reflection of high-voltage ESD protective device on sheet and need that there is good anti-electromagnetic interference capability, and esd protection unit needs to have the combination properties such as good anti-error burst capability, anti-breech lock ability and strong robustness.Although existing partial high pressure esd protection scheme is suggested, successively as the strong ESD robustness protection scheme of LDMOS-SCR structure and the high pressure resistant protection scheme etc. of DeMOS structure.But on the one hand because esd protection design is by the restriction of the work characteristics of protected circuit, on the other hand by the demand that consumer electronics constantly promote electrostatic defending level, on sheet, the esd protection design of high pressure IC is difficult to the bottleneck breaking through prior art.
Summary of the invention
For the technological deficiency that existing esd protection scheme exists; the embodiment of the present invention devises a kind of high-voltage ESD protective device with little time stagnant window; make full use of the high pressure resistant and SCR device strong robustness of LDMOS device, feature that conducting resistance is little; by designing the key characterization parameter of device architecture and conservative control device; the trigger voltage of device can be reduced; improve the ME for maintenance of device, the esd protection of high pressure IC on the high-reliable blade realizing having the low on-resistance of little time stagnant window, strong ESD robustness.
The present invention is achieved through the following technical solutions:
A kind of high-voltage ESD protective device with little time stagnant window, it is characterized in that: primarily of P type substrate, n type buried layer, a P trap, a N trap and the 2nd P trap, first oxygen isolated area, a P+ injection region, second oxygen isolated area, a N+ injection region, the first polysilicon gate, the 3rd oxygen isolated area, the 2nd N+ injection region, the 3rd N+ injection region, the 2nd P+ injection region, the 4th oxygen isolated area, the second polysilicon gate, the 4th N+ injection region, the 5th oxygen isolated area, the 3rd P+ injection region and the 6th oxygen isolated area are formed;
Described P type substrate is provided with described n type buried layer; Described n type buried layer can being uniformly distributed, to improve the ESD robustness of device of enhance device internal electric field;
Described n type buried layer is from left to right provided with a described P trap, a described N trap and described 2nd P trap successively;
Described n type buried layer must cover a described N trap completely, and the right side of a described P trap is connected with the left side of a described N trap, and the right side of a described N trap is connected with the left side of described 2nd P trap;
A described P trap is from left to right provided with described first oxygen isolated area, a described P+ injection region, described second oxygen isolated area, a described N+ injection region and described first polysilicon gate successively;
The left side of described first oxygen isolated area is connected with the left side edge of a described P trap, the right side of described first oxygen isolated area is connected with the left side of a described P+ injection region, the right side of a described P+ injection region is connected with the left side of described second oxygen isolated area, the right side of described second oxygen isolated area is connected with the left side of a described N+ injection region, and the right side of a described N+ injection region is connected with the left side of described first polysilicon gate;
A described N trap is from left to right provided with described 3rd N+ injection region, described 2nd P+ injection region successively, and the right side of described 3rd N+ injection region is connected with the left side of described 2nd P+ injection region; Variable spacing D3 is provided with between the left side and the right side of described 2nd N+ injection region of described 3rd N+ injection region, the left side of described 2nd N+ injection region is connected with the right side of described first polysilicon gate, described 2nd N+ injection region is across the surface portion region between a described P trap and a described N trap, and described 3rd oxygen isolated area covers on described 2nd N+ injection region and described first polycrystalline silicon gate surface subregion;
Described 2nd P trap is from left to right provided with described second polysilicon gate, described 4th N+ injection region, described 5th oxygen isolated area, described 3rd P+ injection region and described 6th oxygen isolated area successively; The left side of described second polysilicon gate is connected with the left side edge of described 2nd P trap, the right side of described second polysilicon gate is connected with the left side of described 4th N+ injection region, the right side of described 4th N+ injection region is connected with the left side of described 5th oxygen isolated area, the right side of described 5th oxygen isolated area is connected with the left side of described 3rd P+ injection region, the right side of described 3rd P+ injection region is connected with the left side of described 6th oxygen isolated area, and the right side of described 6th oxygen isolated area is connected with the right side edge of described 2nd P trap;
Described 4th oxygen isolated area is across on the surface portion region between a described N trap and described 2nd P trap, the right part region overlay of described 4th oxygen isolated area is on the portion surface area of described second polysilicon gate, the left part region overlay of described 4th oxygen isolated area is on the portion surface area of a described N trap, and the left side of described 4th oxygen isolated area is connected with the right side of described 2nd P+ injection region;
A described P+ injection region is connected by the first metal layer of contact hole with metal level 1, a described N+ injection region is connected with the second metal level of metal level 1 by contact hole, described 3rd N+ injection region is connected with the 3rd metal level of metal level 1 by contact hole, described 2nd P+ injection region is connected with the 4th metal level of metal level 1 by contact hole, described 4th N+ injection region is connected with the 5th metal level of metal level 1 by contact hole, described 3rd P+ injection region is connected with the 6th metal level of metal level 1 by contact hole, described first polysilicon gate is connected with the 7th metal level of metal level 1 by contact hole, described second polysilicon gate is connected with the 8th metal level of metal level 1 by contact hole, the described the first metal layer of metal level 1, described second metal level, described 3rd metal level, described 4th metal level, described 5th metal level, described 6th metal level, described 7th metal level, described 8th metal level covers a described P+ injection region respectively, a described N+ injection region, described 3rd N+ injection region, described 2nd P+ injection region, described 4th N+ injection region, described 3rd P+ injection region, on the surf zone of described first polysilicon gate and described second polysilicon gate,
9th metal level of metal level 2 is provided with metal throuth hole, described 3rd metal level of metal level 1, described 4th metal level are all connected with described 9th metal level of metal level 2 by described metal throuth hole, described metal throuth hole is connected with the first pad, as the anode of device; Tenth metal level of metal level 2 is provided with metal throuth hole, the described the first metal layer of metal level 1, described second metal level, described 5th metal level, described 6th metal level, described 7th metal level and described eight metal levels are all connected with described tenth metal level of metal level 2 by described metal throuth hole, described metal throuth hole is connected with the second pad, as the negative electrode of device;
When the positive pole of high pressure esd pulse is connected with the described anode of device, when the negative pole of high pressure esd pulse is connected with the described negative electrode of device, the ESD current path of a LDMOS structure is made up of on the one hand described 3rd N+ injection region, described 2nd N+ injection region, described first polysilicon gate, described 3rd oxygen isolated area, a described N trap, a described P trap and a described N+ injection region, and described 2nd N+ injection region is across between a described P trap and a described N trap, to reduce the trigger voltage of LDMOS structure; The ESD current drain path of a LDMOS-SCR structure is made up of on the other hand, to improve ME for maintenance and ESD robustness described 3rd N+ injection region, described 2nd P+ injection region, described second polysilicon gate, described 4th oxygen isolated area, a described N trap and described 2nd P trap.
Advantageous Effects of the present invention is:
The resistance R2 of a parasitism is made up of described 3rd N+ injection region and a described N trap, by described 2nd P+ injection region, a described N trap and a described P trap form the transistor T3 of a parasitism, the Zener diode ZD of a parasitism is made up of described 2nd N+ injection region and a described P trap, by a described N+ injection region, a described P trap and a described N trap form the transistor T1 of a parasitism, the resistance R1 of a parasitism is made up of a described P+ injection region and a described P trap, by a described N trap, described 2nd P trap and described 4th injection region form the transistor T2 of a parasitism, the resistance R3 of a parasitism is made up of described 3rd P+ injection region and described 2nd P trap, first pin of described resistance R1, first pin of described resistance R3, the emitter of described transistor T2 is all connected with the described negative electrode of device with the emitter of described transistor T1, second pin of described resistance R1, second pin of described resistance R3, the base stage of described transistor T1, the base stage of described transistor T2, the collector electrode of described transistor T3 is all connected with the anode of described Zener diode ZD, the collector electrode of described transistor T1, the negative electrode of described Zener diode ZD, the base stage of described transistor T3, the collector electrode of described transistor T2 is all connected with first pin of described resistance R2, second pin of described dead resistance R2 is all connected with the described anode of device with the emitter of described transistor T3, under the effect of forward esd pulse, described resistance R2, described transistor T3, described transistor T1, SCR structure on the left of described resistance R1 formation one, described resistance R2, described transistor T3 and described transistor T2, SCR structure on the right side of described resistance R3 formation one, described left side SCR structure and described right side SCR structure all share the emitter of described transistor T3, the electron emissivity of described left side SCR structure and described right side SCR structure can be reduced, improve ME for maintenance.
The space D 1 be made up of a described N+ injection region and described 2nd N+ injection region, the space D 2 be made up of the left side edge of described 4th N+ injection region and described 2nd P trap, the described space D 3 be made up of described 2nd N+ injection region (112) and described 3rd N+ injection region (113) is all adjustable, with the trigger voltage of conservative control device and ME for maintenance.
Embodiment of the present invention device takes full advantage of that SCR opening speed is fast, little, the advantage that current drain ability strong high pressure resistant with LDMOS of secondary breakdown current large (strong robustness), conducting resistance, on this basis, by the design internal structure of device and the key characterization parameter of conservative control device, reduce device trigger voltage, improve ME for maintenance and the ESD robustness of device.
Compared with prior art, embodiment of the present invention device not only has the resistance to breakdown capability of certain high pressure, suitably reduces again the trigger voltage of device, improves ME for maintenance, reduces ESD and returns stagnant window, reduce conducting resistance, enhances ESD current drain ability.Correct the shortcomings such as LDMOS high voltage protective device robustness was weak in the past, response speed slowly can not be opened in time, easy breech lock, the esd protection demand of high pressure IC on sheet can have been realized better.
Accompanying drawing explanation
Fig. 1 is the internal structure generalized section of the embodiment of the present invention;
Fig. 2 is the circuit connection diagram of the embodiment of the present invention for high pressure esd protection;
Fig. 3 is the inside equivalent electric circuit of the embodiment of the present invention under the effect of forward esd pulse;
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
The present invention proposes a kind of high-voltage ESD protective device with little time stagnant window, because of the particular design of its internal structure and the conservative control of key characterization parameter, the advantage that opening speed is fast, conducting resistance is little, secondary breakdown current is large of embodiment of the present invention device existing SCR structure ESD protective device; Again by reducing the emissivity of parasitic PNP pipe, improve ME for maintenance.Also by introducing Zener diode breakdown characteristics, reducing the trigger voltage of device, realizing the high-performance esd protection with little time stagnant window.Be conducive to by Stack Technology, expand the range of application of embodiment of the present invention device.
As shown in Figure 1, a kind of high-voltage ESD protective device with little time stagnant window, it is characterized in that: primarily of P type substrate 101, n type buried layer 102, one P trap 103, one N trap 104 and the 2nd P trap 105, first oxygen isolated area 106, one P+ injection region 107, second oxygen isolated area 108, one N+ injection region 109, first polysilicon gate 110, 3rd oxygen isolated area 111, 2nd N+ injection region 112, 3rd N+ injection region 113, 2nd P+ injection region 114, 4th oxygen isolated area 115, second polysilicon gate 116, 4th N+ injection region 117, 5th oxygen isolated area 118, 3rd P+ injection region 119 and the 6th oxygen isolated area 120 are formed,
Described P type substrate 101 is provided with the heavily doped described n type buried layer 102 of N-type; Described n type buried layer 102 can being uniformly distributed of enhance device internal electric field, to improve the ESD robustness of device, to preparing example of the present invention without on the semiconductor preparing process platform of described n type buried layer, also can remove described n type buried layer 102, the preparation flow of following example device of the present invention also can realize in described P type substrate 101 or P type extension;
Described n type buried layer 102 is from left to right provided with successively a described P trap 103, a described N trap 104 and described 2nd P trap 105; Described n type buried layer 102 must cover a described N trap 104 completely, and the right side of a described P trap 103 is connected with the left side of a described N trap 104, and the right side of a described N trap 104 is connected with the left side of described 2nd P trap 105;
A described P trap 103 is from left to right provided with described first oxygen isolated area 106, a described P+ injection region 107, described second oxygen isolated area 108, a described N+ injection region 109 and described first polysilicon gate 110 successively, the conducting channel of LDMOS structure can be formed under the thin grid oxide layer that described first polysilicon gate 110 covers; The left side of described first oxygen isolated area 106 is connected with the left side edge of a described P trap 103, the right side of described first oxygen isolated area 106 is connected with the left side of a described P+ injection region 107, the right side of a described P+ injection region 107 is connected with the left side of described second oxygen isolated area 108, the right side of described second oxygen isolated area 108 is connected with the left side of a described N+ injection region 109, and the right side of a described N+ injection region 109 is connected with the left side of described first polysilicon gate 110;
A described N trap 104 is from left to right provided with described 3rd N+ injection region 113, described 2nd P+ injection region 114 successively, and the right side of described 3rd N+ injection region 113 is connected with the left side of described 2nd P+ injection region 114; The left side of described 3rd N+ injection region 113 and the right side of described 2nd N+ injection region 112 are provided with variable spacing D3, the left side of described 2nd N+ injection region 112 is connected with the right side of described first polysilicon gate 110, described 2nd N+ injection region 112 is across the surface portion region between a described P trap 103 and a described N trap 104, and described 3rd oxygen isolated area 111 covers on described 2nd N+ injection region 112 and described first polysilicon gate 110 surface portion region;
Described 2nd P trap 105 is from left to right provided with described second polysilicon gate 116, described 4th N+ injection region 117, described 5th oxygen isolated area 118, described 3rd P+ injection region 119 and described 6th oxygen isolated area 120 successively, the left side of described second polysilicon gate 116 is connected with the left side edge of described 2nd P trap 105, the right side of described second polysilicon gate 116 is connected with the left side of described 4th N+ injection region 117, the right side of described 4th N+ injection region 117 is connected with the left side of described 5th oxygen isolated area 118, the right side of described 5th oxygen isolated area 118 is connected with the left side of described 3rd P+ injection region 119, the right side of described 3rd P+ injection region 119 is connected with the left side of described 6th oxygen isolated area 120, the right side of described 6th oxygen isolated area 120 is connected with the right side edge of described 2nd P trap 105,
Described 4th oxygen isolated area 115 is across on the surface portion region of a described N trap 104 and described 2nd P trap 105, the right part region overlay of described 4th oxygen isolated area 115 is on the portion surface area of described second polysilicon gate 116, the left part region overlay of described 4th oxygen isolated area 115 is on the portion surface area of a described N trap 104, and the left side of described 4th oxygen isolated area 115 is connected with the right side of described 2nd P+ injection region 114; The conducting channel of a LDMOS-SCR structure can be formed under the grid thin oxide layer that described second polysilicon gate 116 covers;
As shown in Figure 2, a described P+ injection region 107 is connected with the first metal layer 201 of metal level 1 by contact hole, a described N+ injection region 109 is connected with the second metal level 202 of metal level 1 by contact hole, described 3rd N+ injection region 113 is connected with the 3rd metal level 203 of metal level 1 by contact hole, described 2nd P+ injection region 114 is connected with the 4th metal level 204 of metal level 1 by contact hole, described 4th N+ injection region 117 is connected with the 5th metal level 205 of metal level 1 by contact hole, described 3rd P+ injection region 119 is connected with the 6th metal level 206 of metal level 1 by contact hole, described first polysilicon gate 110 is connected with the 7th metal level 207 of metal level 1 by contact hole, described second polysilicon gate 116 is connected with the 8th metal level 208 of metal level 1 by contact hole, the described the first metal layer 201 of metal level 1, described second metal level 202, described 3rd metal level 203, described 4th metal level 204, described 5th metal level 205, described 6th metal level 206, described 7th metal level 207, described 8th metal level 208 covers a described P+ injection region 107 respectively, a described N+ injection region 109, described 3rd N+ injection region 113, described 2nd P+ injection region 114, described 4th N+ injection region 117, described 3rd P+ injection region 119, on the surf zone of described first polysilicon gate 110 and described second polysilicon gate 116,
9th metal level 209 of metal level 2 is provided with metal throuth hole 210, described 3rd metal level 203 of metal level 1, described 4th metal level 204 are all connected with described 9th metal level 209 of metal level 2 by described metal throuth hole 210, described metal throuth hole 210 is connected with the first pad, as the anode of device; Tenth metal level 211 of metal level 2 is provided with metal throuth hole 212, the described the first metal layer 201 of metal level 1, described second metal level 202, described 5th metal level 205, described 6th metal level 206, described 7th metal level 207 and described eight metal levels 208 are all connected with described tenth metal level 211 of metal level 2 by described metal throuth hole 212, described metal throuth hole 212 is connected with the second pad, as the negative electrode of device;
When the positive pole of high pressure esd pulse is connected with the described anode of device, when the negative pole of high pressure esd pulse is connected with the described negative electrode of device, the ESD current path of a LDMOS structure is made up of on the one hand described 3rd N+ injection region 113, described 2nd N+ injection region 112, described first polysilicon gate 110, described 3rd oxygen isolated area 111, a described N trap 104, a described P trap 103 and a described N+ injection region 109, and described 2nd N+ injection region 112 is across between a described P trap 103 and a described N trap 104, to reduce the trigger voltage of LDMOS structure; The ESD current drain path of a LDMOS-SCR structure is made up of on the other hand, to improve ME for maintenance and ESD robustness described 3rd N+ injection region 113, described 2nd P+ injection region 114, described second polysilicon gate 116, described 4th oxygen isolated area 115, a described N trap 104 and described 2nd P trap 105.
As shown in Figure 3, the resistance R2 of a parasitism is made up of described 3rd N+ injection region 113 and a described N trap 104, by described 2nd P+ injection region 114, a described N trap 104 and a described P trap 103 form the transistor T3 of a parasitism, the Zener diode ZD of a parasitism is made up of described 2nd N+ injection region 112 and a described P trap 103, by a described N+ injection region 109, a described P trap 103 and a described N trap 104 form the transistor T1 of a parasitism, the resistance R1 of a parasitism is made up of a described P+ injection region 107 and a described P trap 103, by a described N trap 104, described 2nd P trap 105 and described 4th injection region 117 form the transistor T2 of a parasitism, the resistance R3 of a parasitism is made up of described 3rd P+ injection region 119 and described 2nd P trap 105, first pin of described resistance R1, first pin of described resistance R3, the emitter of described transistor T2 is all connected with the described negative electrode of device with the emitter of described transistor T1, second pin of described resistance R1, second pin of described resistance R3, the base stage of described transistor T1, the base stage of described transistor T2, the collector electrode of described transistor T3 is all connected with the anode of described Zener diode ZD, the collector electrode of described transistor T1, the negative electrode of described Zener diode ZD, the base stage of described transistor T3, the collector electrode of described transistor T2 is all connected with first pin of described resistance R2, second pin of described dead resistance R2 is all connected with the described anode of device with the emitter of described transistor T3, under the effect of forward esd pulse, described resistance R2, described transistor T3, described transistor T1, SCR structure on the left of described resistance R1 formation one, described resistance R2, described transistor T3 and described transistor T2, SCR structure on the right side of described resistance R3 formation one, described left side SCR structure and described right side SCR structure all share the emitter of described transistor T3, the electron emissivity of described left side SCR structure and described right side SCR structure can be reduced, improve ME for maintenance.
What finally illustrate is, above embodiment is only in order to illustrate technical scheme of the present invention and unrestricted, although with reference to preferred embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that, can modify to technical scheme of the present invention or equivalent replacement, and not departing from aim and the scope of technical solution of the present invention, it all should be encompassed in the middle of right of the present invention.
Claims (3)
1. one kind has the high-voltage ESD protective device of little time stagnant window, it is characterized in that: primarily of P type substrate (101), n type buried layer (102), one P trap (103), one N trap (104) and the 2nd P trap (105), first oxygen isolated area (106), one P+ injection region (107), second oxygen isolated area (108), one N+ injection region (109), first polysilicon gate (110), 3rd oxygen isolated area (111), 2nd N+ injection region (112), 3rd N+ injection region (113), 2nd P+ injection region (114), 4th oxygen isolated area (115), second polysilicon gate (116), 4th N+ injection region (117), 5th oxygen isolated area (118), 3rd P+ injection region (119) and the 6th oxygen isolated area (120) are formed,
Described P type substrate (101) is provided with described n type buried layer (102); Described n type buried layer (102) can being uniformly distributed, to improve the ESD robustness of device of enhance device internal electric field;
Described n type buried layer (102) is from left to right provided with a described P trap (103), a described N trap (104) and described 2nd P trap (105) successively;
Described n type buried layer (102) must cover a described N trap (104) completely, the right side of a described P trap (103) is connected with the left side of a described N trap (104), and the right side of a described N trap (104) is connected with the left side of described 2nd P trap (105);
A described P trap (103) is from left to right provided with described first oxygen isolated area (106), a described P+ injection region (107), described second oxygen isolated area (108), a described N+ injection region (109) and described first polysilicon gate (110) successively;
The left side of described first oxygen isolated area (106) is connected with the left side edge of a described P trap (103), the right side of described first oxygen isolated area (106) is connected with the left side of a described P+ injection region (107), the right side of a described P+ injection region (107) is connected with the left side of described second oxygen isolated area (108), the right side of described second oxygen isolated area (108) is connected with the left side of a described N+ injection region (109), the right side of a described N+ injection region (109) is connected with the left side of described first polysilicon gate (110),
A described N trap (104) is from left to right provided with described 3rd N+ injection region (113), described 2nd P+ injection region (114) successively, and the right side of described 3rd N+ injection region (113) is connected with the left side of described 2nd P+ injection region (114);
Variable spacing D3 is provided with between the left side and the right side of described 2nd N+ injection region (112) of described 3rd N+ injection region (113), the left side of described 2nd N+ injection region (112) is connected with the right side of described first polysilicon gate (110), described 2nd N+ injection region (112) is across the surface portion region between a described P trap (103) and a described N trap (104), described 3rd oxygen isolated area (111) covers on described 2nd N+ injection region (112) and described first polysilicon gate (110) surface portion region,
Described 2nd P trap (105) is from left to right provided with described second polysilicon gate (116), described 4th N+ injection region (117), described 5th oxygen isolated area (118), described 3rd P+ injection region (119) and described 6th oxygen isolated area (120) successively;
The left side of described second polysilicon gate (116) is connected with the left side edge of described 2nd P trap (105), the right side of described second polysilicon gate (116) is connected with the left side of described 4th N+ injection region (117), the right side of described 4th N+ injection region (117) is connected with the left side of described 5th oxygen isolated area (118), the right side of described 5th oxygen isolated area (118) is connected with the left side of described 3rd P+ injection region (119), the right side of described 3rd P+ injection region (119) is connected with the left side of described 6th oxygen isolated area (120), the right side of described 6th oxygen isolated area (120) is connected with the right side edge of described 2nd P trap (105),
Described 4th oxygen isolated area (115) is across on the surface portion region between a described N trap (104) and described 2nd P trap (105), the right part region overlay of described 4th oxygen isolated area (115) is on the portion surface area of described second polysilicon gate (116), the left part region overlay of described 4th oxygen isolated area (115) is on the portion surface area of a described N trap (104), and the left side of described 4th oxygen isolated area (115) is connected with the right side of described 2nd P+ injection region (114);
A described P+ injection region (107) is connected with the first metal layer (201) of metal level 1 by contact hole, a described N+ injection region (109) is connected with second metal level (202) of metal level 1 by contact hole, described 3rd N+ injection region (113) is connected with the 3rd metal level (203) of metal level 1 by contact hole, described 2nd P+ injection region (114) is connected with the 4th metal level (204) of metal level 1 by contact hole, described 4th N+ injection region (117) is connected with the 5th metal level (205) of metal level 1 by contact hole, described 3rd P+ injection region (119) is connected with the 6th metal level (206) of metal level 1 by contact hole, described first polysilicon gate (110) is connected with the 7th metal level (207) of metal level 1 by contact hole, described second polysilicon gate (116) is connected with the 8th metal level (208) of metal level 1 by contact hole, the described the first metal layer (201) of metal level 1, described second metal level (202), described 3rd metal level (203), described 4th metal level (204), described 5th metal level (205), described 6th metal level (206), described 7th metal level (207), described 8th metal level (208) covers a described P+ injection region (107) respectively, a described N+ injection region (109), described 3rd N+ injection region (113), described 2nd P+ injection region (114), described 4th N+ injection region (117), described 3rd P+ injection region (119), on the surf zone of described first polysilicon gate (110) and described second polysilicon gate (116),
9th metal level (209) of metal level 2 is provided with metal throuth hole (210), described 3rd metal level (203) of metal level 1, described 4th metal level (204) are all connected with described 9th metal level (209) of metal level 2 by described metal throuth hole (210), described metal throuth hole (210) is connected with the first pad, as the anode of device; Tenth metal level (211) of metal level 2 is provided with metal throuth hole (212), the described the first metal layer (201) of metal level 1, described second metal level (202), described 5th metal level (205), described 6th metal level (206), described 7th metal level (207) are all connected with described tenth metal level (211) of metal level 2 by described metal throuth hole (212) with described eight metal levels (208), described metal throuth hole (212) is connected with the second pad, as the negative electrode of device;
When the positive pole of high pressure esd pulse is connected with the described anode of device, when the negative pole of high pressure esd pulse is connected with the described negative electrode of device, on the one hand by described 3rd N+ injection region (113), described 2nd N+ injection region (112), described first polysilicon gate (110), described 3rd oxygen isolated area (111), a described N trap (104), a described P trap (103) and a described N+ injection region (109) form the ESD current path of a LDMOS structure, and described 2nd N+ injection region (112) is across between a described P trap (103) and a described N trap (104), to reduce the trigger voltage of LDMOS structure, the ESD current drain path of a LDMOS-SCR structure is made up of on the other hand, to improve ME for maintenance and ESD robustness described 3rd N+ injection region (113), described 2nd P+ injection region (114), described second polysilicon gate (116), described 4th oxygen isolated area (115), a described N trap (104) and described 2nd P trap (105).
2. a kind of high-voltage ESD protective device with little time stagnant window as claimed in claim 1, it is characterized in that: the resistance R2 being made up of a parasitism described 3rd N+ injection region (113) and a described N trap (104), by described 2nd P+ injection region (114), a described N trap (104) and a described P trap (103) form the transistor T3 of a parasitism, the Zener diode ZD of a parasitism is made up of described 2nd N+ injection region (112) and a described P trap (103), by a described N+ injection region (109), a described P trap (103) and a described N trap (104) form the transistor T1 of a parasitism, the resistance R1 of a parasitism is made up of a described P+ injection region (107) and a described P trap (103), by a described N trap (104), described 2nd P trap (105) and described 4th injection region (117) form the transistor T2 of a parasitism, the resistance R3 of a parasitism is made up of described 3rd P+ injection region (119) and described 2nd P trap (105), first pin of described resistance R1, first pin of described resistance R3, the emitter of described transistor T2 is all connected with the described negative electrode of device with the emitter of described transistor T1, second pin of described resistance R1, second pin of described resistance R3, the base stage of described transistor T1, the base stage of described transistor T2, the collector electrode of described transistor T3 is all connected with the anode of described Zener diode ZD, the collector electrode of described transistor T1, the negative electrode of described Zener diode ZD, the base stage of described transistor T3, the collector electrode of described transistor T2 is all connected with first pin of described resistance R2, second pin of described dead resistance R2 is all connected with the described anode of device with the emitter of described transistor T3, under the effect of forward esd pulse, described resistance R2, described transistor T3, described transistor T1, SCR structure on the left of described resistance R1 formation one, described resistance R2, described transistor T3 and described transistor T2, SCR structure on the right side of described resistance R3 formation one, described left side SCR structure and described right side SCR structure all share the emitter of described transistor T3, the electron emissivity of described left side SCR structure and described right side SCR structure can be reduced, improve ME for maintenance.
3. a kind of high-voltage ESD protective device with little time stagnant window as claimed in claim 1; it is characterized in that: the space D 1 be made up of a described N+ injection region (109) and described 2nd N+ injection region (112), the space D 2 be made up of the left side edge of described 4th N+ injection region (117) and described 2nd P trap (105), the described space D 3 be made up of described 2nd N+ injection region (112) and described 3rd N+ injection region (113) is all adjustable, with the trigger voltage of conservative control device and ME for maintenance.
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| CN109065537A (en) * | 2018-08-24 | 2018-12-21 | 电子科技大学 | High maintenance electric current SCR device for ESD protection |
| CN109119416A (en) * | 2018-08-24 | 2019-01-01 | 电子科技大学 | High maintenance electric current ESD protection device |
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| CN103730462A (en) * | 2014-01-20 | 2014-04-16 | 江南大学 | ESD self-protection device with LDMOS-SCR structure and high in holding current and robustness |
| CN204271080U (en) * | 2014-12-11 | 2015-04-15 | 江南大学 | A kind of high-voltage ESD protective device with little time stagnant window |
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| CN103606548A (en) * | 2013-12-09 | 2014-02-26 | 江南大学 | Zener breakdown high-voltage ESD (Electronic Static Discharge) protective device with small-hysteresis SCR (Selective Catalytic Reduction) structure |
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| CN109065537B (en) * | 2018-08-24 | 2021-01-08 | 电子科技大学 | High-maintenance-current SCR device for ESD protection |
| CN109119416B (en) * | 2018-08-24 | 2023-03-03 | 电子科技大学 | High holding current ESD protection device |
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