CN104575313A - Eight-level LED (light emitting diode) light cube display screen - Google Patents
Eight-level LED (light emitting diode) light cube display screen Download PDFInfo
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- CN104575313A CN104575313A CN201510042626.3A CN201510042626A CN104575313A CN 104575313 A CN104575313 A CN 104575313A CN 201510042626 A CN201510042626 A CN 201510042626A CN 104575313 A CN104575313 A CN 104575313A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Led Device Packages (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
An eight-level LED (light emitting diode) light cube display screen is provided with a light cube and a control mechanism, wherein the light cube is provided with a substrate, N row holes Paik (k=1, 2, 3, ......, N-1, N), N wires Cs (s-1, 2, 3, ......, N-1, N) and a cube structure; the N row holes are formed in the substrate; the cube structure consists of NxNxN LED diodes which are arrayed in a matrix manner; the cube structure consists of N cubic plane layers; the LEDs in each cubic plane layer are arrayed as a matrix structure in N lines and N rows; and the control mechanism is provided with a power supply VCC, a chip U1, a latch unit and a switch amplifying unit. The eight-level LED light cube display screen does not have a support, a stereoscopic matrix structure is directly formed by the LEDs, and when in a working state, the eight-level LED light cube display screen has the advantages of high transparency, high stereoscopic impression and high displaying effect. A circuit structure of the control mechanism is simple, and a control effect is high.
Description
Technical field
The present invention relates to technical field of LED display, particularly relate to a kind of eight rank LED light cube display screens.
Background technology
Along with the high speed development of information society and the development of broadband network, digitized multimedia show occupies main flow gradually in message area, and replacement conventional television is become the center that people enjoy information and content of multimedia by novel large-screen display equipment.
LED display is made up of LED matrix-block usually, can realize dynamic graphics and text display.Dynamic graphics and text display screen can with computing machine simultaneous display Chinese character, English text and figure; Video display screen adopts microcomputer to control, picture and text, image luxuriant, with in real time, synchronously, clearly information propagation pattern play various information, also can show two dimension, three-dimensional animation, video recording, TV, VCD program and on-the-spot circumstance and relay.And display frame is bright in luster, stereoscopic sensation is strong, quiet as oil painting, dynamic as film, is widely used in the public places such as communications and transportation, station, market, hospital, hotel, securities market, Industrial Management.
Stereo display receives much concern because it can show various space pattern, and in prior art, although light cube LED can realize stereo display, owing to inevitably needing support in structure, therefore penetrating not, display effect is limited.In addition, there is circuit structure complexity in control circuit part, controls the defect of inconvenience.
Therefore, not enough for prior art, provide that a kind of stereo display effect is good, the simple eight rank LED light cube display screens of control structure are very necessary to overcome prior art deficiency.
Summary of the invention
The object of the invention is to avoid the deficiencies in the prior art part and a kind of eight rank LED light cube display screens are provided, this eight rank LED light cube display screen has when stereo display that permeability is good, stereoscopic sensation is strong, display effect is good, the feature that control structure is simple, control effects is good.
Above-mentioned purpose of the present invention is realized by following technological means.
A kind of eight rank LED light cube display screens are provided, are provided with light cube and control gear;
Described smooth cube is provided with substrate, is arranged at N number of round Pai of substrate
k(k=1,2,3 ..., N-1, N), N root wire C
s(s=1,2,3 ..., N-1, N) and by N
×n
×the cube structure that N number of LED diode is formed according to matrix arrangement, described cube structure is made up of N layer cubic plane layer, and the LED diode structure in every layer of cubic plane layer is that N is capable, N column matrix structural arrangement, wherein N=8;
Round Pai
kbe provided with N number of be arranged in a linear meet hole i
km(m=1,2,3 ..., N-1, N);
To be parallel to the plane at substrate place for surface level, the direction being parallel to round in surface level is X-axis coordinate, and be Y-axis coordinate perpendicular to the direction of X-axis in surface level, the direction perpendicular to surface level is Z axis coordinate;
Each described cubic plane layer and plane-parallel are the first cubic plane layer D with distance surface level cubic plane layer farthest
1, remaining N-1 cubic plane layer is followed successively by the second cubic plane layer D
2, the 3rd cubic plane layer D
3..., N cubic plane layer D
n;
The negative electrode pin of each LED diode comprises first paragraph and second segment, and first paragraph and second segment are mutually vertical, the plane at first paragraph and second segment place and plane-parallel;
The anode pin of LED diode comprises the 3rd section and the 4th section, and the 3rd section mutually vertical with the 4th section, and the 3rd section and first paragraph, second segment are at same plane, and the 4th section perpendicular to surface level;
Each LED diode is according to the aspect at its place and its position LED diode A (I in specific layer, P, Q) indicate, wherein, I represents the cubic plane layer at this LED diode place, and P represents the row of LED diode in the layer of cubic plane, Q represents the row of LED diode in the layer of cubic plane, and I=1,2,3 ..., N-1, N, P=1,2,3 ..., N-1, N, Q=1,2,3 ..., N-1, N;
As Q< N, the second segment of any LED diode A (I, P, Q) and the second segment of LED diode A (I, P, Q+1) connect;
The second segment of any LED diode A (I, P, N) and wire C
sconnect, s=I;
As I < N, the 4th section of any LED diode A (I, P, Q) connects with the 4th section of LED diode A (I+1, P, Q);
The 4th section of any LED diode A (N, P, Q) with meet hole i
kmconnect, and k=p, m=Q;
Described control gear is provided with power supply VCC, chip U1, latch units and switch amplifying unit;
The model of described chip U1 is AT89C51, and described chip U1 is by exclusion P1, P2 expansion;
The pin 1 of described chip U1 is connected with the pin wei1 of exclusion P1, the pin 2 of described chip U1 is connected with the pin wei2 of exclusion P1, the pin 3 of described chip U1 is connected with the pin wei3 of exclusion P1, the pin 4 of described chip U1 is connected with the pin wei4 of exclusion P1, the pin 5 of described chip U1 is connected with the pin wei5 of exclusion P1, the pin 6 of described chip U1 is connected with the pin wei6 of exclusion P1, the pin 2 of described chip U1 is connected with the pin wei7 of exclusion P7, the pin 8 of described chip U1 is connected with the pin wei8 of exclusion P1, the pin 9 of described chip U1 is connected with the pin RST of exclusion P1, the pin 10 of described chip U1 is connected with the pin SZ of exclusion P1, the pin 11 of described chip U1 is connected with the pin L1 of exclusion P1, the pin 12 of described chip U1 is connected with the pin L2 of exclusion P1, the pin 13 of described chip U1 is connected with the pin L3 of exclusion P1, the pin 14 of described chip U1 is connected with the pin S2 of exclusion P1, the pin 15 of described chip U1 is connected with the pin S3 of exclusion P1, the pin 16 of described chip U1 is connected with the pin S4 of exclusion P1, the pin 20 of described chip U1, the pin 1 of exclusion P1 meets GND, the pin 17 of described chip U1 is connected with the pin 17 of exclusion P1, the pin 18 of described chip U1 is connected with the pin 18 of exclusion P1, the pin 19 of described chip U1 is connected with the pin 19 of exclusion P1, and the pin 20 of described chip U1, the pin 20 of exclusion P1 are connected with GND,
The pin 21 of described chip U1 is connected with the pin SE1 of exclusion P2, the pin 22 of described chip U1 is connected with the pin SE2 of exclusion P2, the pin 23 of described chip U1 is connected with the pin SE3 of exclusion P2, the pin 24 of described chip U1 is connected with the pin SE4 of exclusion P2, the pin 25 of described chip U1 is connected with the pin SE5 of exclusion P2, the pin 26 of described chip U1 is connected with the pin SE6 of exclusion P2, the pin 27 of described chip U1 is connected with the pin SE7 of exclusion P2, and the pin 28 of described chip U1 is connected with the pin SE8 of exclusion P2;
The pin 29 of described chip U1 is connected with the pin 12 of exclusion P2, and the pin 40 of the pin 30 of described chip U1, the pin 31 of chip U1, chip U1, the pin 11 of exclusion P2, the pin 10 of exclusion P2, the pin 1 of exclusion P2 meet VCC;
The pin 32 of described chip U1 is connected with the pin NET8 of exclusion P2, the pin 33 of described chip U1 is connected with the pin NET7 of exclusion P2, the pin 34 of described chip U1 is connected with the pin NET6 of exclusion P2, the pin 35 of described chip U1 is connected with the pin NET5 of exclusion P2, the pin 36 of described chip U1 is connected with the pin NET4 of exclusion P2, the pin 37 of described chip U1 is connected with the pin NET3 of exclusion P2, the pin 38 of described chip U1 is connected with the pin NET2 of exclusion P2, and the pin 39 of described chip U1 is connected with the pin NET1 of exclusion P2;
Described latch units be provided with eight structures identical point latch units f, f=1,2,3 ..., N-1, N;
Any one point of latch units f is provided with the chip U2 that model is 74HC573, resistance R1 is to resistance R8, the pin 1 of chip U2, pin 10 ground connection, the pin 11 of chip U2 is connected with the pin SEf of exclusion P2, the pin 2 of chip U2 is connected with the pin NETf of exclusion P2, the pin 3 of chip U2 is connected with the pin NET2 of exclusion P2, the pin 4 of chip U2 is connected with the pin NET3 of exclusion P2, the pin 5 of chip U2 is connected with the pin NET4 of exclusion P2, the pin 6 of chip U2 is connected with the pin NET5 of exclusion P2, the pin 7 of chip U2 is connected with the pin NET6 of exclusion P2, the pin 8 of chip U2 is connected with the pin NET7 of exclusion P2, the pin 9 of chip U2 is connected with the pin NET8 of exclusion P2,
One end of resistance R1 is connected with the pin 19 of chip U1, the other end of resistance R1 and round Pai
kmeet hole i
km(m=1, k=f) connects; One end of resistance R2 is connected with the pin 18 of chip U1, the other end of resistance R2 and round Pai
kmeet hole i
km(m=2, k=f) connects; One end of resistance R3 is connected with the pin 17 of chip U1, the other end of resistance R3 and round Pai
kmeet hole i
km(m=3, k=f) connects; One end of resistance R4 is connected with the pin 16 of chip U1, the other end of resistance R4 and round Pai
kmeet hole i
km(m=4, k=f) connects; One end of resistance R5 is connected with the pin 15 of chip U1, the other end of resistance R5 and round Pai
kmeet hole i
km(m=5, k=f) connects; One end of resistance R6 is connected with the pin 14 of chip U1, the other end of resistance R6 and round Pai
kmeet hole i
km(m=6, k=f) connects; One end of resistance R7 is connected with the pin 13 of chip U1, the other end of resistance R7 and round Pai
kmeet hole i
km(m=7, k=f) connects; One end of resistance R8 is connected with the pin 12 of chip U1, the other end of resistance R8 and round Pai
kmeet hole i
km(m=8, k=f) connects;
Described switch amplifying unit is provided with the identical switch-dividing amplifying unit w of eight structures, w=1,2,3 ..., N-1, N;
Any one switch-dividing amplifying unit w is provided with resistance R0 and triode Q, the grounded emitter of triode Q, and the base stage of triode Q is connected with one end of resistance R0, and the resistance R0 other end is connected with the pin weiw of exclusion P1, the collector of triode Q and wire C
sconnect, s=w.
Preferably, the model of above-mentioned triode Q is SS8050.
Preferably, above-mentioned control gear is also provided with button switch unit, described button switch unit is provided with four foot control T2, four foot control T3 and four foot control T4, the one termination GND of one end of four foot control T2, one end of four foot control T3, four foot control T4, the other end of four foot control T2 is connected with the pin S2 of exclusion P1, the other end of four foot control T3 is connected with the pin S3 of exclusion P1, and the other end of four foot control T4 is connected with the pin S4 of exclusion P1.
Preferably, above-mentioned control gear is also provided with running lamp judging unit, described running lamp judging unit is provided with diode D1, diode D2, diode D3, resistance R001, resistance R002 and resistance R003, the negative pole of diode D1, the negative pole of diode D2, the negative pole of diode D3 is connected with VCC, one end of resistance R001 is connected with the positive pole of diode D1, the other end of resistance R001 is connected with the pin L1 of exclusion, one end of resistance R002 is connected with the positive pole of diode D2, the other end of resistance R002 is connected with the pin L2 of exclusion, one end of resistance R003 is connected with the positive pole of diode D3, the other end of resistance R003 is connected with the pin L3 of exclusion.
Preferably, as Q< N, the second segment of any LED diode A (I, P, Q) and the second segment of LED diode A (I, P, Q+1) are welded to connect.
The second segment of any LED diode A (I, P, N) and wire C
sbe welded to connect, s=I.
Preferably, as I < N, the 4th section of any LED diode A (I, P, Q) is welded to connect with the 4th section of LED diode A (I+1, P, Q).
Preferably, the 4th section of any LED diode A (N, P, Q) with meet hole i
kmbe welded to connect, and k=p, m=Q.
Eight rank LED light cube display screens of the present invention, are provided with light cube and control gear.This eight rank LED light cube display screen directly forms stereoscopic matrix structure by LED light emitting diode, and have when descending in working order that permeability is good, stereoscopic sensation is strong, the feature that display effect is good, has the advantages that control structure is simple, control effects is good.
Accompanying drawing explanation
The present invention is further illustrated to utilize accompanying drawing, but the content in accompanying drawing does not form any limitation of the invention.
Fig. 1 is the structural representation of a kind of eight rank LED light cube display screens of the present invention.
Fig. 2 is the structural representation of the substrate of Fig. 1.
Fig. 3 is the preparation process schematic diagram of a kind of eight rank LED light cube display screens of the present invention.
Fig. 4 is the electrical block diagram of the control chip part of the control gear of the present invention eight rank LED light cube display screen.
Fig. 5 is the electrical block diagram of any one point of latch units f of the control gear of the present invention eight rank LED light cube display screen.
Fig. 6 is the electrical block diagram of any one switch-dividing amplifying unit w of the control gear of the present invention eight rank LED light cube display screen.
Fig. 7 is the electrical block diagram of this real button switch unit part.
Fig. 8 is the electrical block diagram of the control chip part running lamp judging unit of the control gear of the present invention eight rank LED light cube display screen.
In Fig. 1 to Fig. 3, comprising:
Substrate 100,
Round 200, connect hole 210,
Wire 300,
LED diode 400,
First paragraph 410, second segment 420, the 3rd section 430, the 4th section 440.
Embodiment
The invention will be further described with the following Examples.
A kind of eight rank LED light cube display screens, are provided with substrate, are arranged at N number of round Pai of substrate
k(k=1,2,3 ..., N-1, N), N root wire C
s(s=1,2,3 ..., N-1, N) and by N
×n
×the cube structure that N number of LED diode is formed according to matrix arrangement, cube structure is made up of N layer cubic plane layer, and the LED diode structure in every layer of cubic plane layer is that N is capable, N column matrix structural arrangement.It should be noted that, N is natural number, and N is more than or equal to 2.
Round Pai
kbe provided with N number of be arranged in a linear meet hole i
km(m=1,2,3 ..., N-1, N).
To be parallel to the plane at substrate place for surface level, the direction being parallel to round in surface level is X-axis coordinate, and be Y-axis coordinate perpendicular to the direction of X-axis in surface level, the direction perpendicular to surface level is Z axis coordinate.
Each cubic plane layer and plane-parallel are the first cubic plane layer D with distance surface level cubic plane layer farthest
1, remaining N-1 cubic plane layer is followed successively by the second cubic plane layer D
2, the 3rd cubic plane layer D
3..., N cubic plane layer D
n.
The negative electrode pin of each LED diode comprises first paragraph and second segment, and first paragraph and second segment are mutually vertical, the plane at first paragraph and second segment place and plane-parallel.
The anode pin of LED diode comprises the 3rd section and the 4th section, and the 3rd section mutually vertical with the 4th section, and the 3rd section and first paragraph, second segment are at same plane, and the 4th section perpendicular to surface level.
Each LED diode is according to the position LED diode A (I in the aspect at its place and specific layer, P, Q) indicate, wherein, I represents the cubic plane layer at this LED diode place, and P represents the row of LED diode in the layer of cubic plane, Q represents the row of LED diode in the layer of cubic plane, and I=1,2,3 ..., N-1, N, P=1,2,3 ..., N-1, N, Q=1,2,3 ..., N-1, N.
As Q< N, the second segment of any LED diode A (I, P, Q) and the second segment of LED diode A (I, P, Q+1) connect, concrete for being welded to connect.
The second segment of any LED diode A (I, P, N) and wire C
sconnect, s=I, is specially and is welded to connect.
As I < N, the 4th section of any LED diode A (I, P, Q) connects with the 4th section of LED diode A (I+1, P, Q), is specially and is welded to connect.
The 4th section of any LED diode A (N, P, Q) with meet hole i
kmconnect, and k=p, m=Q, be specially and be welded to connect.
For eight rank LED light cube display screens, i.e. N=8, its structural representation as shown in Figure 1, by one piece of substrate, 100,8 round Pai
k(k=1,2,3 ..., 7,8), 8 wire C
s(s=1,2,3 ..., N-1, N) and by 8
×8
×the cube structure that 8 LED diodes 400 are formed according to matrix arrangement, cube structure is made up of 8 layers of cubic plane layer, and LED diode 400 structure in every layer of cubic plane layer is 8 row, 8 column matrix structural arrangement.
Substrate 100 and on round 200 structure as shown in Figure 2.Distance surface level cubic plane layer is farthest the first cubic plane layer D
1, remaining 7 cubic plane layers are arranged in order.
In the layer of same cubic plane, with in a line from left to right the second segment 420 of (with the direction in Fig. 1 for reference) LED diode 400 be welded in the second segment 420 of the adjacent LED diode 400 in right side, the wire 300 that the second segment 420 of the LED diode 400 arranged with a line Nei 8 is corresponding with this row connects.
In the layer of different cubic planes, after with ground floor, to be front, last one deck be, from front to back, 4th section of 440 welding of the LED diode 400 of same a line, same row and the LED diode 400 of the 4th section the 440, eight layer of the adjacent LED diode 400 of one deck below the 4th section 440 is welded in and corresponding connects hole 210.
This eight rank LED light cube display screen, does not need the support arranged especially for placing LED diode 400, all realizes cube matrix structure by the pin of LED diode 400 itself.Its preparation process can operate as follows, as shown in Figure 3:
First, prepare and the negative electrode pin bending of LED diode 400 is formed first paragraph 410 and second segment 420, then in same a line, the second segment 420 of previous LED diode 400 negative electrode pin is welded to connect with the second segment 420 of adjacent LED diode 400 negative electrode pin, the second segment 420 of last LED diode 400 negative electrode pin in a line is connected with corresponding wire 300.
Then the 4th section 440 that the 4th of the LED diode 400 of two-layer for front and back respective column the section 440 is welded the LED diode 400 corresponding with one deck below, the 4th section 440 of last one deck LED diode 400 is welded with the corresponding hole 210 that connects.Complete the preparation of light cube matrix.
It should be noted that, this preparation method is a kind of mode wherein, also first the pin of each LED diode 400 can be converted into first paragraph 410, second segment 420, the structure of the 3rd section 430, the 4th section 440, and then the pin correspondence of each LED diode 400 be carried out welding and realize cube matrix structure.Concrete preparation method does not limit to this.
Each LED diode 400 is controlled by control gear, and control gear realizes the connection with LED diode 400 by wire 300 and round 200.
Accompanying drawing 4 to 8 is circuit diagrams of the control gear part of this eight rank light cube display screen, and control gear is provided with power supply VCC, chip U1, latch units and switch amplifying unit.
The model of chip U1 is AT89C51, and chip U1 is by exclusion P1, P2 expansion.
As shown in Figure 4, the pin 1 of chip U1 is connected with the pin wei1 of exclusion P1, the pin 2 of chip U1 is connected with the pin wei2 of exclusion P1, the pin 3 of chip U1 is connected with the pin wei3 of exclusion P1, the pin 4 of described chip U1 is connected with the pin wei4 of exclusion P1, the pin 5 of chip U1 is connected with the pin wei5 of exclusion P1, the pin 6 of chip U1 is connected with the pin wei6 of exclusion P1, the pin 2 of chip U1 is connected with the pin wei7 of exclusion P7, the pin 8 of chip U1 is connected with the pin wei8 of exclusion P1, the pin 9 of chip U1 is connected with the pin RST of exclusion P1, the pin 10 of chip U1 is connected with the pin SZ of exclusion P1, the pin 11 of described chip U1 is connected with the pin L1 of exclusion P1, the pin 12 of chip U1 is connected with the pin L2 of exclusion P1, the pin 13 of chip U1 is connected with the pin L3 of exclusion P1, the pin 14 of chip U1 is connected with the pin S2 of exclusion P1, the pin 15 of chip U1 is connected with the pin S3 of exclusion P1, the pin 16 of chip U1 is connected with the pin S4 of exclusion P1, the pin 20 of chip U1, the pin 1 of exclusion P1 meets GND, the pin 17 of chip U1 is connected with the pin 17 of exclusion P1, and the pin 18 of chip U1 is connected with the pin 18 of exclusion P1, and the pin 19 of chip U1 is connected with the pin 19 of exclusion P1, and the pin 20 of chip U1, the pin 20 of exclusion P1 are connected with GND.
The pin 21 of chip U1 is connected with the pin SE1 of exclusion P2, the pin 22 of chip U1 is connected with the pin SE2 of exclusion P2, the pin 23 of chip U1 is connected with the pin SE3 of exclusion P2, the pin 24 of chip U1 is connected with the pin SE4 of exclusion P2, the pin 25 of chip U1 is connected with the pin SE5 of exclusion P2, the pin 26 of chip U1 is connected with the pin SE6 of exclusion P2, and the pin 27 of chip U1 is connected with the pin SE7 of exclusion P2, and the pin 28 of chip U1 is connected with the pin SE8 of exclusion P2.
The pin 29 of chip U1 is connected with the pin 12 of exclusion P2, and the pin 40 of the pin 30 of chip U1, the pin 31 of chip U1, chip U1, the pin 11 of exclusion P2, the pin 10 of exclusion P2, the pin 1 of exclusion P2 meet VCC.
The pin 32 of chip U1 is connected with the pin NET8 of exclusion P2, the pin 33 of chip U1 is connected with the pin NET7 of exclusion P2, the pin 34 of chip U1 is connected with the pin NET6 of exclusion P2, the pin 35 of chip U1 is connected with the pin NET5 of exclusion P2, the pin 36 of chip U1 is connected with the pin NET4 of exclusion P2, the pin 37 of chip U1 is connected with the pin NET3 of exclusion P2, and the pin 38 of chip U1 is connected with the pin NET2 of exclusion P2, and the pin 39 of chip U1 is connected with the pin NET1 of exclusion P2.
Latch units be provided with eight structures identical point latch units f, f=1,2,3 ..., N-1, N.
As shown in Figure 5, any one point of latch units f is provided with the chip U2 that model is 74HC573, resistance R1 is to resistance R8, the pin 1 of chip U2, pin 10 ground connection, the pin 11 of chip U2 is connected with the pin SEf of exclusion P2, the pin 2 of chip U2 is connected with the pin NETf of exclusion P2, the pin 3 of chip U2 is connected with the pin NET2 of exclusion P2, the pin 4 of chip U2 is connected with the pin NET3 of exclusion P2, the pin 5 of chip U2 is connected with the pin NET4 of exclusion P2, the pin 6 of chip U2 is connected with the pin NET5 of exclusion P2, the pin 7 of chip U2 is connected with the pin NET6 of exclusion P2, the pin 8 of chip U2 is connected with the pin NET7 of exclusion P2, the pin 9 of chip U2 is connected with the pin NET8 of exclusion P2.
One end of resistance R1 is connected with the pin 19 of chip U1, the other end of resistance R1 and round Pai
kmeet hole i
km(m=1, k=f) connects; One end of resistance R2 is connected with the pin 18 of chip U1, the other end of resistance R2 and round Pai
kmeet hole i
km(m=2, k=f) connects; One end of resistance R3 is connected with the pin 17 of chip U1, the other end of resistance R3 and round Pai
kmeet hole i
km(m=3, k=f) connects; One end of resistance R4 is connected with the pin 16 of chip U1, the other end of resistance R4 and round Pai
kmeet hole i
km(m=4, k=f) connects; One end of resistance R5 is connected with the pin 15 of chip U1, the other end of resistance R5 and round Pai
kmeet hole i
km(m=5, k=f) connects; One end of resistance R6 is connected with the pin 14 of chip U1, the other end of resistance R6 and round Pai
kmeet hole i
km(m=6, k=f) connects; One end of resistance R7 is connected with the pin 13 of chip U1, the other end of resistance R7 and round Pai
kmeet hole i
km(m=7, k=f) connects; One end of resistance R8 is connected with the pin 12 of chip U1, the other end of resistance R8 and round Pai
kmeet hole i
km(m=8, k=f) connects.
Switch amplifying unit is provided with the identical switch-dividing amplifying unit w of eight structures, w=1,2,3 ..., N-1, N.
As shown in Figure 6, any one switch-dividing amplifying unit w is provided with resistance R0 and triode Q, the grounded emitter of triode Q, and the base stage of triode Q is connected with one end of resistance R0, the resistance R0 other end is connected with the pin weiw of exclusion P1, the collector of triode Q and wire C
sconnect, s=w.The model of triode Q is SS8050.
This control gear is also provided with button switch unit, as shown in Figure 7, button switch unit is provided with four foot control T2, four foot control T3 and four foot control T4, the one termination GND of one end of four foot control T2, one end of four foot control T3, four foot control T4, the other end of four foot control T2 is connected with the pin S2 of exclusion P1, the other end of four foot control T3 is connected with the pin S3 of exclusion P1, and the other end of four foot control T4 is connected with the pin S4 of exclusion P1.
Control gear is also provided with running lamp judging unit, as shown in Figure 8, running lamp judging unit is provided with diode D1, diode D2, diode D3, resistance R001, resistance R002 and resistance R003, the negative pole of diode D1, the negative pole of diode D2, the negative pole of diode D3 is connected with VCC, one end of resistance R001 is connected with the positive pole of diode D1, the other end of resistance R001 is connected with the pin L1 of exclusion, one end of resistance R002 is connected with the positive pole of diode D2, the other end of resistance R002 is connected with the pin L2 of exclusion, one end of resistance R003 is connected with the positive pole of diode D3, the other end of resistance R003 is connected with the pin L3 of exclusion.
This eight rank LED light cube display screen, realize building of cube matrix by the pin of LED diode 400 self, entirety does not need to arrange support, has that permeability is good, stereoscopic sensation is strong, the feature that display effect is good time in working order.Its control gear structure is simple, controls result accurate.
Finally should be noted that; above embodiment is only in order to illustrate technical scheme of the present invention but not limiting the scope of the invention; although be explained in detail the present invention with reference to preferred embodiment; those of ordinary skill in the art is to be understood that; can modify to technical scheme of the present invention or equivalent replacement, and not depart from essence and the scope of technical solution of the present invention.
Claims (8)
1. eight rank LED light cube display screens, is characterized in that: be provided with light cube and control gear;
Described smooth cube is provided with substrate, is arranged at N number of round Pai of substrate
k(k=1,2,3 ..., N-1, N), N root wire C
s(s=1,2,3 ..., N-1, N) and by N
×n
×the cube structure that N number of LED diode is formed according to matrix arrangement, described cube structure is made up of N layer cubic plane layer, and the LED diode structure in every layer of cubic plane layer is that N is capable, N column matrix structural arrangement, wherein N=8;
Round Pai
kbe provided with N number of be arranged in a linear meet hole i
km(m=1,2,3 ..., N-1, N);
To be parallel to the plane at substrate place for surface level, the direction being parallel to round in surface level is X-axis coordinate, and be Y-axis coordinate perpendicular to the direction of X-axis in surface level, the direction perpendicular to surface level is Z axis coordinate;
Each described cubic plane layer and plane-parallel are the first cubic plane layer D with distance surface level cubic plane layer farthest
1, remaining N-1 cubic plane layer is followed successively by the second cubic plane layer D
2, the 3rd cubic plane layer D
3..., N cubic plane layer D
n;
The negative electrode pin of each LED diode comprises first paragraph and second segment, and first paragraph and second segment are mutually vertical, the plane at first paragraph and second segment place and plane-parallel;
The anode pin of LED diode comprises the 3rd section and the 4th section, and the 3rd section mutually vertical with the 4th section, and the 3rd section and first paragraph, second segment are at same plane, and the 4th section perpendicular to surface level;
Each LED diode is according to the aspect at its place and its position LED diode A (I in specific layer, P, Q) indicate, wherein, I represents the cubic plane layer at this LED diode place, and P represents the row of LED diode in the layer of cubic plane, Q represents the row of LED diode in the layer of cubic plane, and I=1,2,3 ..., N-1, N, P=1,2,3 ..., N-1, N, Q=1,2,3 ..., N-1, N;
As Q< N, the second segment of any LED diode A (I, P, Q) and the second segment of LED diode A (I, P, Q+1) connect;
The second segment of any LED diode A (I, P, N) and wire C
sconnect, s=I;
As I < N, the 4th section of any LED diode A (I, P, Q) connects with the 4th section of LED diode A (I+1, P, Q);
The 4th section of any LED diode A (N, P, Q) with meet hole i
kmconnect, and k=p, m=Q;
Described control gear is provided with power supply VCC, chip U1, latch units and switch amplifying unit;
The model of described chip U1 is AT89C51, and described chip U1 is by exclusion P1, P2 expansion;
The pin 1 of described chip U1 is connected with the pin wei1 of exclusion P1, the pin 2 of described chip U1 is connected with the pin wei2 of exclusion P1, the pin 3 of described chip U1 is connected with the pin wei3 of exclusion P1, the pin 4 of described chip U1 is connected with the pin wei4 of exclusion P1, the pin 5 of described chip U1 is connected with the pin wei5 of exclusion P1, the pin 6 of described chip U1 is connected with the pin wei6 of exclusion P1, the pin 2 of described chip U1 is connected with the pin wei7 of exclusion P7, the pin 8 of described chip U1 is connected with the pin wei8 of exclusion P1, the pin 9 of described chip U1 is connected with the pin RST of exclusion P1, the pin 10 of described chip U1 is connected with the pin SZ of exclusion P1, the pin 11 of described chip U1 is connected with the pin L1 of exclusion P1, the pin 12 of described chip U1 is connected with the pin L2 of exclusion P1, the pin 13 of described chip U1 is connected with the pin L3 of exclusion P1, the pin 14 of described chip U1 is connected with the pin S2 of exclusion P1, the pin 15 of described chip U1 is connected with the pin S3 of exclusion P1, the pin 16 of described chip U1 is connected with the pin S4 of exclusion P1, the pin 20 of described chip U1, the pin 1 of exclusion P1 meets GND, the pin 17 of described chip U1 is connected with the pin 17 of exclusion P1, the pin 18 of described chip U1 is connected with the pin 18 of exclusion P1, the pin 19 of described chip U1 is connected with the pin 19 of exclusion P1, and the pin 20 of described chip U1, the pin 20 of exclusion P1 are connected with GND,
The pin 21 of described chip U1 is connected with the pin SE1 of exclusion P2, the pin 22 of described chip U1 is connected with the pin SE2 of exclusion P2, the pin 23 of described chip U1 is connected with the pin SE3 of exclusion P2, the pin 24 of described chip U1 is connected with the pin SE4 of exclusion P2, the pin 25 of described chip U1 is connected with the pin SE5 of exclusion P2, the pin 26 of described chip U1 is connected with the pin SE6 of exclusion P2, the pin 27 of described chip U1 is connected with the pin SE7 of exclusion P2, and the pin 28 of described chip U1 is connected with the pin SE8 of exclusion P2;
The pin 29 of described chip U1 is connected with the pin 12 of exclusion P2, and the pin 40 of the pin 30 of described chip U1, the pin 31 of chip U1, chip U1, the pin 11 of exclusion P2, the pin 10 of exclusion P2, the pin 1 of exclusion P2 meet VCC;
The pin 32 of described chip U1 is connected with the pin NET8 of exclusion P2, the pin 33 of described chip U1 is connected with the pin NET7 of exclusion P2, the pin 34 of described chip U1 is connected with the pin NET6 of exclusion P2, the pin 35 of described chip U1 is connected with the pin NET5 of exclusion P2, the pin 36 of described chip U1 is connected with the pin NET4 of exclusion P2, the pin 37 of described chip U1 is connected with the pin NET3 of exclusion P2, the pin 38 of described chip U1 is connected with the pin NET2 of exclusion P2, and the pin 39 of described chip U1 is connected with the pin NET1 of exclusion P2;
Described latch units be provided with eight structures identical point latch units f, f=1,2,3 ..., N-1, N;
Any one point of latch units f is provided with the chip U2 that model is 74HC573, resistance R1 is to resistance R8, the pin 1 of chip U2, pin 10 ground connection, the pin 11 of chip U2 is connected with the pin SEf of exclusion P2, the pin 2 of chip U2 is connected with the pin NETf of exclusion P2, the pin 3 of chip U2 is connected with the pin NET2 of exclusion P2, the pin 4 of chip U2 is connected with the pin NET3 of exclusion P2, the pin 5 of chip U2 is connected with the pin NET4 of exclusion P2, the pin 6 of chip U2 is connected with the pin NET5 of exclusion P2, the pin 7 of chip U2 is connected with the pin NET6 of exclusion P2, the pin 8 of chip U2 is connected with the pin NET7 of exclusion P2, the pin 9 of chip U2 is connected with the pin NET8 of exclusion P2,
One end of resistance R1 is connected with the pin 19 of chip U1, the other end of resistance R1 and round Pai
kmeet hole i
km(m=1, k=f) connects; One end of resistance R2 is connected with the pin 18 of chip U1, the other end of resistance R2 and round Pai
kmeet hole i
km(m=2, k=f) connects; One end of resistance R3 is connected with the pin 17 of chip U1, the other end of resistance R3 and round Pai
kmeet hole i
km(m=3, k=f) connects; One end of resistance R4 is connected with the pin 16 of chip U1, the other end of resistance R4 and round Pai
kmeet hole i
km(m=4, k=f) connects; One end of resistance R5 is connected with the pin 15 of chip U1, the other end of resistance R5 and round Pai
kmeet hole i
km(m=5, k=f) connects; One end of resistance R6 is connected with the pin 14 of chip U1, the other end of resistance R6 and round Pai
kmeet hole i
km(m=6, k=f) connects; One end of resistance R7 is connected with the pin 13 of chip U1, the other end of resistance R7 and round Pai
kmeet hole i
km(m=7, k=f) connects; One end of resistance R8 is connected with the pin 12 of chip U1, the other end of resistance R8 and round Pai
kmeet hole i
km(m=8, k=f) connects;
Described switch amplifying unit is provided with the identical switch-dividing amplifying unit w of eight structures, w=1,2,3 ..., N-1, N;
Any one switch-dividing amplifying unit w is provided with resistance R0 and triode Q, the grounded emitter of triode Q, and the base stage of triode Q is connected with one end of resistance R0, and the resistance R0 other end is connected with the pin weiw of exclusion P1, the collector of triode Q and wire C
sconnect, s=w.
2. eight rank LED light cube display screens according to claim 1, is characterized in that: the model of described triode Q is SS8050.
3. eight rank light cube display screens according to claim 1 and 2, it is characterized in that: described control gear is also provided with button switch unit, described button switch unit is provided with four foot control T2, four foot control T3 and four foot control T4, the one termination GND of one end of four foot control T2, one end of four foot control T3, four foot control T4, the other end of four foot control T2 is connected with the pin S2 of exclusion P1, the other end of four foot control T3 is connected with the pin S3 of exclusion P1, and the other end of four foot control T4 is connected with the pin S4 of exclusion P1.
4. eight rank light cube display screens according to claim 3, it is characterized in that: described control gear is also provided with running lamp judging unit, described running lamp judging unit is provided with diode D1, diode D2, diode D3, resistance R001, resistance R002 and resistance R003, the negative pole of diode D1, the negative pole of diode D2, the negative pole of diode D3 is connected with VCC, one end of resistance R001 is connected with the positive pole of diode D1, the other end of resistance R001 is connected with the pin L1 of exclusion, one end of resistance R002 is connected with the positive pole of diode D2, the other end of resistance R002 is connected with the pin L2 of exclusion, one end of resistance R003 is connected with the positive pole of diode D3, the other end of resistance R003 is connected with the pin L3 of exclusion.
5. eight rank light cube display screens according to claim 1, is characterized in that:
As Q< N, the second segment of any LED diode A (I, P, Q) and the second segment of LED diode A (I, P, Q+1) are welded to connect.
6. eight rank LED light cube display screens according to claim 5, is characterized in that: the second segment of any LED diode A (I, P, N) and wire C
sbe welded to connect, s=I.
7. eight rank LED light cube display screens according to claim 6, is characterized in that: as I < N, any LED diode A (I, P, Q) the 4th section is welded to connect with the 4th section of LED diode A (I+1, P, Q).
8. eight rank LED light cube display screens according to claim 7, is characterized in that: arbitrarily the 4th section of LED diode A (N, P, Q) with meet hole i
kmbe welded to connect, and k=p, m=Q.
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