CN104539886A - Infrared digital image acquisition and transmission system and method based on optical fiber communication - Google Patents

Abstract

The invention discloses an infrared digital image acquisition and transmission system and method based on optical fiber communication. It is used for remote acquisition, transmission and real-time display of digital images generated by infrared imaging detection equipment. The method includes: the sending end detects the infrared digital image received from the LVDS interface and packs it; the receiving end cuts the unpacked image data according to the acquisition window, and then the data enters the FPGA built-in FIFO buffer and external SDRAM. Large-capacity FIFO buffer area, and then the data enters the host computer through the USB interface and displays it in real time. The present invention has the advantages of: the large-capacity FIFO buffer area formed by the image acquisition window, FPGA built-in FIFO buffer and external SDRAM is adopted, the transmission of useless image data is reduced, the data transmission efficiency is improved, and only one piece of SDRAM is used for buffering , simplifying the circuit structure.

Description

Infrared digital image acquisition and transmission system and method based on optical fiber communication

Technical field:

The invention relates to the transmission and display of infrared digital images, in particular to a system and method for collecting and transmitting infrared digital images based on optical fiber communication. It is mainly used for remote acquisition, transmission and real-time display of digital images generated by infrared imaging detection equipment.

Background technique:

Infrared imaging detectors convert infrared radiation into electrical signals, which are then analog-to-digital converted and preprocessed into infrared digital images. Usually infrared imaging detectors need to have real-time detection capabilities in omnidirectional airspace, so infrared detectors need to rotate 360 degrees, and the data acquisition and receiving devices are fixed bodies, so it is necessary to collect the data generated on the rotating body in real time with high speed and high reliability. transferred to the fixed body. However, the implementation method of brushes and conductive rings initially adopted will introduce a lot of signal noise, which is not suitable for transmitting high-speed data signals.

In the past, the cache design of data acquisition system mostly used ping-pong cache, which required two SDRAMs, which virtually increased the volume and complexity of the acquisition and transmission system equipment. At the same time, the previous data acquisition systems mostly used PCI bus to connect with the host computer. But it does not support hot plugging, and it is not conducive to making it into a portable device, and its application popularity is far less than that of a USB interface.

Therefore, it is very necessary to design a high-speed, high-reliability, portable infrared digital image acquisition system and transmission. The use of optical fiber to transmit data between the rotating body and the fixed body can avoid introducing signal noise, and at the same time, using a piece of SDRAM to simulate a large-capacity FIFO and connecting to the host computer with a USB interface can simplify the circuit structure.

Invention content:

The purpose of the present invention is to propose an infrared digital image acquisition and transmission system and method based on optical fiber communication, to realize high-speed, high-reliability transmission, processing and display of infrared digital images, and to realize not only simple circuit structure but also Targets that require high-speed, reliable transmission of data.

To achieve the above purpose, the hardware platform used in the present invention mainly includes: a host, an optical fiber receiving end and an optical fiber transmitting end.

Each hardware part needs to meet: the host is a computer with a USB2.0 interface. The optical fiber receiving end includes a FPGA, a USB2.0 controller chip, a SDRAM, an optical fiber receiving module and peripheral circuits; wherein, the FPGA has a block memory module; the USB2.0 controller chip has A USB2.0 interface connected to the host, a slave device FIFO interface connected to external devices, and two IO pins that can set the direction of input and output; the SDRAM has a storage capacity of 8M bytes and an 8-bit data bus; the The optical fiber receiving module is an optical fiber receiving circuit module composed of an optical fiber connector and a serial-to-parallel conversion chip; the USB2.0 controller chip, SDRAM and optical fiber receiving module are all directly connected to the FPGA. The optical fiber sending end includes a piece of FPGA, an optical fiber sending module and a peripheral circuit interface; wherein, the FPGA has a block memory module; the optical fiber sending module is an optical fiber connector and a parallel-serial conversion chip. Sending circuit module; the peripheral circuit interface described is an LVDS interface; the optical fiber sending module and the peripheral circuit interface are all directly connected to the FPGA;

The connection relationship of each hardware composition is: the host and the optical fiber receiving end are connected through a USB2.0 transmission cable; the optical fiber receiving end and the optical fiber transmitting end are connected through an optical fiber; the optical fiber transmitting end and the infrared detector are connected through an LVDS interface.

The concrete implementation flow process of the present invention is as follows:

Step 1: The FPGA at the optical fiber transmitting end configures the clock of the optical fiber transmitting module, and packs the detected image data into the built-in FIFO buffer;

Step 2: FPGA at the optical fiber sending end reads data from the built-in FIFO buffer and sends it through the optical fiber sending module;

Step 3: FPGA at the fiber receiving end configures the clock of the fiber receiving module, receives fiber data and detects its image frame header;

Step 4: According to the acquisition window command, the received image data is cropped and stored in the built-in input FIFO buffer;

Step 5: The SDRAM control unit determines the read and write operations to SDRAM according to the priority algorithm rotation mechanism, and continuously reads and writes the data in the built-in input FIFO buffer to SDRAM in sequence, or reads and writes the data in SDRAM in sequence into the built-in output FIFO buffer, so that SDRAM, built-in input FIFO buffer and output FIFO buffer are combined into a large-capacity FIFO;

Step 6: The image data sending module reads the data in the built-in output FIFO buffer and writes it into the slave device FIFO of the USB2.0 controller chip;

Step 7: Configure the USB2.0 control chip as a slave device FIFO and control transmission mode through firmware program design, establish a DMA transmission channel and simultaneously send the control command sent by the host to the FPGA of the optical fiber receiving end through the IO port analog IIC protocol;

Step 8: The host reads the data in the slave device FIFO of the USB2.0 controller chip through the USB2.0 interface, and can send control commands such as the acquisition window through the USB2.0 interface;

Step 9: The IIC slave device interface module in the FPGA of the optical fiber receiving end receives the control command sent by the USB2.0 controller chip according to the IIC protocol, and stores it in the command register.

The specific steps of the priority algorithm rotation mechanism described in step 5 are as follows:

(5-1): Initialization has high priority for SDRAM writing;

(5-2): Check whether reading or writing SDRAM is completed, and then go to (5-3);

(5-3): If the SDRAM has more than 127 bytes of capacity and there are more than 127 bytes in the input FIFO buffer, then go to (5-4), otherwise go to (5-6);

(5-4): If writing to SDRAM has a high priority or the output FIFO buffer has a capacity of less than 128 bytes, then go to (5-5), otherwise go to (5-6);

(5-5): Write operation to SDRAM, read SDRAM after completion with high priority and go to (5-2);

(5-6): If the SDRAM has more than 127 bytes and the output FIFO buffer has more than 127 byte capacity, then go to (5-7), otherwise go to (5-2);

(5-7): If reading SDRAM has a high priority or the input FIFO buffer has less than 128 bytes, then go to (5-8), otherwise go to (5-2);

(5-8): Read operation to SDRAM, write to SDRAM after completion has high priority and go to (5-2).

Notable features of the present invention are as follows:

(1) Small size and strong portability. The entire optical fiber receiving end is concentrated on one board. Since only one piece of SDRAM is used and the computer connection end uses a USB interface, the volume and weight of the system are greatly reduced.

(2) Due to the use of the image acquisition window, when the image generation rate exceeds the transmission rate of the acquisition system, only meaningful image data can be transmitted by setting the acquisition window, which improves the transmission rate of the acquisition system.

(3) Adopt the scheme of module division, divide the design of optical fiber sending board into image receiving, cache module and image sending module according to the data flow direction, and divide the design of optical fiber receiving board into frame header detection, image acquisition in the window and large-capacity FIFO, etc. , clear and easy to program.

Description of drawings

Fig. 1 is a system block diagram of an infrared digital image acquisition and transmission system and method based on optical fiber communication.

Fig. 2 is a flowchart of the infrared digital image acquisition and transmission system and method based on optical fiber communication.

Detailed ways:

The specific embodiments of the present invention will be further described below according to the accompanying drawings.

Fig. 1 is a system block diagram of an infrared digital image acquisition and transmission system and method based on optical fiber communication.

The hardware platform adopted in the present invention is: a host computer, a USB2.0 control chip, two FPGAs, a SDRAM, an optical fiber receiving module, an optical fiber sending module and peripheral interfaces.

The host has a USB2.0 interface, and is installed with a driver program for an infrared digital image acquisition and transmission system based on optical fiber communication.

The USB2.0 control chip is selected from Cypress's CY7C68013. This chip conforms to the USB2.0 standard, and its maximum operating frequency is 48MHz. It has more than two common input and output pins that can simulate the IIC protocol. It can be configured as a slave device FIFO and control transmission mode, so that data can be transferred at high speed It is reliably transmitted to the host for display through CY7C68013, and the measured maximum transmission rate is 23Mbyte/s.

Said FPGA chip, the optical fiber transmitting end and the optical fiber receiving end all select the XC6SLX9-TQG144 of Xilinx Spartan-6 series, the FPGA of this type has abundant logic resource and clock management resource, can be used for constructing the internal buffer zone, in order to realize Data cache, and combined with SDRAM to form a large-capacity FIFO.

The SDRAM chip selected is Micron's MT48LC8M8A2-75. The total capacity of this type of SDRAM is 8M bytes, and the read/write rate can reach up to 133Mbyte/s. The rate still exceeds the highest measured rate of USB2.0, which can provide buffer for high-speed data transmission without reducing the transfer rate.

The optical fiber receiving module includes a fiber optic connector HFBR-5208AMZ and a serial-to-parallel conversion chip MAX9218. The FPGA at the fiber receiving end controls the MAX9218 to receive fiber data through the internal frame header detection module.

The optical fiber transmission module includes a fiber optic connector HFBR-5208AMZ and a parallel-to-serial conversion chip MAX9217. The optical fiber transmission terminal FPGA controls the MAX9217 to send optical fiber data through the internal optical fiber transmission control module. The maximum rate of the optical fiber transmission and reception modules is 70Mbyte /s, exceeding the measured rate of USB2.0.

The LVDS interface is directly connected to 3 pairs of differential I/O pins of the FPGA at the optical fiber transmitting end as differential input. Use the pin type DB9 socket as the connector.

Fig. 2 is a flowchart of the infrared digital image acquisition and transmission system and method based on optical fiber communication.

After the optical fiber sending and receiving module clocks are configured, the FPGA at the optical fiber sending end continuously detects the image data received from the LVDS interface, and after packing the image data with a frame header, the image data is sent out from the optical fiber by controlling the optical fiber sending module.

The FPGA at the optical fiber receiving end continuously detects the image data received by the optical fiber receiving module, and cuts the image according to the acquisition window command sent by the host. At the same time, in order to ensure the panoramic view, the cropped image stream is inserted into the uncropped image at a fixed length. The insertion frequency is determined by Acquisition window command parameter control. Then inject the image data plus the frame header into the large-capacity FIFO composed of FPGA built-in FIFO cache and SDRAM. The large-capacity FIFO is 16-bit data written to match the number of bits of the data bus of the optical fiber receiving module, and 8-bit data The number of bits read and written to the USB2.0 control chip slave device FIFO matches. At the same time, the image data sending module controls to continuously write the image data in the large-capacity FIFO into the FIFO of the slave device of the USB2.0 control chip.

The SDRAM control unit in the FPGA of the optical fiber receiving end controls the read and write operations of the input FIFO buffer, output FIFO buffer, and SDRAM chip through the read or write SDRAM operation arbitrated by the priority algorithm rotation mechanism. The priority algorithm rotation mechanism fully considers that the optical fiber transmission rate is not controlled by the optical fiber receiving end, but the USB2.0 transmission rate will be affected by it, and in order to give full play to the buffering effect of SDRAM, the write SDRAM operation is always given priority, that is, first judge whether to write SDRAM Satisfy the condition, so as to ensure that the data in the input FIFO buffer will not exceed its capacity. In this way, the four modules of SDRAM control unit, input FIFO buffer, output FIFO buffer and SDRAM chip are combined into a large-capacity buffer. The timing is the same, so the combination of these four modules can be operated as a large capacity FIFO.

The USB2.0 control chip is configured as a slave device FIFO and controls the transmission mode. After the DMA transmission channel is established, the FPGA can continuously write image data to its slave device FIFO, and the host can continuously read the data from the slave device FIFO into the host and send show.

The acquisition window command is sent by the host to the USB2.0 control chip through the control endpoint of the USB2.0 control chip, and then transmitted to the FPGA of the optical fiber receiving end through the IIC protocol and stored in its command register module. The two ordinary IO pins of the USB2.0 control chip are connected to the two IO pins of the FPGA at the fiber receiving end, and the IIC protocol is simulated through the IO pins. The USB2.0 control chip is used as the master device of the IIC, and the FPGA at the fiber receiving end is used as the IIC from the device.

Claims (3)

1., based on infrared digital image collection and the transmission system of optical fiber communication, it comprises main frame, optical fiber receiving terminal and optical fiber transmitting terminal, it is characterized in that:

Described main frame is the computer with USB2.0 interface;

Described optical fiber receiving terminal comprises a slice FPGA, a slice USB2.0 controller chip, an optic fiber transceiver module, a slice SDRAM; Wherein: described FPGA has block memory module; Described USB2.0 controller chip has the USB2.0 interface of a connection main frame, the IO pin that can arrange input and output direction from device fifo interface and two of a connection external equipment; Described SDRAM has 8M bytes store capacity and 8 bit data bus; Described optic fiber transceiver module is the optical receiving circuit module of an optical fiber connector and a slice serioparallel exchange chip composition; USB2.0 controller chip, SDRAM are directly connected with FPGA with optic fiber transceiver module is equal;

Described optical fiber transmitting terminal comprises a slice FPGA, an optical fiber sending module and peripheral circuit interface; Wherein, described FPGA has block memory module; Described optical fiber sending module is the optical fiber transtation mission circuit module of an optical fiber connector and a slice parallel-serial conversion chip composition; Described peripheral circuit interface is LVDS interface; Optical fiber sending module is all directly connected with FPGA with peripheral circuit interface;

Main frame is connected by USB2.0 transmission cable with optical fiber receiving terminal; Optical fiber receiving terminal and optical fiber transmitting terminal pass through Fiber connection; Optical fiber transmitting terminal is connected by LVDS interface with Infrared Detectors.

2., based on the method based on the infrared digital image collection of optical fiber communication and the infrared digital image collection of transmission system and transmission according to claim 1, it is characterized in that comprising the following steps:

Step 1: optical fiber transmitting terminal FPGA configures optical fiber sending module clock, and stored in built-in FIFO buffer memory after the view data detected is packed;

Step 2: optical fiber transmitting terminal FPGA is read data and sent by optical fiber sending module from built-in FIFO buffer memory;

Step 3: optical fiber receiving terminal FPGA configures optic fiber transceiver module clock, receives fiber data and detects its image frame head;

Step 4: according to acquisition window order, by after the view data cutting that receives stored in built-in input FIFO buffer memory;

Step 5:SDRAM control unit determines the read-write operation to SDRAM according to priority algorithm rotation mechanism, constantly data in built-in input FIFO buffer memory are read successively and are written in SDRAM, or data in SDRAM read successively and is written in built-in output FIFO buffer memory, making SDRAM and the built-in FIFO of input buffer memory and export FIFO buffer memory to be combined into a high-capacity FIFO;

Step 6: view data sending module read data in built-in output FIFO buffer memory and be written to USB2.0 controller chip from device FIFO;

Step 7: be configured to from device FIFO, controls transfer pattern by USB2.0 control chip by Design of Firmware, sets up a DMA transmission channel and the control command that main frame sends can be issued optical fiber receiving terminal FPGA by I/O port Simulation with I IC protocol mode simultaneously;

Step 8: main frame reads the data from device FIFO of USB2.0 controller chip by USB2.0 interface, and send the control commands such as acquisition window by USB2.0 interface;

Step 9: the IIC in optical fiber receiving terminal FPGA, from device interface module, according to IIC agreement, receives the control command that USB2.0 controller chip sends, and by it stored in command register.

3. according to claim 2 a kind of based on the infrared digital image collection of the infrared digital image acquiring and transmission system based on optical fiber communication according to claim 1 and the method for transmission, it is characterized in that: priority algorithm rotation mechanism concrete steps described are in steps of 5 as follows:

(5-1): initialization is write SDRAM has high priority;

(5-2): check and read or write SDRAM whether to complete, complete and forward to (5-3);

(5-3): have more than 127 bytes if SDRAM has more than 127 byte capacities and inputs in FIFO buffer memory, then forward to (5-4), otherwise forward to (5-6);

(5-4): there is high priority or export FIFO and be cached with if write SDRAM and be less than 128 byte capacities, then forward to (5-5), otherwise forward to (5-6);

(5-5): carry out write operation to SDRAM, complete the rearmounted SDRAM of reading there is high priority and forward to (5-2);

(5-6): be cached with more than 127 byte capacities if SDRAM has more than 127 bytes and exports FIFO, then forward to (5-7), otherwise forward to (5-2);

(5-7): if read SDRAM to there is high priority or input FIFO is cached with and is less than 128 bytes, then forward to (5-8), otherwise forward to (5-2);

(5-8): carry out read operation to SDRAM, complete the rearmounted SDRAM of writing there is high priority and forward to (5-2).