CN109284243A - FPGA communication control unit and method based on USB - Google Patents
FPGA communication control unit and method based on USB Download PDFInfo
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- CN109284243A CN109284243A CN201811392968.8A CN201811392968A CN109284243A CN 109284243 A CN109284243 A CN 109284243A CN 201811392968 A CN201811392968 A CN 201811392968A CN 109284243 A CN109284243 A CN 109284243A
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- 238000004891 communication Methods 0.000 title claims abstract description 20
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- 238000003860 storage Methods 0.000 claims abstract description 75
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- 230000004044 response Effects 0.000 claims description 73
- 238000012797 qualification Methods 0.000 claims description 13
- 238000006243 chemical reaction Methods 0.000 claims description 10
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- 230000005540 biological transmission Effects 0.000 description 31
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/366—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a centralised polling arbiter
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
Abstract
This application provides a kind of FPGA communication control unit based on USB, including poll arbitration modules, it include controller and multiple buffer storage in poll arbitration modules, controller is connected with preset sending endpoint in multiple buffer storage and USB chip and receiving endpoint, state for each endpoint in the state according to multiple buffer storage and USB chip, dispatch the upload and/or downloading of the information in multiple buffer storage, realize that the timesharing for the bandwidth between FPGA and USB chip utilizes, to improve the utilization rate of bandwidth.
Description
Technical field
This application involves electronic information field more particularly to a kind of FPGA communication control units and method based on USB.
Background technique
Fig. 1 is that field programmable gate array (Field-Programmable Gate Array, FPGA) passes through general serial
The schematic diagram that bus (Universal Serial Bus, USB) chip is communicated with host computer.Wherein, USB mould is provided in PFGA
Block, USB module transmit the data obtained from data-source device, such as ultrasound image number to USB chip by USB physical layer interface
According to.And host computer is issued control signal to FPGA and receives FPGA and believed for controlling the response of signal by other transmission channels
Number.
Based on above-mentioned transmission mode, in the case where data source does not generate data, do not counted between FPGA and USB chip
According to transmission, therefore, bandwidth between the two is in idle state, it is seen then that the bandwidth of communication mode of the existing FPGA based on USB
Utilization rate is not high.
Summary of the invention
This application provides a kind of FPGA communication control unit and method based on USB, it is therefore intended that solve how to improve
The problem of bandwidth availability ratio based on usb communication.
To achieve the goals above, this application provides following technical schemes:
A kind of FPGA communication control unit based on USB is arranged in FPGA, and the FPGA and USB chip communication are described
Device includes:
Poll arbitration modules；
It include controller and multiple buffer storage in the poll arbitration modules；
Preset sending endpoint and reception in the controller and the multiple buffer storage and the USB chip
Endpoint is connected, for the state of each endpoint in the state according to the multiple buffer storage and the USB chip, scheduling
The upload and/or downloading of information in the multiple buffer storage.
Optionally, the multiple buffer storage includes:
Downloading control signal buffer memory uploads response signal buffer storage and uploads Data Buffer Memory；
The downloading control signal buffer memory is sent by the control signal that the controller connects the USB chip
Endpoint, for caching the controller from the received control signal of the USB chip；
The response signal buffer storage that uploads is received by the response signal that the controller connects the USB chip
Endpoint, for caching the FPGA to be sent to the USB chip by the controller for the sound of the control signal
Induction signal；
The data receiver endpoint for uploading Data Buffer Memory and connecting the USB chip by the controller, is used
In caching the data in the FPGA to be sent to the USB chip by the controller.
Optionally, the poll arbitration modules further include:
It is connected with the controller, and register corresponding with the upload Data Buffer Memory；
The register is for storing by the marker of the controller assignment, the table when the marker is the first numerical value
Show: there are the data not passed in the corresponding upload Data Buffer Memory of the register.
Optionally, the quantity for uploading Data Buffer Memory is multiple；
Multiple upload Data Buffer Memories pass through the data receiver endpoint phase of the controller and the USB chip respectively
Even, wherein the controller is used to successively upload in the multiple upload Data Buffer Memory according to preset byte orderings
Data to the data receiver endpoint.
Optionally, described device further include:
Cache module；
It include control signal buffer memory, response signal buffer storage and data buffer-stored in the cache module
Device；
The control signal buffer memory is connected with downloading control signal buffer memory, is used for and the downloading
Control the signal buffer memory interaction control signal；
The response signal buffer storage is connected with the upload response signal buffer storage, is used for the upload
The response signal buffer storage interaction response signal；
The Data Buffer Memory is connected with the upload Data Buffer Memory, for slow with the upload data being connected
Rush memory interaction data.
Optionally, in the case where the quantity for uploading data buffer memory is multiple, the data buffering storage
Device is identical as the upload data buffer memory quantity, for store the Data Buffer Memories of same type data with
The upload Data Buffer Memory is corresponding to be connected.
Optionally, described device further include:
Parameter decoding module is connected, for receiving the parsing module with the parsing module in the PFGA by bus
The analytic signal of transmission, wherein the parsing module is connected with the control signal buffer memory, for by receiving and solving
The control signal in the control signal buffer memory is analysed, the analytic signal is obtained；
Cross clock domain conversion module is connected with the parameter decoding module and the poll arbitration modules, and being used for will be described
After the clock frequency of analytic signal is converted to local clock frequency, according to the analytic signal after conversion, the poll arbitration is accessed
Register in module.
A kind of FPGA communication control method based on USB, the FPGA are communicated by USB chip with host computer, the side
Method includes being executed with random order:
In the case where meeting downloading control signal conditioning, by the control of the control signal sending end in the USB chip
Signal downloads in the control signal buffer memory of the downloading in the FPGA, until meeting downloading control signal stop condition；
Wherein, it is not the empty and described downloading control signal buffer that the downloading control signal conditioning, which includes: the control signal sending end,
Memory is not full；The downloading control signal stop condition includes: that the control signal sending end is the empty or described downloading
Control signal buffer memory is that the full or described control signal is transmitted；
It, will be in the upload response signal buffer storage of the FPGA in the case where meeting upload response signal condition
Response signal uploads to the response signal receiving end of the USB chip, uploads response signal stop condition until meeting；Wherein,
The upload response signal condition includes: that the response signal receiving end in the USB chip is not upper in the full and described FPGA
It is not empty for passing response signal buffer storage；The upload response signal stop condition includes: that the response signal receiving end is
The full or described upload response signal buffer storage is that the empty or described response signal is transmitted；
In the case where meeting upload data qualification, the data of the FPGA uploaded in Data Buffer Memory are uploaded
To the data receiver of the USB chip, data stop condition is uploaded until meeting；Wherein, the upload data qualification includes:
Data receiver in the USB chip is not that the upload Data Buffer Memory in the full and described FPGA is not empty；On described
It is full or described the uploads Data Buffer Memory is sky or described that pass data stop condition, which include: the data receiver,
Data are transmitted.
Optionally, the data include a plurality of types of data being stored in different upload Data Buffer Memories；
It is described meet upload data qualification in the case where, by the FPGA upload Data Buffer Memory in data
The data receiver of the USB chip is uploaded to, uploads data stop condition until meeting, comprising:
According to arbitrary byte orderings, judge whether all types of data meet the upload data qualification, it will be described in satisfaction
The data for uploading the type of data qualification are uploaded to the data receiver, until meeting the upload data stop condition.
Optionally, further includes:
During uploading the data, meet the feelings for uploading data stop condition and stopping uploading the data
Under condition, if data have not passed, records data and do not passed.
Optionally, described in the case where meeting upload data qualification, by the upload Data Buffer Memory of the FPGA
In data upload to the data receiver of the USB chip, upload data stop condition until meeting, before further include:
Upload the data not passed recorded.
FPGA communication control unit described herein based on USB, including poll arbitration modules, in poll arbitration modules
Including controller and multiple buffer storage, preset sending endpoint in controller and multiple buffer storage and USB chip
It is connected with receiving endpoint, for the state of each endpoint in the state according to multiple buffer storage and USB chip, dispatches more
The timesharing benefit for the bandwidth between FPGA and USB chip is realized in the upload and/or downloading of information in a buffer storage
With to improve the utilization rate of bandwidth.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of application for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is the schematic diagram that FPGA passes through that USB chip is communicated with host computer；
Fig. 2 is a kind of structural schematic diagram of the FPGA communication control unit based on USB disclosed in the embodiment of the present application；
Fig. 3 is the flow chart of the FPGA communication control method based on USB disclosed in the embodiment of the present application.
Specific embodiment
FPGA communication control method and device based on USB disclosed in the embodiment of the present application, it is therefore intended that realize FPGA pairs
In the scheduled transmission of different information, bandwidth is made full use of to realize, in the case where transmitting a plurality of types of information, further
, it can also be ensured that the integrality of information.
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of embodiments of the present application, instead of all the embodiments.It is based on
Embodiment in the application, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall in the protection scope of this application.
Fig. 2 is a kind of FPGA communication control unit based on USB disclosed in the embodiment of the present application, comprising: poll arbitrates mould
Block 21 further includes optionally cache module 22, parameter decoding module 23 and cross clock domain conversion module 24.
Wherein, it (includes control signal, sound in information that poll arbitration modules 21, which are used to store the information interacted with USB chip,
Induction signal and data), and realize the scheduling transmitted for information.
Specifically, poll arbitration modules 21 include that downloading controls signal buffer memory 211, upload response signal buffering is deposited
Reservoir 212 uploads Data Buffer Memory 213, controller 214 and register (being not drawn into Fig. 2).
Controller 214 and multiple buffer storage (including 211,212 and 213) difference phase in poll arbitration modules 21
Even, and it is connected with preset sending endpoint in USB chip and receiving endpoint, for according to multiple in poll arbitration modules 21
The state of buffer storage and the state of each endpoint in USB chip, the multiple bufferings dispatched in poll arbitration modules 21 are deposited
The upload and/or downloading of information in reservoir.Wherein, downloading refers to information (the usually control letter for receiving USB chip and sending
Number), upload, which refers to, is sent to USB chip for information (usually response signal and data).
Further, downloading control signal buffer memory 211 connects the control letter in USB chip by controller 214
Number sending endpoint (in Fig. 2, by taking EP2 endpoint as an example).It uploads response signal buffer storage 212 and USB is connected by controller 214
Response signal receiving endpoint in chip (in Fig. 2, by taking EP4 endpoint as an example).It uploads Data Buffer Memory 213 and passes through controller
The data receiver endpoint of 214 connection USB chips (in Fig. 2, by taking EP6 endpoint as an example).
EP2 received control letter of the downloading control signal buffer memory 211 for cache controller 214 from USB chip
Number.Wherein, control signal is the signal for being used to control FPGA that host computer issues.Response signal buffer storage 212 is uploaded to use
In caching FPGA for the response signal of control signal, response signal will be sent to the EP4 of USB chip by controller 214.
The data that Data Buffer Memory 213 is used to cache the EP6 that USB chip is sent in FPGA are uploaded, data will
The EP6 of USB chip is sent to by controller 214.
Further, the quantity of upload Data Buffer Memory 213 can be multiple, be in the type of data to be sent
In the case where multiple, the data of any one type at least have the upload data buffering of the data for storing the type
Memory 213.In Fig. 2, with three kinds of data instances to be uploaded, therefore, three upload Data Buffer Memories 213 are set.Three
A upload Data Buffer Memory 213 is connected by controller 214 with the EP6 of USB chip respectively.Controller 214 can be according to
Preset byte orderings successively upload multiple data uploaded in Data Buffer Memories 213 to EP6.
Each upload Data Buffer Memory is correspondingly arranged register.Register is for storing by 214 assignment of controller
Marker, when marker be the first numerical value (such as 1) when indicate: have not in the corresponding upload Data Buffer Memory of register
The data passed.It indicates when marker is second value (such as 0): not having in the corresponding upload Data Buffer Memory of register
There are the data not passed.
The other modules and hardware device (the i.e. data of data are provided that cache module 22 is used to cache with inside FPGA
Source) interaction information (including control signal, response signal and data in information).
Specifically, including control signal buffer memory 221,222 and of response signal buffer storage in cache module 22
Data Buffer Memory 223.
Wherein, control signal buffer memory 221 is connected with downloading control signal buffer memory 211, is used for and downloading
211 interactive controlling signal of signal buffer memory is controlled, i.e., downloading control signal buffer memory 211 is receiving control signal
Afterwards, FPGA sends control signals to control signal buffer memory 221, and further, FPGA will control signal buffer storage
Control signal in device 221 issues other modules.
Response signal buffer storage 222 is connected with response signal buffer storage 212 is uploaded, for slow with response signal
Rush 222 interaction response signal of memory.I.e. response signal buffer storage 222 receives FPGA and believes for controlling the response of signal
Number (response signal by control signal respond module send) after, FPGA by response signal issue upload response signal buffer-stored
Device 212.
Data Buffer Memory 223 is connected with Data Buffer Memory 213 is uploaded, and is used for and uploads Data Buffer Memory
213 interaction datas.I.e. Data Buffer Memory 223 is from data sources data, and after being filled with, FPGA sends data to upload number
According to buffer storage 213.
Specifically, in the case where it is multiple for uploading the quantity of data buffer memory 213, Data Buffer Memory 223
It is identical as the quantity of data buffer memory 213 is uploaded, and for store the Data Buffer Memories 223 of same type data with
It is corresponding connected to upload Data Buffer Memory 213.
In Fig. 2, data are with ultrasound image data (Img is indicated), the status data of heart rate data (Ecg is indicated) and hardware
For (Inf expression).Control signal indicates that response signal is indicated with status with cmd.Citing based on Fig. 2, cache module 22
The buffer storage of middle storage Img is connected with the buffer storage for storing Img in poll arbitration modules 21, deposits in cache module 22
The buffer storage for storing up cmd is connected with the buffer storage for storing cmd in poll arbitration modules 21, stores in cache module 22
The buffer storage of status is connected with the buffer storage for storing status in poll arbitration modules 21.
In general, including parsing module in PFGA, parsing module is connected with control signal buffer memory 221, for passing through
The control signal in control signal buffer memory 221 is received and parsed through, analytic signal is obtained.
In Fig. 2, parameter decoding module 23 is connected by bus (in Fig. 2, bus indicates bus) with parsing module, for connecing
Receive the analytic signal that parsing module is sent.
Cross clock domain conversion module 24 is connected with parameter decoding module 23 and poll arbitration modules 24, is used for analytic signal
Clock frequency be converted to local clock frequency after, according to conversion after analytic signal, access poll arbitration modules in deposit
Device.It should be noted that the register in poll arbitration modules described here, can include but is not limited in poll arbitration modules
Buffer status register, wherein buffer status register is used for the corresponding status signal for storing each caching, status signal
It is normal or abnormal in the current state for indicating to cache.
For example, the analytic signal instruction that parsing module parsing control signal obtains: obtaining all in poll arbitration modules
The current state of Data Buffer Memory 213 is uploaded, then cross clock domain conversion module 24 converts the clock frequency of analytic signal
After local clock frequency, according to the analytic signal after conversion, the buffer status register in poll arbitration modules 21 is read
Status signal, and by the status signal of reading signal in response, response signal buffer storage 222 is issued by FPGA, is filled with
Afterwards, it is transmitted to and uploads response signal buffer storage 212, then USB chip is sent to by the controller 214 of poll arbitration modules
EP4。
The concrete function of parameter decoding module 23 and cross clock domain conversion module 24 is realized, with the prior art (i.e. FPGA
Based on a kind of technology of data type of USB transmission) it is identical, which is not described herein again other than above-mentioned each module, in Fig. 2, fifo
Indicate queue, USB-reg indicates that poll arbitrates the signal in register used in 21 modules.
Below with FPGA under the control of host computer, data are obtained from hardware device and are issued data by USB chip
For the scene of host computer, the process that controller 214 shown in Fig. 2 executes the FPGA communication control based on USB is carried out detailed
Explanation.
Assuming that FPGA connection cardiotachometer obtains heart rate data, connection Ultrasound Instrument obtains ultrasound image data, and obtains hardware
In the present embodiment, heart rate data, ultrasound image data and state are joined for the state parameter of equipment (including cardiotachometer and Ultrasound Instrument)
Number is referred to as data.
The heart rate data that FPGA will acquire is stored in a buffer storage (referred to as Ecg data in cache module 22
Caching) in, the ultrasound image data that will acquire is stored in another buffer storage (referred to as Img number in cache module 22
According to caching) in, state parameter is stored in another buffer storage in cache module 22, and (referred to as Status data are slow
Deposit) in.
Fig. 3 is the flow chart of the FPGA communication control method based on USB disclosed in the embodiment of the present application, by controller 214
It executes, it is therefore intended that: according to certain polling sequence, scheduled transmission controls signal, response signal and data.Include in Fig. 3 with
Lower step:
S301: judge whether to meet downloading control signal conditioning: judging whether EP2 endpoint is non-empty and downloading control
Whether signal buffer memory 211 is non-full, if so, executing S302, otherwise, executes S304.
S302: the control signal of EP2 endpoint is downloaded in downloading control signal buffer memory 211.
S303: during downloading controls signal, judge whether to meet downloading control signal stop condition: i.e. judgement control
Signal processed transmission whether complete or EP2 endpoint whether be empty or downloading control signal buffer memory 211 whether be it is full,
If the judging result of any one condition is yes, execution S304, otherwise, execution S302.
S304: judge whether to meet upload response signal condition: judging whether EP4 endpoint is non-full and uploads response
Whether signal buffer memory 212 is non-empty, if so, executing S305, otherwise, executes S307.
S305: the response signal uploaded in response signal buffer storage 212 is uploaded into EP4 endpoint.
S306: during uploading response signal, judge whether to meet upload response signal stop condition: i.e. judgement is rung
Whether induction signal transmission is completed or whether EP4 endpoint is full or uploads whether response signal buffer storage 212 is sky,
If the judging result of any one condition is yes, execution S307, otherwise, execution S305.
S307: judging whether there is the data for not completing transmission, if not, S308 is executed, if so, executing S321.
Specifically, can recorde in the case that controller 214 does not complete data transmission in upper primary data transmission procedure
The type of the data of transmission is not completed, controller 214 determines that last time data transmission does not complete according to record.Specifically, record
The mark of the caching of the data of transmission is not completed, it is assumed for example that for storing the slow of ultrasound image data in poll arbitration modules 21
The number deposited is 1, for the caching of storage state data number be 2, the number of caching for storing heart rate data is 3,
Then if ultrasound image data has not passed in last time data transmission procedure, the caching of 214 record storage heart rate data of controller
Number 3.Or as previously mentioned, for each buffer setting register for storing data, if transmitted in a data
In the process, the data in any one caching have not passed, then set 1 for the flag bit in the slow register.Controller 214
The data not passed are determined whether according to the flag bit in the corresponding register of each caching.
S308: judge whether to meet upload data qualification: judging whether EP6 endpoint is non-full and storage ultrasound image
Whether the upload Data Buffer Memory 213 of data is non-empty, if so, executing S309, otherwise, executes S312.
S309: the ultrasound image data in the upload Data Buffer Memory 213 for storing ultrasound image data is uploaded to
EP6 endpoint.
S310: during uploading ultrasound image data, judge whether to meet upload data stop condition: judge
Whether EP6 endpoint is full or whether the caching of storage ultrasound image data is sky, if the judging result of any one condition
It is yes, execution S311, otherwise, execution S309.
S311: judging whether the transmission of this ultrasound image data is completed, if so, executing S312, otherwise, executes S320.
S312: judging whether EP6 endpoint is non-full and whether the caching of storage state data is non-empty, if so, executing
Otherwise S313 executes S316.
S313: the status data in the upload Data Buffer Memory 213 of storage state data is uploaded to EP6 endpoint.
S314: during uploading status data, judge whether EP6 endpoint is that full or status data caching is
No is sky, if the judging result of any one condition is yes, execution S315, otherwise, execution S313.
S315: judging whether this status data transfers is completed, if so, executing S316, otherwise, executes S320.
S316: judging whether EP6 endpoint is whether caching that is non-full and storing heart rate data is non-empty, if so, executing
Otherwise S317 executes S301.
S317: the heart rate data in the upload Data Buffer Memory 213 for storing heart rate data is uploaded to EP6 endpoint.
S318: during uploading heart rate data, judge whether EP6 endpoint is that full or heart rate data caching is
No is sky, if the judging result of any one condition is yes, execution S319, otherwise, execution S317.
S319: judging whether the transmission of this heart rate data is completed, if so, executing S301, otherwise, executes S320.
S320: record does not complete the data of transmission.
The concrete mode of record is as previously mentioned, which is not described herein again.
S321: transmission last time does not complete the data of transmission.
Controller 214 returns after the data for transferring last time unfinished transmission and executes S308, carry out this data biography
It is defeated.
From process shown in Fig. 3 can be seen that poll arbitration modules according to control signal, response signal, the sequence of data,
The state of the endpoint of poll local cache and USB chip carries out the transmission of information in the case where two sides are all satisfied condition, because
This, can take into account the transmission of much information.Further, for a plurality of types of data, also can be used preset sequence into
The transmission of row poll, so, using timesharing in the way of bandwidth, it can be realized the transmission of multiple types of data.With existing one
Kind data are compared using the mode that individual fpga chip transmits, and a PFGA chip can take into account the transmission of a variety of data, i.e.,
Using a plurality of types of data of bandwidth time sharing transmissions for PFGA distribution, the utilization rate of bandwidth can be improved.
Also, polling sequence is arranged with the dimension of the endpoint of USB chip setting, thus it is possible to be compatible with the transmission association of USB
View, hardware compatibility are higher.
In general, the transmission quantity of data (such as ultrasound image data) is larger compared with state parameter, therefore, had in last time
In the case where not passed data, the data that prioritised transmission has not passed, thus it is possible to be further ensured that the integrality of data and correct
Property, without because wheel sequence mechanism leads to loss of data and mistake.
In the present embodiment, the setting principle of above-mentioned Rule of judgment are as follows: the recipient of information is non-full and the sender of information is non-
Therefore sky can either guarantee that information is lost caused by recipient has expired, and can carry out the poll of next information in time,
Improve the efficiency of transmission of information.
It should be noted that if host computer Caton and cause FPGA information to block, information can first store FPGA
It,, therefore, can if host computer will lead to information loss also in Caton state when internal queues are filled in internal queues
Following bandwidth relationship: bandwidth > USB bandwidth > FPGA bandwidth of host computer is arranged.
It should be noted that polling sequence described in process shown in Fig. 3: control signal, response signal and data,
It is merely illustrative, not as the restriction of the application, other preset orders also can be used and be polled.Likewise, ultrasound data figure
The polling sequence of picture, status data and heart rate data, also not as restriction.
It should be noted that in process shown in Fig. 3, the downloading control signal storage uploads response signal storage
Device and upload data storage, are not limited to structure shown in Fig. 2, or existing memory in FPGA, as long as only using
In the data of storage respective type, for example, existing memory in FPGA, can be only used for storage control signal, as
Downloading control signal storage.
If function described in the embodiment of the present application method is realized in the form of SFU software functional unit and as independent production
Product when selling or using, can store in a storage medium readable by a compute device.Based on this understanding, the application is real
The part for applying a part that contributes to existing technology or the technical solution can be embodied in the form of software products,
The software product is stored in a storage medium, including some instructions are used so that a calculating equipment (can be personal meter
Calculation machine, server, mobile computing device or network equipment etc.) execute each embodiment the method for the application whole or portion
Step by step.And storage medium above-mentioned include: USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), with
Machine accesses various Jie that can store program code such as memory (RAM, Random Access Memory), magnetic or disk
Matter.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with it is other
The difference of embodiment, same or similar part may refer to each other between each embodiment.
The foregoing description of the disclosed embodiments makes professional and technical personnel in the field can be realized or use the application.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the application.Therefore, the application
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (11)
1. a kind of FPGA communication control unit based on USB is arranged in FPGA, the FPGA and USB chip communication, feature
It is, described device includes:
Poll arbitration modules；
It include controller and multiple buffer storage in the poll arbitration modules；
Preset sending endpoint and receiving endpoint in the controller and the multiple buffer storage and the USB chip
It is connected, for the state of each endpoint in the state according to the multiple buffer storage and the USB chip, described in scheduling
The upload and/or downloading of information in multiple buffer storage.
2. the apparatus according to claim 1, which is characterized in that the multiple buffer storage includes:
Downloading control signal buffer memory uploads response signal buffer storage and uploads Data Buffer Memory；
The downloading control signal buffer memory connects the control signal sending end of the USB chip by the controller
Point, for caching the controller from the received control signal of the USB chip；
The response signal receiving end for uploading response signal buffer storage and connecting the USB chip by the controller
Point, for caching response of the FPGA to be sent to the USB chip by the controller for the control signal
Signal；
The data receiver endpoint for uploading Data Buffer Memory and connecting the USB chip by the controller, for delaying
Deposit the data in the FPGA to be sent to the USB chip by the controller.
3. the apparatus of claim 2, which is characterized in that the poll arbitration modules further include:
It is connected with the controller, and register corresponding with the upload Data Buffer Memory；
The register is used to store to be indicated by the marker of the controller assignment when the marker is the first numerical value:
There are the data not passed in the corresponding upload Data Buffer Memory of the register.
4. device according to any one of claims 2 to 3, which is characterized in that the number for uploading Data Buffer Memory
Amount is multiple；
Multiple upload Data Buffer Memories pass through the controller respectively and are connected with the data receiver endpoint of the USB chip,
Wherein, the controller is used to successively upload in the multiple upload Data Buffer Memory according to preset byte orderings
Data are to the data receiver endpoint.
5. the apparatus of claim 2, which is characterized in that described device further include:
Cache module；
It include control signal buffer memory, response signal buffer storage and Data Buffer Memory in the cache module；
The control signal buffer memory is connected with downloading control signal buffer memory, for controlling with the downloading
The signal buffer memory interaction control signal；
The response signal buffer storage is connected with the upload response signal buffer storage, for responding to the upload
The signal buffer memory interaction response signal；
The Data Buffer Memory is connected with the upload Data Buffer Memory, for depositing with the upload data buffering being connected
Reservoir interaction data.
6. device according to claim 5, which is characterized in that it is described upload data buffer memory quantity be it is multiple
In the case where, the Data Buffer Memory is identical as the upload data buffer memory quantity, for storing same type
The Data Buffer Memory of data is corresponding with the upload Data Buffer Memory to be connected.
7. device according to claim 5, which is characterized in that described device further include:
Parameter decoding module is connected by bus with the parsing module in the PFGA, is sent for receiving the parsing module
Analytic signal, wherein the parsing module is connected with the control signal buffer memory, for by receiving and parsing through
The control signal in control signal buffer memory is stated, the analytic signal is obtained；
Cross clock domain conversion module is connected with the parameter decoding module and the poll arbitration modules, is used for the parsing
After the clock frequency of signal is converted to local clock frequency, according to the analytic signal after conversion, the poll arbitration modules are accessed
In register.
8. a kind of FPGA communication control method based on USB, the FPGA is communicated by USB chip with host computer, and feature exists
In the method includes being executed with random order:
In the case where meeting downloading control signal conditioning, by the control signal of the control signal sending end in the USB chip
It downloads in the downloading control signal buffer memory in the FPGA, until meeting downloading control signal stop condition；Wherein,
The downloading control signal conditioning includes: that the control signal sending end is not the empty and described downloading control signal buffer memory
It is not full；The downloading control signal stop condition includes: that the control signal sending end is believed for the empty or described downloading control
Number buffer storage is that the full or described control signal is transmitted；
In the case where meeting upload response signal condition, by the response in the upload response signal buffer storage of the FPGA
Signal uploads to the response signal receiving end of the USB chip, uploads response signal stop condition until meeting；Wherein, described
It is not that upload in the full and described FPGA is rung that upload response signal condition, which include: response signal receiving end in the USB chip,
Induction signal buffer storage is not empty；The upload response signal stop condition include: the response signal receiving end be it is full or
Upload response signal buffer storage described in person is that the empty or described response signal is transmitted；
In the case where meeting upload data qualification, the data in the upload Data Buffer Memory of the FPGA are uploaded into institute
The data receiver of USB chip is stated, uploads data stop condition until meeting；Wherein, the upload data qualification includes: described
Data receiver in USB chip is not that the upload Data Buffer Memory in the full and described FPGA is not empty；The upload number
It include: the data receiver according to stop condition be full or described the uploads Data Buffer Memory is sky or the data
It is transmitted.
9. according to the method described in claim 8, it is characterized in that, the data include being stored in different upload data bufferings to deposit
A plurality of types of data in reservoir；
It is described meet upload data qualification in the case where, by the FPGA upload Data Buffer Memory in data upload
To the data receiver of the USB chip, data stop condition is uploaded until meeting, comprising:
According to arbitrary byte orderings, judge whether all types of data meet the upload data qualification, the upload will be met
The data of the type of data qualification are uploaded to the data receiver, until meeting the upload data stop condition.
10. method according to claim 8 or claim 9, which is characterized in that further include:
During uploading the data, meets the upload data stop condition and stop the case where uploading the data
Under, if data have not passed, records data and do not passed.
11. according to the method described in claim 10, it is characterized in that, described in the case where meeting upload data qualification, general
Data in the upload Data Buffer Memory of the FPGA upload to the data receiver of the USB chip, until on meeting
Data stop condition is passed, before further include:
Upload the data not passed recorded.
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