CN104535937A - New energy power integrated test system based on digital simulated conditions - Google Patents
New energy power integrated test system based on digital simulated conditions Download PDFInfo
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- CN104535937A CN104535937A CN201510046788.4A CN201510046788A CN104535937A CN 104535937 A CN104535937 A CN 104535937A CN 201510046788 A CN201510046788 A CN 201510046788A CN 104535937 A CN104535937 A CN 104535937A
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Abstract
The invention discloses a new energy power integrated test system based on digital simulated conditions. The system comprises a tested power platform and a tested engine arranged on the tested power platform, and is characterized by also comprising a single-chip (1), a power analyzer (2) and a measuring and control instrument (4) which are connected with the single-chip (1), an accelerator driver (3) connected with the measuring and control instrument (4), a direct current power supply (5) connected with the measuring and control instrument (4), a motor controller (6) connected with the power analyzer (2), and a concentrator (7) arranged on the tested power platform. The system disclosed by the invention is simple in overall structure, various condition environments can be effectively simulated, and the test precision is high. Meanwhile, a self-developed digital analog drive circuit is adopted, stable performance during operation can be ensured, and the external electromagnetic interference can be effectively reduced.
Description
Technical field
The present invention relates to a kind of integrated test system, specifically refer to a kind of new forms of energy Dynamic Synthesis test macro based on digitized simulation operating mode.
Background technology
At present, All Around The World is all faced with the energy shortage and environment deterioration problem that are on the rise, seeks society, economy and resource, environment and mutually promotes and becoming worldwide trend with the mode of sustainable development developed in harmony.Under this background, new-energy automobile technology is just becoming a large focus in automotive research field.For guaranteeing use safety, all new-energy automobiles all just can must dispatch from the factory through strict working condition simulation test.But, also do not have on the market at present to provide high precision for new-energy automobile completely and to simulate the integrated test system of various working condition.Therefore, a kind of high-precision new forms of energy Dynamic Synthesis test macro simulating various working condition is provided to be the task of top priority.
Summary of the invention
The object of the invention is to overcome the defect of the test macro also not having energy fine test oil electricity hybrid drive system at present on the market, a kind of new forms of energy Dynamic Synthesis test macro based on digitized simulation operating mode is provided.
Object of the present invention is achieved through the following technical solutions: a kind of new forms of energy Dynamic Synthesis test macro based on digitized simulation operating mode, comprise tested power platform, and the tested engine be arranged on tested power platform, also include single-chip microcomputer simultaneously, the power analyzer be connected with single-chip microcomputer and measurement and control instrument, the accelerator drive instrument be connected with measurement and control instrument, the direct supply be connected with measurement and control instrument, the electric machine controller be connected with power analyzer, be arranged on the hub on tested power platform, and the digital simulation driving circuit to be connected with electric machine controller, described measurement and control instrument is connected with hub by CAN, described digital simulation driving circuit is by signal acquisition circuit, the signal processing circuit that is connected with signal acquisition circuit, the transforming circuit be connected with signal processing circuit, and the Hall element H1 be connected with signal acquisition circuit and Hall element H2 forms.
Further, described signal gathering unit is made up of one-level logic Acquisition Circuit and two-level logic Acquisition Circuit, described one-level logic Acquisition Circuit is by not gate IC1, the input end of P pole Sheffer stroke gate IC1 is connected, N pole is in turn through diode D1 that the input end of resistance R2 Sheffer stroke gate IC1 after electric capacity C1 is connected, and form with the resistance R1 that diode D1 is in parallel, described Hall element H1 is then connected with the N pole of diode D1; Described two-level logic Acquisition Circuit is by not gate IC2, the diode D2 that the input end of N pole Sheffer stroke gate IC2 is connected, the input end of P pole Sheffer stroke gate IC2 after electric capacity C2 is connected, and form with the resistance R3 that diode D2 is in parallel, described Hall element H2 is then connected with the P pole of diode D2.
Described signal processing circuit is by driving chip U, the output terminal of input end Sheffer stroke gate IC1 is connected the one stage signal handle link that its output terminal is then connected with EN pin with the VSS pin of driving chip U, and the output terminal of the input end Sheffer stroke gate IC2 second signal handle link that output terminal is then connected with TN pin with the NC pin of driving chip U that is connected forms.
Described one stage signal handle link is by Sheffer stroke gate IC3, Sheffer stroke gate IC4, rejection gate IC5, power amplifier P1, power amplifier P2, be serially connected in the resistance R5 between the end of oppisite phase of power amplifier P1 and output terminal, be serially connected in the electric capacity C4 between the output terminal of rejection gate IC5 and electrode input end, one end is connected with the output terminal of Sheffer stroke gate IC3, the resistance R6 that the other end is then connected with the negative input of Sheffer stroke gate IC4, one end is connected with the negative input of Sheffer stroke gate IC3, the resistance R4 that the other end is connected with the in-phase end of power amplifier P2, and one end is connected with the output terminal of Sheffer stroke gate IC4, the resistance R7 that the other end is connected with the end of oppisite phase of power amplifier P2 forms, the described output terminal of power amplifier P1 is connected with the electrode input end of Sheffer stroke gate IC4, and its end of oppisite phase is also connected with the electrode input end of Sheffer stroke gate IC3, the described negative input of rejection gate IC5 is connected with the output terminal of Sheffer stroke gate IC4, its output terminal is then connected with the EN pin of driving chip U, the output terminal of described power amplifier P2 is then connected with the VSS pin of driving chip U, and the output terminal of the in-phase end of power amplifier P1 then Sheffer stroke gate IC1 is connected.
Described second signal handle link is by Sheffer stroke gate IC6, Sheffer stroke gate IC7, power amplifier P3, the output terminal of positive pole Sheffer stroke gate IC2 is connected, the polar capacitor C3 that negative pole is connected with the in-phase end of power amplifier P3, be serially connected in the resistance R9 between the end of oppisite phase of power amplifier P3 and output terminal, one end is connected with the positive pole of polar capacitor C3, the resistance R10 that the other end is connected with the negative input of Sheffer stroke gate IC7, one end is connected with the negative pole of polar capacitor C3, the resistance R8 that the other end is connected with the negative input of Sheffer stroke gate IC6, P pole is connected with the output terminal of Sheffer stroke gate IC6, the diode D5 that N pole is connected with the NC pin of driving chip U after resistance R11, positive pole is connected with the output terminal of Sheffer stroke gate IC7, the electric capacity C5 that negative pole is connected with the TN pin of driving chip U, P pole is connected with the negative pole of electric capacity C5, the voltage stabilizing diode D4 that N pole is connected with the N pole of diode D5, one end is connected with the output terminal of power amplifier P3, the resistance R12 that the other end is connected with the NC pin of driving chip U, and P pole is connected with the negative pole of electric capacity C5, the voltage stabilizing diode D6 that N pole is connected with the output terminal of power amplifier P3 forms, the electrode input end of described Sheffer stroke gate IC6 is connected with the end of oppisite phase of power amplifier P3, and its output terminal is then also connected with the electrode input end of Sheffer stroke gate IC7.
Described transforming circuit is by triode Q1, transformer T, the diode D3 that P pole is connected with the in-phase end of power amplifier P2, N pole is connected with the base stage of triode Q1 after electric capacity C6, be serially connected in the resistance R13 between the base stage of triode Q1 and emitter, and positive pole is connected with the collector of triode Q1, negative pole electric capacity C7 of ground connection after electric capacity C8 forms; The base stage of this triode Q1 is connected with the CS pin of driving chip U, and the N pole of diode D3 is also connected with the TOFF pin of driving chip U; The Same Name of Ends of the primary coil of transformer T is connected with the tie point of electric capacity C8 with electric capacity C7, its non-same polarity is then connected with the emitter of triode Q1; Meanwhile, the emitter of triode Q1 is also connected with the DRV pin of driving chip U.
For guaranteeing result of use, this driving chip U preferentially adopts QX9910 type integrated chip to realize.
The present invention comparatively prior art compares, and has the following advantages and beneficial effect:
(1) one-piece construction of the present invention is comparatively simple, can not only effectively simulate various work condition environment, and the precision of its test is higher.
(2) present invention employs the digital simulation driving circuit researched and developed voluntarily, stable performance when running can not only be guaranteed, and can also external electromagnetic interference be effectively reduced.
Accompanying drawing explanation
Fig. 1 is one-piece construction schematic diagram of the present invention.
Fig. 2 is digital simulation driving circuit structure schematic diagram of the present invention.
Wherein, the Reference numeral title in above accompanying drawing is respectively:
1-single-chip microcomputer, 2-power analyzer, 3-accelerator drive instrument, 4-measurement and control instrument, 5-direct supply, 6-electric machine controller, 7-hub, 8-digital simulation driving circuit.
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited thereto.
Embodiment
As shown in Figure 1, tested power platform of the present invention, for carrying tested engine, namely needs the new forms of energy carrying out testing to drive engine to need to be fixed on this tested power platform.Simultaneously, the present invention also includes single-chip microcomputer 1, the power analyzer 2 be connected with single-chip microcomputer 1 and measurement and control instrument 4, the accelerator drive instrument 3 be connected with measurement and control instrument 4, the direct supply 5 be connected with measurement and control instrument 4, the electric machine controller 6 be connected with power analyzer 2, the digital simulation driving circuit 8 being arranged on the hub 7 on tested power platform and being connected with electric machine controller 6.During connection, this measurement and control instrument 4 is connected with hub 7 by CAN, to guarantee the transmitting of test data.
Wherein, direct supply 5 adopts 24V programmable DC power supply general on the market at present to realize, and it is for providing working power for the motor portion of tested engine.Accelerator drive instrument 3 provides fuel oil for the fuel engines part for tested engine, and is shown by measurement and control instrument 4 and control its fuel oil output quantity.Electric machine controller 6 is as the control assembly of motor portion, and for controlling the start and stop of motor, power analyzer 2 is then for the output power of test engine.Digital simulation driving circuit 8 acts on electric machine controller 6, and can simulate various work condition environment.
The mechanism of described digital simulation driving circuit 8 as shown in Figure 2, it is by signal acquisition circuit 81, the signal processing circuit 82 that is connected with signal acquisition circuit 81, the transforming circuit 83 be connected with signal processing circuit 82, and the Hall element H1 be connected with signal acquisition circuit 81 and Hall element H2 forms.
Wherein, Hall element H1 and Hall element H2 is arranged on the rotor portion of tested engine, for gathering magnetic induction variable condition during engine rotation.The induced signal that signal gathering unit 81 is transmitted for gathering Hall element H1 and Hall element H2, it is made up of one-level logic Acquisition Circuit and two-level logic Acquisition Circuit.
Described one-level logic Acquisition Circuit is by not gate IC1, the input end of P pole Sheffer stroke gate IC1 is connected, N pole is in turn through diode D1 that the input end of resistance R2 Sheffer stroke gate IC1 after electric capacity C1 is connected, and form with the resistance R1 that diode D1 is in parallel, described Hall element H1 is then connected with the N pole of diode D1.Described two-level logic Acquisition Circuit is by not gate IC2, the diode D2 that the input end of N pole Sheffer stroke gate IC2 is connected, the input end of P pole Sheffer stroke gate IC2 after electric capacity C2 is connected, and form with the resistance R3 that diode D2 is in parallel, described Hall element H2 is then connected with the P pole of diode D2.
Described signal processing circuit 82 is by driving chip U, the output terminal of input end Sheffer stroke gate IC1 is connected the one stage signal handle link that its output terminal is then connected with EN pin with the VSS pin of driving chip U, and the output terminal of the input end Sheffer stroke gate IC2 second signal handle link that output terminal is then connected with TN pin with the NC pin of driving chip U that is connected forms.For guaranteeing result of use, this driving chip U preferentially adopts QX9910 type integrated chip to realize.This driving chip U is built-in with precision comparator, off-time control circuit, the circuit such as constant current driving.
Described one stage signal handle link is by Sheffer stroke gate IC3, Sheffer stroke gate IC4, rejection gate IC5, power amplifier P1, power amplifier P2, be serially connected in the resistance R5 between the end of oppisite phase of power amplifier P1 and output terminal, be serially connected in the electric capacity C4 between the output terminal of rejection gate IC5 and electrode input end, one end is connected with the output terminal of Sheffer stroke gate IC3, the resistance R6 that the other end is then connected with the negative input of Sheffer stroke gate IC4, one end is connected with the negative input of Sheffer stroke gate IC3, the resistance R4 that the other end is connected with the in-phase end of power amplifier P2, and one end is connected with the output terminal of Sheffer stroke gate IC4, the resistance R7 that the other end is connected with the end of oppisite phase of power amplifier P2 forms, the described output terminal of power amplifier P1 is connected with the electrode input end of Sheffer stroke gate IC4, and its end of oppisite phase is also connected with the electrode input end of Sheffer stroke gate IC3, the described negative input of rejection gate IC5 is connected with the output terminal of Sheffer stroke gate IC4, its output terminal is then connected with the EN pin of driving chip U, the output terminal of described power amplifier P2 is then connected with the VSS pin of driving chip U, and the output terminal of the in-phase end of power amplifier P1 then Sheffer stroke gate IC1 is connected.
Described second signal handle link is by Sheffer stroke gate IC6, Sheffer stroke gate IC7, power amplifier P3, the output terminal of positive pole Sheffer stroke gate IC2 is connected, the polar capacitor C3 that negative pole is connected with the in-phase end of power amplifier P3, be serially connected in the resistance R9 between the end of oppisite phase of power amplifier P3 and output terminal, one end is connected with the positive pole of polar capacitor C3, the resistance R10 that the other end is connected with the negative input of Sheffer stroke gate IC7, one end is connected with the negative pole of polar capacitor C3, the resistance R8 that the other end is connected with the negative input of Sheffer stroke gate IC6, P pole is connected with the output terminal of Sheffer stroke gate IC6, the diode D5 that N pole is connected with the NC pin of driving chip U after resistance R11, positive pole is connected with the output terminal of Sheffer stroke gate IC7, the electric capacity C5 that negative pole is connected with the TN pin of driving chip U, P pole is connected with the negative pole of electric capacity C5, the voltage stabilizing diode D4 that N pole is connected with the N pole of diode D5, one end is connected with the output terminal of power amplifier P3, the resistance R12 that the other end is connected with the NC pin of driving chip U, and P pole is connected with the negative pole of electric capacity C5, the voltage stabilizing diode D6 that N pole is connected with the output terminal of power amplifier P3 forms, the electrode input end of described Sheffer stroke gate IC6 is connected with the end of oppisite phase of power amplifier P3, and its output terminal is then also connected with the electrode input end of Sheffer stroke gate IC7.
Described transforming circuit 83 is by triode Q1, transformer T, the diode D3 that P pole is connected with the in-phase end of power amplifier P2, N pole is connected with the base stage of triode Q1 after electric capacity C6, be serially connected in the resistance R13 between the base stage of triode Q1 and emitter, and positive pole is connected with the collector of triode Q1, negative pole electric capacity C7 of ground connection after electric capacity C8 forms; The base stage of this triode Q1 is connected with the CS pin of driving chip U, and the N pole of diode D3 is also connected with the TOFF pin of driving chip U; The Same Name of Ends of the primary coil of transformer T is connected with the tie point of electric capacity C8 with electric capacity C7, its non-same polarity is then connected with the emitter of triode Q1; Meanwhile, the emitter of triode Q1 is also connected with the DRV pin of driving chip U.
During connection, the OUT pin of driving chip U is directly connected with the control end of electric machine controller 6, and the output terminal of transformer T is then connected with the power end of tested engine.
As mentioned above, just the present invention can well be realized.
Claims (7)
1. the new forms of energy Dynamic Synthesis test macro based on digitized simulation operating mode, comprise tested power platform, and the tested engine be arranged on tested power platform, it is characterized in that, also include single-chip microcomputer (1), the power analyzer (2) be connected with single-chip microcomputer (1) and measurement and control instrument (4), the accelerator drive instrument (3) be connected with measurement and control instrument (4), the direct supply (5) be connected with measurement and control instrument (4), the electric machine controller (6) be connected with power analyzer (2), be arranged on the hub (7) on tested power platform, and the digital simulation driving circuit (8) to be connected with electric machine controller (6), described measurement and control instrument (4) is connected with hub (7) by CAN, described digital simulation driving circuit (8) is by signal acquisition circuit (81), the signal processing circuit (82) that is connected with signal acquisition circuit (81), the transforming circuit (83) be connected with signal processing circuit (82), and the Hall element H1 be connected with signal acquisition circuit (81) and Hall element H2 forms.
2. a kind of new forms of energy Dynamic Synthesis test macro based on digitized simulation operating mode according to claim 1, it is characterized in that, described signal gathering unit (81) is made up of one-level logic Acquisition Circuit and two-level logic Acquisition Circuit, described one-level logic Acquisition Circuit is by not gate IC1, the input end of P pole Sheffer stroke gate IC1 is connected, N pole is in turn through diode D1 that the input end of resistance R2 Sheffer stroke gate IC1 after electric capacity C1 is connected, and form with the resistance R1 that diode D1 is in parallel, described Hall element H1 is then connected with the N pole of diode D1; Described two-level logic Acquisition Circuit is by not gate IC2, the diode D2 that the input end of N pole Sheffer stroke gate IC2 is connected, the input end of P pole Sheffer stroke gate IC2 after electric capacity C2 is connected, and form with the resistance R3 that diode D2 is in parallel, described Hall element H2 is then connected with the P pole of diode D2.
3. a kind of new forms of energy Dynamic Synthesis test macro based on digitized simulation operating mode according to claim 2, it is characterized in that, described signal processing circuit (82) is by driving chip U, the output terminal of input end Sheffer stroke gate IC1 is connected the one stage signal handle link that its output terminal is then connected with EN pin with the VSS pin of driving chip U, and the output terminal of the input end Sheffer stroke gate IC2 second signal handle link that output terminal is then connected with TN pin with the NC pin of driving chip U that is connected forms.
4. a kind of new forms of energy Dynamic Synthesis test macro based on digitized simulation operating mode according to claim 3, it is characterized in that, described one stage signal handle link is by Sheffer stroke gate IC3, Sheffer stroke gate IC4, rejection gate IC5, power amplifier P1, power amplifier P2, be serially connected in the resistance R5 between the end of oppisite phase of power amplifier P1 and output terminal, be serially connected in the electric capacity C4 between the output terminal of rejection gate IC5 and electrode input end, one end is connected with the output terminal of Sheffer stroke gate IC3, the resistance R6 that the other end is then connected with the negative input of Sheffer stroke gate IC4, one end is connected with the negative input of Sheffer stroke gate IC3, the resistance R4 that the other end is connected with the in-phase end of power amplifier P2, and one end is connected with the output terminal of Sheffer stroke gate IC4, the resistance R7 that the other end is connected with the end of oppisite phase of power amplifier P2 forms, the described output terminal of power amplifier P1 is connected with the electrode input end of Sheffer stroke gate IC4, and its end of oppisite phase is also connected with the electrode input end of Sheffer stroke gate IC3, the described negative input of rejection gate IC5 is connected with the output terminal of Sheffer stroke gate IC4, its output terminal is then connected with the EN pin of driving chip U, the output terminal of described power amplifier P2 is then connected with the VSS pin of driving chip U, and the output terminal of the in-phase end of power amplifier P1 then Sheffer stroke gate IC1 is connected.
5. a kind of new forms of energy Dynamic Synthesis test macro based on digitized simulation operating mode according to claim 4, it is characterized in that, described second signal handle link is by Sheffer stroke gate IC6, Sheffer stroke gate IC7, power amplifier P3, the output terminal of positive pole Sheffer stroke gate IC2 is connected, the polar capacitor C3 that negative pole is connected with the in-phase end of power amplifier P3, be serially connected in the resistance R9 between the end of oppisite phase of power amplifier P3 and output terminal, one end is connected with the positive pole of polar capacitor C3, the resistance R10 that the other end is connected with the negative input of Sheffer stroke gate IC7, one end is connected with the negative pole of polar capacitor C3, the resistance R8 that the other end is connected with the negative input of Sheffer stroke gate IC6, P pole is connected with the output terminal of Sheffer stroke gate IC6, the diode D5 that N pole is connected with the NC pin of driving chip U after resistance R11, positive pole is connected with the output terminal of Sheffer stroke gate IC7, the electric capacity C5 that negative pole is connected with the TN pin of driving chip U, P pole is connected with the negative pole of electric capacity C5, the voltage stabilizing diode D4 that N pole is connected with the N pole of diode D5, one end is connected with the output terminal of power amplifier P3, the resistance R12 that the other end is connected with the NC pin of driving chip U, and P pole is connected with the negative pole of electric capacity C5, the voltage stabilizing diode D6 that N pole is connected with the output terminal of power amplifier P3 forms, the electrode input end of described Sheffer stroke gate IC6 is connected with the end of oppisite phase of power amplifier P3, and its output terminal is then also connected with the electrode input end of Sheffer stroke gate IC7.
6. a kind of new forms of energy Dynamic Synthesis test macro based on digitized simulation operating mode according to claim 5, it is characterized in that, described transforming circuit (83) is by triode Q1, transformer T, the diode D3 that P pole is connected with the in-phase end of power amplifier P2, N pole is connected with the base stage of triode Q1 after electric capacity C6, be serially connected in the resistance R13 between the base stage of triode Q1 and emitter, and positive pole is connected with the collector of triode Q1, negative pole electric capacity C7 of ground connection after electric capacity C8 forms; The base stage of this triode Q1 is connected with the CS pin of driving chip U, and the N pole of diode D3 is also connected with the TOFF pin of driving chip U; The Same Name of Ends of the primary coil of transformer T is connected with the tie point of electric capacity C8 with electric capacity C7, its non-same polarity is then connected with the emitter of triode Q1; Meanwhile, the emitter of triode Q1 is also connected with the DRV pin of driving chip U.
7. a kind of new forms of energy Dynamic Synthesis test macro based on digitized simulation operating mode according to any one of claim 3 ~ 6, it is characterized in that, described driving chip U is QX9910 type integrated chip.
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Effective date of registration: 20220726 Address after: 610000 No. 1588, Checheng West Fifth Road, Chengdu Economic and Technological Development Zone (Longquanyi District), Sichuan Province Patentee after: SICHUAN CHENGBANG HAORAN MEASUREMENT AND CONTROL TECHNOLOGY CO.,LTD. Address before: 610000 block 3, shuangxiang Road, Shuangliu Park, Chengdu Jiaolong industrial port, Shuangliu County, Chengdu, Sichuan Province Patentee before: Sichuan Chengbang Measurement Control Technology Co.,Ltd. |