CN104520823B - 用于混合存储器管理的方法、系统和设备 - Google Patents

用于混合存储器管理的方法、系统和设备 Download PDF

Info

Publication number
CN104520823B
CN104520823B CN201380041635.XA CN201380041635A CN104520823B CN 104520823 B CN104520823 B CN 104520823B CN 201380041635 A CN201380041635 A CN 201380041635A CN 104520823 B CN104520823 B CN 104520823B
Authority
CN
China
Prior art keywords
memory
physical address
computing device
allocating
hybrid memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201380041635.XA
Other languages
English (en)
Chinese (zh)
Other versions
CN104520823A (zh
Inventor
S·R·科第林格尔
R·拉马斯瓦米
S·亚利尔
A·托兹尼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN104520823A publication Critical patent/CN104520823A/zh
Application granted granted Critical
Publication of CN104520823B publication Critical patent/CN104520823B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/3296Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1027Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/15Use in a specific computing environment
    • G06F2212/151Emulated environment, e.g. virtual machine
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20Employing a main memory using a specific memory technology
    • G06F2212/205Hybrid memory, e.g. using both volatile and non-volatile memory
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65Details of virtual memory and virtual address translation
    • G06F2212/651Multi-level translation tables
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65Details of virtual memory and virtual address translation
    • G06F2212/657Virtual address space management
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
  • Power Sources (AREA)
  • Information Transfer Between Computers (AREA)
CN201380041635.XA 2012-08-07 2013-06-13 用于混合存储器管理的方法、系统和设备 Expired - Fee Related CN104520823B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/568,523 US9047090B2 (en) 2012-08-07 2012-08-07 Methods, systems and devices for hybrid memory management
US13/568,523 2012-08-07
PCT/US2013/045685 WO2014025454A1 (en) 2012-08-07 2013-06-13 Methods, systems and devices for hybrid memory management

Publications (2)

Publication Number Publication Date
CN104520823A CN104520823A (zh) 2015-04-15
CN104520823B true CN104520823B (zh) 2016-05-04

Family

ID=48747725

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201380041635.XA Expired - Fee Related CN104520823B (zh) 2012-08-07 2013-06-13 用于混合存储器管理的方法、系统和设备

Country Status (6)

Country Link
US (1) US9047090B2 (enExample)
EP (1) EP2883146A1 (enExample)
JP (1) JP5916955B2 (enExample)
CN (1) CN104520823B (enExample)
IN (1) IN2015MN00051A (enExample)
WO (1) WO2014025454A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11791326B2 (en) 2021-05-10 2023-10-17 International Business Machines Corporation Memory and logic chip stack with a translator chip

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8515052B2 (en) 2007-12-17 2013-08-20 Wai Wu Parallel signal processing system and method
GB2495959A (en) * 2011-10-26 2013-05-01 Imagination Tech Ltd Multi-threaded memory access processor
US10303618B2 (en) * 2012-09-25 2019-05-28 International Business Machines Corporation Power savings via dynamic page type selection
US9348757B2 (en) 2012-10-08 2016-05-24 International Business Machines Corporation System supporting multiple partitions with differing translation formats
US9355032B2 (en) 2012-10-08 2016-05-31 International Business Machines Corporation Supporting multiple types of guests by a hypervisor
US9280488B2 (en) 2012-10-08 2016-03-08 International Business Machines Corporation Asymmetric co-existent address translation structure formats
US9740624B2 (en) 2012-10-08 2017-08-22 International Business Machines Corporation Selectable address translation mechanisms within a partition
US9355040B2 (en) 2012-10-08 2016-05-31 International Business Machines Corporation Adjunct component to provide full virtualization using paravirtualized hypervisors
US9600419B2 (en) * 2012-10-08 2017-03-21 International Business Machines Corporation Selectable address translation mechanisms
US9448612B2 (en) * 2012-11-12 2016-09-20 International Business Machines Corporation Management to reduce power consumption in virtual memory provided by plurality of different types of memory devices
US10210096B2 (en) * 2013-10-01 2019-02-19 Ampere Computing Llc Multi-stage address translation for a computing device
US10437479B2 (en) 2014-08-19 2019-10-08 Samsung Electronics Co., Ltd. Unified addressing and hierarchical heterogeneous storage and memory
US10282100B2 (en) 2014-08-19 2019-05-07 Samsung Electronics Co., Ltd. Data management scheme in virtualized hyperscale environments
GB2536201B (en) * 2015-03-02 2021-08-18 Advanced Risc Mach Ltd Handling address translation requests
US9547361B2 (en) * 2015-04-29 2017-01-17 Qualcomm Incorporated Methods and apparatuses for memory power reduction
US10157008B2 (en) 2015-04-29 2018-12-18 Qualcomm Incorporated Systems and methods for optimizing memory power consumption in a heterogeneous system memory
US9977730B2 (en) * 2015-05-08 2018-05-22 Dell Products, Lp System and method for optimizing system memory and input/output operations memory
US10007435B2 (en) 2015-05-21 2018-06-26 Micron Technology, Inc. Translation lookaside buffer in memory
JP6212073B2 (ja) * 2015-06-29 2017-10-11 ファナック株式会社 プログラムの内容に応じて格納先を自動選択する機能を備えた数値制御装置
US9690494B2 (en) * 2015-07-21 2017-06-27 Qualcomm Incorporated Managing concurrent access to multiple storage bank domains by multiple interfaces
US10003529B2 (en) 2015-08-04 2018-06-19 Telefonaktiebolaget Lm Ericsson (Publ) Method and system for memory allocation in a software-defined networking (SDN) system
US9740438B2 (en) * 2015-08-20 2017-08-22 Sap Se Allocating memory on multiple types of main memory technologies from software application layer
US20170108914A1 (en) * 2015-10-16 2017-04-20 Qualcomm Incorporated System and method for memory channel interleaving using a sliding threshold address
US20170108911A1 (en) * 2015-10-16 2017-04-20 Qualcomm Incorporated System and method for page-by-page memory channel interleaving
GB2545170B (en) * 2015-12-02 2020-01-08 Imagination Tech Ltd GPU virtualisation
US11762764B1 (en) 2015-12-02 2023-09-19 Pure Storage, Inc. Writing data in a storage system that includes a first type of storage device and a second type of storage device
US20170168541A1 (en) 2015-12-15 2017-06-15 Intel Corporation Processor core energy management
US20170185292A1 (en) * 2015-12-23 2017-06-29 Intel Corporation Memory Management of High-Performance Memory
CN105676727B (zh) * 2016-01-11 2018-03-02 西北工业大学 一种发动机燃油供应系统控制时序存储和读取方法
US10140216B2 (en) * 2016-01-21 2018-11-27 Arm Limited Measuring address translation latency
US9830086B2 (en) * 2016-03-03 2017-11-28 Samsung Electronics Co., Ltd. Hybrid memory controller for arbitrating access to volatile and non-volatile memories in a hybrid memory group
US20170262367A1 (en) * 2016-03-11 2017-09-14 Qualcomm Incorporated Multi-rank collision reduction in a hybrid parallel-serial memory system
CN106657718B (zh) * 2016-11-07 2019-12-06 金陵科技学院 实现虚拟现实的数据传送系统及其方法
US10866912B2 (en) 2017-03-10 2020-12-15 Toshiba Memory Corporation Integrated heterogeneous solid state storage drive
CN107102824B (zh) * 2017-05-26 2019-08-30 华中科技大学 一种基于存储和加速优化的Hadoop异构方法和系统
US11049009B2 (en) 2017-06-12 2021-06-29 Western Digital Technologies, Inc. Identifying memory block write endurance using machine learning
US10445009B2 (en) * 2017-06-30 2019-10-15 Intel Corporation Systems and methods of controlling memory footprint
US10783252B2 (en) * 2017-08-23 2020-09-22 Qualcomm Incorporated System and method for booting within a heterogeneous memory environment
US10691805B2 (en) * 2018-02-14 2020-06-23 GM Global Technology Operations LLC Resident manufacturing test software based system for mitigating risks associated with vehicle control modules
US20190370009A1 (en) * 2018-06-03 2019-12-05 Apple Inc. Intelligent swap for fatigable storage mediums
CN110928737B (zh) * 2018-09-19 2021-05-18 华为技术有限公司 监控样本进程的内存访问行为的方法和装置
US11176493B2 (en) 2019-04-29 2021-11-16 Google Llc Virtualizing external memory as local to a machine learning accelerator
CN112016693B (zh) * 2019-05-30 2021-06-04 中兴通讯股份有限公司 机器学习引擎实现方法及装置、终端设备、存储介质
CN110265029A (zh) * 2019-06-21 2019-09-20 百度在线网络技术(北京)有限公司 语音芯片和电子设备
US11099758B2 (en) * 2019-07-16 2021-08-24 Facebook Technologies, Llc Memory management of computing devices
US10996975B2 (en) * 2019-08-22 2021-05-04 Micron Technology, Inc. Hierarchical memory systems
US11650742B2 (en) * 2019-09-17 2023-05-16 Micron Technology, Inc. Accessing stored metadata to identify memory devices in which data is stored
US11494311B2 (en) 2019-09-17 2022-11-08 Micron Technology, Inc. Page table hooks to memory types
JP2021051420A (ja) 2019-09-24 2021-04-01 株式会社東芝 仮想化支援デバイス及び仮想化支援デバイスの制御方法
US11733763B2 (en) * 2020-08-06 2023-08-22 Micron Technology, Inc. Intelligent low power modes for deep learning accelerator and random access memory
WO2022118322A1 (en) * 2020-12-02 2022-06-09 Unifabrix Ltd. System and method for multimodal computer address space provisioning
US20220318132A1 (en) * 2022-06-22 2022-10-06 Intel Corporation Software-assisted sparse memory
US12197266B2 (en) * 2022-11-22 2025-01-14 Gopro, Inc. Dynamic power allocation for memory using multiple interleaving patterns

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1662886A (zh) * 2002-04-18 2005-08-31 英特尔公司 存储信息的方法和系统
US20090106478A1 (en) * 2007-10-19 2009-04-23 Virident Systems Inc. Managing Memory Systems Containing Components with Asymmetric Characteristics
US20120117304A1 (en) * 2010-11-05 2012-05-10 Microsoft Corporation Managing memory with limited write cycles in heterogeneous memory systems
US20120198140A1 (en) * 2006-11-04 2012-08-02 Virident Systems Inc. Asymmetric memory migration in hybrid main memory

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04230508A (ja) * 1990-10-29 1992-08-19 Internatl Business Mach Corp <Ibm> 低電力消費メモリ装置
JPH11242629A (ja) * 1997-10-09 1999-09-07 Matsushita Electric Ind Co Ltd メモリシステム
JP2004310580A (ja) * 2003-04-09 2004-11-04 Mitsubishi Electric Corp メモリマップ最適化方式及びメモリマップ最適化方法
GB2460393B (en) 2008-02-29 2012-03-28 Advanced Risc Mach Ltd A data processing apparatus and method for controlling access to secure memory by virtual machines executing on processing circuitry
US9280466B2 (en) 2008-09-09 2016-03-08 Kabushiki Kaisha Toshiba Information processing device including memory management device managing access from processor to memory and memory management method
JP2011022933A (ja) * 2009-07-17 2011-02-03 Toshiba Corp メモリ管理装置を含む情報処理装置及びメモリ管理方法
GB2474666B (en) 2009-10-21 2015-07-15 Advanced Risc Mach Ltd Hardware resource management within a data processing system
US8589650B2 (en) * 2010-05-17 2013-11-19 Texas Instruments Incorporated Dynamically configurable memory system
GB2483906C (en) * 2010-09-24 2019-10-09 Advanced Risc Mach Ltd Selection of debug instruction set for debugging of a data processing apparatus
GB2483907A (en) 2010-09-24 2012-03-28 Advanced Risc Mach Ltd Privilege level switching for data processing circuitry when in a debug mode
US8239620B2 (en) 2010-09-27 2012-08-07 Mips Technologies, Inc. Microprocessor with dual-level address translation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1662886A (zh) * 2002-04-18 2005-08-31 英特尔公司 存储信息的方法和系统
US20120198140A1 (en) * 2006-11-04 2012-08-02 Virident Systems Inc. Asymmetric memory migration in hybrid main memory
US20090106478A1 (en) * 2007-10-19 2009-04-23 Virident Systems Inc. Managing Memory Systems Containing Components with Asymmetric Characteristics
US20120117304A1 (en) * 2010-11-05 2012-05-10 Microsoft Corporation Managing memory with limited write cycles in heterogeneous memory systems

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11791326B2 (en) 2021-05-10 2023-10-17 International Business Machines Corporation Memory and logic chip stack with a translator chip

Also Published As

Publication number Publication date
EP2883146A1 (en) 2015-06-17
JP5916955B2 (ja) 2016-05-11
IN2015MN00051A (enExample) 2015-10-16
US9047090B2 (en) 2015-06-02
US20140047251A1 (en) 2014-02-13
JP2015528597A (ja) 2015-09-28
CN104520823A (zh) 2015-04-15
WO2014025454A1 (en) 2014-02-13

Similar Documents

Publication Publication Date Title
CN104520823B (zh) 用于混合存储器管理的方法、系统和设备
US10503542B2 (en) Systems, methods and devices for work placement on processor cores
US9268394B2 (en) Virtualized application power budgeting
Francesco et al. An integrated hardware/software approach for run-time scratchpad management
JP6110038B2 (ja) 異種マルチプロセッサシステムにおける共有メモリ領域のための動的なアドレスのネゴシエーション
US20120054409A1 (en) Application triggered state migration via hypervisor
Shaheen et al. Towards energy saving in computational clouds: taxonomy, review, and open challenges
CN111860804A (zh) 分形计算装置、方法、集成电路及板卡
Singh et al. Collaborative adaptation for energy-efficient heterogeneous mobile SoCs
Chen et al. Cache partitioning and scheduling for energy optimization of real-time MPSoCs
Cuesta et al. Adaptive task migration policies for thermal control in MPSoCs
CN107562645A (zh) 一种内存页管理方法及计算设备
Liu et al. Scratchpad memory architectures and allocation algorithms for hard real-time multicore processors
Liang et al. Data center multidimensional management strategy based on descending neighborhood DBSCAN algorithm in unsupervised learning
US10956210B2 (en) Multi-processor system, multi-core processing device, and method of operating the same
Hu et al. A novel design of software system on chip for embedded system
Tang et al. CARE: Cloudified android OSes on the cloud rendering
Zhu et al. A thread-oriented memory resource management framework for mobile edge computing
Georgopoulos et al. Energy-efficient heterogeneous computing at exaSCALE—ECOSCALE
Dustdar et al. Rethinking divide and conquer—Towards holistic interfaces of the computing stack
Sundari et al. Improved memory performance through the development of an energy efficient distributed memory Management System
Valera An energy saving perspective for distributed environments: Deployment, scheduling and simulation with multidimensional entities for Software and Hardware
US20250390977A1 (en) Granular gpu dvfs with execution unit partial powerdown
US20240354139A1 (en) Low-latency virtual machines
Moore et al. General-purpose multi-core processors

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20160504

Termination date: 20210613