CN104518789A - Method for high-precision digital frequency pulse output - Google Patents
Method for high-precision digital frequency pulse output Download PDFInfo
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- CN104518789A CN104518789A CN201410839011.9A CN201410839011A CN104518789A CN 104518789 A CN104518789 A CN 104518789A CN 201410839011 A CN201410839011 A CN 201410839011A CN 104518789 A CN104518789 A CN 104518789A
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Abstract
The invention relates to a method for high-precision digital frequency pulse output. The method is characterized in that an FPGA (Field Programmable Gate Array) chip and an external clock are provided, wherein the external clock is used as a system clock; two channels of internal clocks of 250 MHz are provided through phase-locked loop frequency doubling inside the chip, and the phase difference of the two channels of clocks is 180 degrees; the error of each channel of clock is 4 ns, the errors of the two channels of clocks are complementary, and the precision is improved to 2 ns through addition of compensation algorithm. According to the method, an algorithm is designed by the utilization of an FPGA hardware circuit and a verilog language, so that the pulse width precision outputted by pulse width can reach 2 ns, and the pulse width output interval precision of an interrupt event can reach 2 ns.
Description
Technical field
The present invention relates to a kind of method that numerical frequency pulse exports, be specifically related to a kind of method that high accuracy number frequency pulse exports, export numerical frequency pulse signal width up to 2ns precision.
Background technology
At present, the precision of existing frequency digital card pulse output signals is mainly relevant according to the clock frequency of frequency meter card inside, and precision approximately all remains on us level scope.
Summary of the invention
In order to overcome the drawback of above-mentioned existing digital pulse width method of measurement, the present invention utilizes a kind of algorithm of FPGA hardware circuit, verilog language design, and the pulsewidth precision that pulsewidth is exported can up to 2ns, and the pulsewidth output gap precision of interrupt event can up to 2ns.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of method that high accuracy number frequency pulse exports, its special character is: the method provides a fpga chip and an external clock, using this external clock as system clock, chip internal frequency multiplication of phase locked loop is utilized to go out the internal clocking of 2 road 250MHz, 2 road clock phase differences 180 degree.The error of every road clock is 4ns, and two-way clocking error is complementary, then adds backoff algorithm and make precision bring up to 2ns.
The internal clocking of above-mentioned 2 road 250MHz wherein a road clock as reference clock, another road clock is as auxiliary clock, reference clock is used for the calculating of rough grade, first producing an error is the reference value of 4ns, according to actual conditions, the reference value that error is 4ns is carried out to the positive and negative compensation of 2ns again by auxiliary clock, thus make overall precision bring up to 2ns.
The adjacent two pulse signals that above-mentioned backoff algorithm exports under specifically utilizing adjacent positive-negative phase clock, by this two pulse signals through XOR gate process, then can draw two 2ns pulses at output, the pulse spacing is 2ns; This two pulse signals is passed through and door process, then draws a road 2ns pulse signal at output; 3 the 2ns pulse signal counters exported by above-mentioned output mark, then can select at output the pulse exporting any duty ratio and optional frequency; Also can utilize external interrupt signal, control the time interval interrupting exporting between pulsewidth, precision can up to 2ns.
Said external clock is the external crystal-controlled oscillation clock of 50MHz.
The model that above-mentioned fpga chip adopts XILINX company to produce is the chip of SPARTAN6 series.
Beneficial outcomes of the present invention is:
1) the present invention can make the output accuracy of digital pulse signal up to 2ns, and duty ratio precision also can reach 2ns.
2) phase-locked loop of the present invention is a kind of analog phase-locked look, and inside comprises voltage controlled oscillator and phase discriminator, realizes phase deviation, and have more leggy by the mode of simulation.
3) the present invention more economically, do not need a lot of stone resource, a phase-locked loop.
Embodiment
The present invention adopts FPGA minimum system to be used as gathering the hardware implementations of pulse width signal.The model that FPGA adopts XILINX company to produce is the chip of SPARTAN6 series, external crystal-controlled oscillation clock selecting.Using this external clock as system clock, chip internal frequency multiplication of phase locked loop is utilized to go out the internal clocking of 2 road 250MHz, 2 road clock phase differences 180 degree.The error of every road clock is 4ns, and two-way clocking error is complementary, then adds backoff algorithm and make precision bring up to 2ns.
The present invention use wherein a road clock as reference clock, another road clock is as auxiliary clock, reference clock is used for the calculating of rough grade, first producing an error is the reference value of 4ns, according to actual conditions, the reference value that error is 4ns is carried out to the positive and negative compensation of 2ns again by auxiliary clock, thus make overall precision bring up to 2ns.
Specifically: the adjacent two pulse signals exported under utilizing adjacent positive-negative phase clock, by this two pulse signals through XOR gate process, then can draw two 2ns pulses at output, the pulse spacing is 2ns; This two pulse signals is passed through and door process, then draws a road 2ns pulse signal at output.3 the 2ns pulse signal counters exported by above-mentioned output mark, then can select at output the pulse exporting any duty ratio and optional frequency; Also can utilize external interrupt signal, control the time interval interrupting exporting between pulsewidth, precision can up to 2ns.
Claims (5)
1. the method for a high accuracy number frequency pulse output, it is characterized in that: the method provides a fpga chip and an external clock, using this external clock as system clock, chip internal frequency multiplication of phase locked loop is utilized to go out the internal clocking of 2 road 250MHz, 2 road clock phase differences 180 degree; The error of every road clock is 4ns, and two-way clocking error is complementary, then adds and make precision bring up to 2ns.
2. the method for high accuracy number frequency pulse output according to claim 1, it is characterized in that: the internal clocking of described 2 road 250MHz wherein a road clock as reference clock, another road clock is as auxiliary clock, reference clock is used for the calculating of rough grade, first producing an error is the reference value of 4ns, according to actual conditions, the reference value that error is 4ns is carried out to the positive and negative compensation of 2ns again by auxiliary clock, thus make overall precision bring up to 2ns.
3. the method that high accuracy number frequency pulse exports according to claim 1 or 2, it is characterized in that: the adjacent two pulse signals that described backoff algorithm exports under specifically utilizing adjacent positive-negative phase clock, by this two pulse signals through XOR gate process, then can draw two 2ns pulses at output, the pulse spacing is 2ns; This two pulse signals is passed through and door process, then draws a road 2ns pulse signal at output; 3 the 2ns pulse signal counters exported by above-mentioned output mark, then can select at output the pulse exporting any duty ratio and optional frequency; Also can utilize external interrupt signal, control the time interval interrupting exporting between pulsewidth, precision can up to 2ns.
4. the method for high accuracy number frequency pulse output according to claim 3, is characterized in that: described external clock is the external crystal-controlled oscillation clock of 50MHz.
5. the method for high accuracy number frequency pulse output according to claim 4, is characterized in that: the model that described fpga chip adopts XILINX company to produce is the chip of SPARTAN6 series.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410839011.9A CN104518789A (en) | 2014-12-30 | 2014-12-30 | Method for high-precision digital frequency pulse output |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410839011.9A CN104518789A (en) | 2014-12-30 | 2014-12-30 | Method for high-precision digital frequency pulse output |
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| CN104518789A true CN104518789A (en) | 2015-04-15 |
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| CN201410839011.9A Pending CN104518789A (en) | 2014-12-30 | 2014-12-30 | Method for high-precision digital frequency pulse output |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107171780A (en) * | 2017-05-26 | 2017-09-15 | 北京理工大学 | Clock recovery phase ambiguity judges, the device and method of compensation |
Citations (4)
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| CN1667957A (en) * | 2004-03-09 | 2005-09-14 | 阿尔特拉公司 | Highly configurable PLL architecture for programmable logic device |
| US6965660B2 (en) * | 2000-10-05 | 2005-11-15 | Infineon Technologies Ag | Digital phase-locked loop |
| CN103490781A (en) * | 2013-09-14 | 2014-01-01 | 西安奇维科技股份有限公司 | High-accuracy analog signal acquisition circuit with temperature self-correcting function |
| CN103698770A (en) * | 2013-12-11 | 2014-04-02 | 中国科学院长春光学精密机械与物理研究所 | Multi-channel laser echo time measurement system based on FPGA (Field Programmable Gate Array) chip |
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2014
- 2014-12-30 CN CN201410839011.9A patent/CN104518789A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6965660B2 (en) * | 2000-10-05 | 2005-11-15 | Infineon Technologies Ag | Digital phase-locked loop |
| CN1667957A (en) * | 2004-03-09 | 2005-09-14 | 阿尔特拉公司 | Highly configurable PLL architecture for programmable logic device |
| CN103490781A (en) * | 2013-09-14 | 2014-01-01 | 西安奇维科技股份有限公司 | High-accuracy analog signal acquisition circuit with temperature self-correcting function |
| CN103698770A (en) * | 2013-12-11 | 2014-04-02 | 中国科学院长春光学精密机械与物理研究所 | Multi-channel laser echo time measurement system based on FPGA (Field Programmable Gate Array) chip |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107171780A (en) * | 2017-05-26 | 2017-09-15 | 北京理工大学 | Clock recovery phase ambiguity judges, the device and method of compensation |
| CN107171780B (en) * | 2017-05-26 | 2018-07-06 | 北京理工大学 | The judgement of clock recovery phase ambiguity, the device and method of compensation |
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Application publication date: 20150415 |