CN104517937A - Test structure and formation method and test method thereof - Google Patents
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Abstract
Disclosed are a test structure, a formation method and a test method thereof. The test structure comprises a semiconductor substrate, a through-silicone interconnection structure, a medium layer, a first metal interconnection layer, a second metal interconnection layer, a first test end and a second test end, wherein the through-silicone interconnection structure is arranged in the semiconductor substrate, the medium layer covers the semiconductor substrate, the first metal interconnection layer and the second metal interconnection layer are mutually separated in the medium layer and both comprise second diffusion barrier layers and aluminum metal layers arranged on the second diffusion barrier layers, the first metal interconnection layer is connected with the surface of the through-silicone interconnection structure, the second metal interconnection layer is ring-shaped, and the first metal interconnection layer is arranged in the ring; the first test end is connected with the first metal interconnection layer, and the second test end is connected with the second metal interconnection layer. The test structure can detect whether the diffusion barrier layers have cracks or not and locate the cracks.
Description
Technical field
The present invention relates to field of semiconductor fabrication, particularly a kind of test structure and forming method thereof, method of testing.
Background technology
Along with semiconductor technology development, the characteristic size of current semiconductor device has become very little, wish that the quantity increasing semiconductor device in the encapsulating structure of two dimension becomes more and more difficult, therefore three-dimension packaging becomes a kind of method that effectively can improve chip integration.Current three-dimension packaging comprises based on chip-stacked (the Die Stacking) of wire bonding, encapsulation stacking (Package Stacking) and three-dimensional stacked based on silicon through hole (Through Silicon Via, TSV).Wherein, the three-dimensional stacked technology of silicon through hole is utilized to have following three advantages: (1) High Density Integration; (2) shorten the length of electrical interconnection significantly, thus the problems such as the signal delay appeared in two-dimentional system level chip (SOC) technology can be solved well; (3) utilize silicon through hole technology, the chip (as radio frequency, internal memory, logic, MEMS etc.) with difference in functionality can be integrated and realize the multi-functional of packaged chip.Therefore, the described three-dimensional stacked technology of silicon through hole interconnect structure that utilizes becomes a kind of comparatively popular chip encapsulation technology day by day.
Please refer to Fig. 1, the formation method of current silicon through hole interconnect structure comprises: in Semiconductor substrate 101, form hard mask layer 105, and hard mask layer 105 material is silica or silicon nitride; Etch described hard mask layer 105 and Semiconductor substrate 101 forms through hole; At sidewall and the lower surface formation insulating barrier of through hole, insulating layer material is silica; Adopt electric plating method that copper is filled full through hole, and remove unnecessary copper metal layer with chemico-mechanical polishing, form silicon through hole interconnect structure 102; Described silicon through hole interconnect structure 102 and hard mask layer 105 form diffusion impervious layer 104; Diffusion impervious layer 104 is formed the first metal layer 103, and the material of the first metal layer 103 is aluminium, and described diffusion impervious layer 104 stops that the copper atom in silicon through hole interconnect structure 102 spreads in the first metal layer 103; Form the dielectric layer 106 covering described the first metal layer 103 and hard mask layer 105, the material of dielectric layer 106 is silica.
In silicon through hole interconnect structure, relative to the thermal coefficient of expansion of semiconductor substrate materials and insulating layer material, the thermal coefficient of expansion of metallic copper is maximum, when subsequent technique comprises Technology for Heating Processing, silicon through hole interconnect structure 102 easily collides, the displacement of the vertical direction of silicon through hole interconnect structure 102 direction of Semiconductor substrate 101 (vertical and), the diffusion impervious layer 104 between the first metal layer 103 and silicon through hole interconnect structure 102 is easily made to rupture, the interface of the first metal layer 103 and silicon through hole interconnect structure 102 is formed fracture defect 11, specifically please refer to Fig. 2, as can be seen from Figure 2, silicon through hole interconnect structure 102 longitudinal dilatation, the diffusion impervious layer 104 of top can be extruded, the defect 11 that ruptures is formed at diffusion impervious layer 104 and the demarcation line of silicon through hole interconnect structure 102, the copper in the metal of the first metal layer 103 and silicon through hole interconnect structure 102 is made to understand phase counterdiffusion by this fracture defect 11, copper in silicon through hole interconnect structure 102 is diffused into after in the first metal layer 103, under the condition of high temperature, easy continuation is spread in dielectric layer 106, thus easily cause the inefficacy of semiconductor device, reduce the reliability of semiconductor device.
Summary of the invention
The component failure brought when the problem that the present invention solves is and how detects diffusion barrier fault rupture.
For solving the problem, the invention provides a kind of test structure, comprising: Semiconductor substrate, be positioned at the silicon through hole interconnect structure of Semiconductor substrate; Cover the dielectric layer of described Semiconductor substrate; Be arranged in the first metal interconnecting layer be separated from each other and second metal interconnecting layer of dielectric layer, the aluminum metal layer that described first metal interconnecting layer and the second metal interconnecting layer comprise the second diffusion impervious layer and be positioned on the second diffusion impervious layer, described first metal interconnecting layer is connected with the surface of silicon through hole interconnect structure, second metal interconnecting layer shape is annular, and the first metal interconnecting layer is positioned at annular; The first test lead be connected with the first metal interconnecting layer; The second test lead be connected with the second metal interconnecting layer.
Optionally, described silicon through hole interconnect structure comprise the through hole being positioned at Semiconductor substrate, the insulating barrier being positioned at through-hole side wall and bottom, be positioned at surface of insulating layer the first diffusion impervious layer and to be positioned on diffusion impervious layer and the copper metal layer of filling vias.
Optionally, described first metal interconnecting layer is positioned at directly over silicon through hole interconnect structure, and the size of the first metal interconnecting layer is greater than the size of silicon through hole interconnect structure.
Optionally, the edge of described first metal interconnecting layer and the distance at silicon through hole interconnect structure edge are 4 ~ 6 microns.
Optionally, described first metal interconnecting layer is positioned at the center of the annular of the second metal interconnecting layer.
Optionally, the distance between described first metal interconnecting layer and the second metal interconnecting layer is 3 ~ 5 microns.
Optionally, the second metal interconnecting layer of described annular comprises at least two discrete son annulars, and discrete at least two sub-annular rings are around described first metal interconnecting layer.
Optionally, described second test lead comprises some sub-test leads, and the quantity of sub-test lead is equal with the quantity of subring shape, and every sub-test lead is connected with corresponding subring shape.
Optionally, the radian of each subring shape is equal, and equal angular around described first metal interconnecting layer.
Present invention also offers a kind of method of testing, comprising:
There is provided test structure, described test structure comprises: Semiconductor substrate, is positioned at the silicon through hole interconnect structure of Semiconductor substrate; Cover the dielectric layer of described Semiconductor substrate; Be arranged in the first metal interconnecting layer be separated from each other and second metal interconnecting layer of dielectric layer, the aluminum metal layer that described first metal interconnecting layer and the second metal interconnecting layer comprise the second diffusion impervious layer and be positioned on the second diffusion impervious layer, described first metal interconnecting layer is connected with the surface of silicon through hole interconnect structure, second metal interconnecting layer shape is annular, and the first metal interconnecting layer is positioned at annular; The first test lead be connected with the first metal interconnecting layer; The second test lead be connected with the second metal interconnecting layer; First test lead is connected power end, the second test lead ground connection; Measure the leakage current value between acquisition first test lead and the second test lead; When leakage current value be greater than reference current value time, then there is the defect that ruptures in the second diffusion impervious layer between silicon through hole interconnect structure and the first metal interconnecting layer.
Optionally, the voltage swing of described power end is 1 ~ 20 volt.
Optionally, the size of described reference current value is 1E-6 ~ 9E-6 peace.
Optionally, second metal interconnecting layer of described annular comprises at least two discrete son annulars, discrete at least two sub-annular rings are around described the first metal layer, described second test lead comprises some sub-test leads, the quantity of sub-test lead is equal with the quantity of subring shape, and every sub-test lead is connected with corresponding subring shape, every sub-test lead ground connection.
Optionally, test the electric current between the first test lead and every sub-test lead respectively, obtain some sub-measuring currents, when a certain sub-measuring current is greater than reference current value, then there is the defect that ruptures in the second corresponding with this subring shaped position diffusion barrier layer region.
Present invention also offers a kind of formation method of test structure, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, forms silicon through hole interconnect structure; Form the first metal interconnecting layer and the second metal interconnecting layer that are separated from each other on the semiconductor substrate, the aluminum metal layer that described first metal interconnecting layer and the second metal interconnecting layer comprise the second diffusion impervious layer and be positioned on the second diffusion impervious layer, described first metal interconnecting layer is connected with the surface of silicon through hole interconnect structure, second metal interconnecting layer shape is annular, and the first metal interconnecting layer is positioned at annular; Form the dielectric layer covering described first metal interconnecting layer, the second metal interconnecting layer and Semiconductor substrate; Form the first test lead be connected with the first metal interconnecting layer, the second test lead be connected with the second metal interconnecting layer.
Compared with prior art, technical scheme of the present invention has the following advantages:
Described test structure comprises the first discrete metal interconnecting layer and the second metal interconnecting layer, first metal interconnecting layer to be positioned on silicon through hole interconnect structure and to be connected with silicon through hole interconnect structure, second metal interconnecting layer is annular, second metal interconnecting layer is around described first metal interconnecting layer, therefore no matter there is in which direction the defect that ruptures in the intersection at the edge of the second diffusion impervious layer and silicon through hole interconnect structure, test structure of the present invention is all by detecting the leakage current between the first metal interconnecting layer and the second metal interconnecting layer, can judge whether the second diffusion impervious layer ruptures by the size of current value, whether the metal in silicon through hole interconnect structure is diffused in the first metal interconnecting layer neutralization medium layer.
Further, first metal interconnecting layer is positioned at the center of the annular of the second metal interconnecting layer, the second metal interconnecting layer can be made to be equal at one week of annular with the distance at the edge of the first metal interconnecting layer, when the second diffusion impervious layer produces fracture defect, in all directions, the path that copper atom spreads to the second metal interconnecting layer direction through the first metal interconnecting layer is equal, improves accuracy and the sensitivity of follow-up measurement.
Further, second metal interconnecting layer of described annular comprises some discrete subring shapes, some discrete subring shapes are around described first metal interconnecting layer, therefore the size of the leakage current between the first metal interconnecting layer and each subring shape is measured respectively, the second diffusion impervious layer can be detected and whether have fracture defect, can also according to the second diffusion impervious layer existing defects in which place (or direction) of the position judgment of subring shape, to bringing great convenience property such as failure analyses.
Accompanying drawing explanation
Fig. 1 ~ Fig. 2 is the structural representation of present technology silicon through hole interconnect structure;
Fig. 3 ~ Fig. 5 is the structural representation of test structure of the present invention.
Embodiment
As background technology sayed, existing silicon through hole interconnect structure expands and easily makes diffusion impervious layer rupture, copper in silicon through hole interconnect structure is easily diffused in dielectric layer further being diffused into after in the first metal layer, affects the stability of semiconductor device.
The invention provides a kind of test structure and forming method thereof, method of testing, described test structure comprises the first discrete metal interconnecting layer and the second metal interconnecting layer, first metal interconnecting layer to be positioned on silicon through hole interconnect structure and to be connected with silicon through hole interconnect structure, second metal interconnecting layer is annular, second metal interconnecting layer is around described first metal interconnecting layer, therefore by the current value between measurement first metal interconnecting layer and the second metal interconnecting layer, can judge whether the second diffusion impervious layer ruptures by the size of current value, whether the metal in silicon through hole interconnect structure is diffused in the first metal interconnecting layer neutralization medium layer.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.When describing the embodiment of the present invention in detail, for ease of illustrating, schematic diagram can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, and it should not limit the scope of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
Fig. 3 ~ Fig. 5 is the structural representation of embodiment of the present invention test structure.
Be the cross-sectional view of Fig. 3 along line of cut AB direction with reference to figure 3 and Fig. 4, Fig. 4, described test structure comprises: Semiconductor substrate 200, is positioned at the silicon through hole interconnect structure 202 of Semiconductor substrate 200; Cover the dielectric layer 214 of described Semiconductor substrate 200; Be arranged in first metal interconnecting layer 206 and second metal interconnecting layer 208 be separated from each other of dielectric layer 214, the aluminum metal layer 207 that described first metal interconnecting layer 206 and the second metal interconnecting layer 208 comprise the second diffusion impervious layer 212 and be positioned on the second diffusion impervious layer 212, described first metal interconnecting layer 206 is connected with the surface of silicon through hole interconnect structure 202, second metal interconnecting layer 208 shape is annular, and the first metal interconnecting layer 206 is positioned at annular; The first test lead 211 be connected with the first metal interconnecting layer 206; The second test lead 210 be connected with the second metal interconnecting layer 208.
Concrete, described Semiconductor substrate 200 can be single or multiple lift stacked structure, and Semiconductor substrate 200 described in the present embodiment is single layer structure, and described Semiconductor substrate 200 is silicon substrate, germanium substrate, silicon-Germanium substrate or silicon nitrate substrate; Described Semiconductor substrate 200 can also be III-V compounds of group substrate such as silicon-on-insulator substrate or GaAs.In other embodiments of the invention, when described Semiconductor substrate 200 is multilayer lamination structure, described Semiconductor substrate 200 comprises semiconductor base and is positioned at least one deck dielectric layer on semiconductor base.
Described Semiconductor substrate 200 also has hard mask layer 201, mask when described hard mask layer 201 forms through hole as etch semiconductor substrates 200, in the present embodiment, described hard mask layer 201 is as a part for Semiconductor substrate 200, and described silicon through hole interconnect structure 202 part is arranged in hard mask layer 201.
Described silicon through hole interconnect structure 202 comprise the through hole being positioned at Semiconductor substrate 200, the insulating barrier 204 being positioned at through-hole side wall and bottom, be positioned at insulating barrier 204 surface the first diffusion impervious layer 203 and to be positioned on the first diffusion impervious layer 203 and the copper metal layer 205 of filling vias.
Described insulating barrier 204 is for the electric isolation between silicon through hole interconnect structure and Semiconductor substrate, and the material of described insulating barrier 204 can be silica.
Described first diffusion impervious layer 203 spreads in Semiconductor substrate 200 for the copper atom in copper metal layer 205.Described first diffusion impervious layer 203 is single or multiple lift stacked structure, and such as described first diffusion impervious layer 203 is the double-decker of Ti/TiN, the double-decker of Ta/TaN.
The aluminum metal layer 207 that described first metal interconnecting layer 206 comprises the second diffusion impervious layer 212 and is positioned on the second diffusion impervious layer 212, described second diffusion impervious layer 212 covers the surface of silicon through hole interconnect structure 202, second diffusion impervious layer 212 is for preventing the copper in copper metal layer 205 and the aluminium phase counterdiffusion in aluminum metal layer 207, and affect the stability of semiconductor device, described first metal interconnecting layer 206 is positioned at directly over silicon through hole interconnect structure 202, the size of the first metal interconnecting layer 206 is greater than the size of silicon through hole interconnect structure 202, the lifting surface area of the first metal interconnecting layer 206 is made to be greater than the surface area of silicon through hole interconnect structure 202, when there is longitudinal displacement in silicon through hole interconnect structure 202 thermal expansion, the second diffusion impervious layer 212 in first metal interconnecting layer 206 easily produces fracture defect with the intersection at the edge of silicon through hole interconnect structure 202, make follow-up can by the leakage current value between measurement first metal interconnecting layer 206 and the second metal interconnecting layer 208, judge whether to there is fracture defect by the size of leakage current value.
Second diffusion impervious layer 212 is single or multiple lift stacked structure, and such as described second diffusion impervious layer 212 is the double-decker of Ti/TiN, the double-decker of Ta/TaN.It should be noted that, in other embodiments of the invention, described second diffusion impervious layer can also be other structure and material.
The section shape of the transverse direction (being parallel to the direction on Semiconductor substrate 200 surface) of described first metal interconnecting layer 206 is circular, quadrangle or irregularly shaped.In the present embodiment, the section shape of the transverse direction of described first metal interconnecting layer 206 is identical with the section shape of silicon through hole interconnect structure 102 transverse direction, the section shape of the transverse direction of described first metal interconnecting layer 206 is circle, the edge of the first metal interconnecting layer 206 can be made equal with the distance at the edge of silicon through hole interconnect structure 202, when there is fracture defect in the second diffusion impervious layer 212, the evolving path of copper atom along each method in the first metal interconnecting layer 206 is equal, improves the accuracy of detection, sensitivity and efficiency.
The edge of described first metal interconnecting layer 206 and the distance W1 at silicon through hole interconnect structure 202 edge are 4 ~ 6 microns, silicon through hole interconnect structure 202 is covered by the first metal interconnecting layer 206 completely, prevent copper metal layer 205 from contacting with dielectric layer 214, cause the diffusion of copper atom, affect the stability of test structure, in addition, when making silicon through hole interconnect structure 202 expanded by heating, second diffusion impervious layer 212 easily produces fracture defect with the intersection at the edge of silicon through hole interconnect structure 202, thus can realize the detection to fracture defect.
Described second metal interconnecting layer 208 is annular, second metal interconnecting layer 208 is around described first metal interconnecting layer 206, namely the first metal interconnecting layer 206 is positioned at annular, and the second metal interconnecting layer 208 and the first metal interconnecting layer 206 are positioned at same plane (distance on the surface of the distance from bottom Semiconductor substrate 200 of the second metal interconnecting layer 208 and the first metal interconnecting layer 206 is equal), therefore no matter if which direction there is the defect that ruptures with the intersection at the edge of silicon through hole interconnect structure 202 in the second diffusion impervious layer 212, test structure of the present invention is all by detecting the leakage current between the first metal interconnecting layer 206 and the second metal interconnecting layer 208, judge whether the existence of fracture defect.
The annular of described second metal interconnecting layer 208 can be annulus, polygon ring (limit number is more than or equal to 3) or irregular annular.In the present embodiment, the shape of the annular of described second metal interconnecting layer 208 is identical with the shape at the edge of the first metal interconnecting layer 206, described annular is annulus, and described first metal interconnecting layer 206 is positioned at the center of the annular of the second metal interconnecting layer 208, the second metal interconnecting layer 208 is made to be equal at one week of annular with the distance at the edge of the first metal interconnecting layer 206, when the second diffusion impervious layer 212 produces fracture defect, in all directions, the path that copper atom spreads to the second metal interconnecting layer 208 direction through the first metal interconnecting layer 206 is equal, improve accuracy and the sensitivity of follow-up measurement.
Distance W2 between described first metal interconnecting layer and the second metal interconnecting layer is 3 ~ 5 microns, while the validity improving fracture defectoscopy and sensitivity, saves the area that test structure occupies.
Described first metal interconnecting layer 206 is connected with the first test lead 211, and when testing, described first test lead 211 is for applying supply voltage.
Second metal interconnecting layer 208 is connected with the second test lead 210, when testing, described second test lead 210 ground connection, measure the first test lead 211(or the first metal interconnecting layer 206) and the second test lead (or second metal interconnecting layer 208) between leakage current, judge whether there is fracture defect in the second diffusion impervious layer 212 by the size of leakage current.
The metal wire that first test lead 211 or the second test lead 210 comprise connector and be connected with connector, the top surface of described first metal interconnecting layer and the sidewall of connector are also formed with the 3rd diffusion impervious layer, prevent the dielectric layer diffusion of metallic atom above the first metal interconnecting layer 206, and affect measurement effect.
In other embodiments of the invention, second metal interconnecting layer 208 of described annular is broken as some subring shapes, specifically please refer to Fig. 5, second metal interconnecting layer of described annular comprises at least two discrete son annulars, such as: subring shape 208a, 208b, 208c and 208d in Fig. 5, discrete at least two sub-annular rings are around described first metal interconnecting layer 206.
Described second test lead comprises some sub-test leads accordingly, self-test end 210a, 210b, 210c and 210d in such as Fig. 5, and the quantity of sub-test lead is equal with the quantity of subring shape, and every sub-test lead is connected with corresponding subring shape.
Although the test structure in previous embodiment can test the second diffusion impervious layer whether there is fracture defect, but there is fracture defect in the second diffusion impervious layer can accurately not locating that place (or that direction), inconvenience is brought to failure analysis etc., in the present embodiment, second metal interconnecting layer of annular is broken as some discrete subring shapes, some discrete subring shapes are around described first metal interconnecting layer, therefore the size of the leakage current between the first metal interconnecting layer and each subring shape is measured respectively, the second diffusion impervious layer can be detected and whether have fracture defect, can also according to the second diffusion impervious layer existing defects in which place (or direction) of the position judgment of subring shape, to bringing great convenience property such as failure analyses.
The quantity of described subring shape is at least more than or equal to 2, and the radian of each subring shape is equal, and equal angular around described first metal interconnecting layer, is conducive to the accuracy and the precision that improve location.In the particular embodiment, the quantity of described subring shape is 3 ~ 10, while making test structure have certain positioning precision, reduces the manufacture difficulty of test structure.
Additionally provide a kind of method adopting above-mentioned test structure in the embodiment of the present invention, comprising:
There is provided test structure, described test structure comprises: Semiconductor substrate, is positioned at the silicon through hole interconnect structure of Semiconductor substrate; Cover the dielectric layer of described Semiconductor substrate; Be arranged in the first metal interconnecting layer be separated from each other and second metal interconnecting layer of dielectric layer, the aluminum metal layer that described first metal interconnecting layer and the second metal interconnecting layer comprise the second diffusion impervious layer and be positioned on the second diffusion impervious layer, described first metal interconnecting layer is connected with the surface of silicon through hole interconnect structure, second metal interconnecting layer shape is annular, and the first metal interconnecting layer is positioned at annular; The first test lead be connected with the first metal interconnecting layer; The second test lead be connected with the second metal interconnecting layer;
First test lead is connected power end, the second test lead ground connection;
Measure the leakage current value between acquisition first test lead and the second test lead;
When leakage current value be greater than reference current value time, then there is the defect that ruptures in the second diffusion impervious layer between silicon through hole interconnect structure and the first metal interconnecting layer.
The voltage swing of described power end is 1 ~ 20 volt, and the size of described reference current value is 1E-6 ~ 9E-6 peace.
In other embodiments of the invention, when the second metal interconnecting layer of described annular comprises at least two discrete son annulars, discrete at least two sub-annular rings are around described the first metal layer, described second test lead comprises some sub-test leads, the quantity of sub-test lead is equal with the quantity of subring shape, and every sub-test lead is connected with corresponding subring shape, every sub-test lead ground connection; Test the electric current between the first test lead and every sub-test lead respectively, obtain some sub-measuring currents, when a certain sub-measuring current is greater than reference current value, then there is the defect that ruptures in the second corresponding with this subring shaped position diffusion barrier layer region.
The embodiment of the present invention additionally provides a kind of formation method of above-mentioned test structure, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, forms silicon through hole interconnect structure;
Form the first metal interconnecting layer and the second metal interconnecting layer that are separated from each other on the semiconductor substrate, the aluminum metal layer that described first metal interconnecting layer and the second metal interconnecting layer comprise the second diffusion impervious layer and be positioned on the second diffusion impervious layer, described first metal interconnecting layer is connected with the surface of silicon through hole interconnect structure, second metal interconnecting layer shape is annular, and the first metal interconnecting layer is positioned at annular;
Form the dielectric layer covering described first metal interconnecting layer, the second metal interconnecting layer and Semiconductor substrate;
Form the first test lead be connected with the first metal interconnecting layer, the second test lead be connected with the second metal interconnecting layer.
To sum up, test structure of the embodiment of the present invention and forming method thereof, method of testing, can in the manufacture craft of interpretation silicon through hole interconnect structure accurately, whether the second diffusion impervious layer contacted with silicon through hole interconnect structure exists fracture defect, and accurately can locate the relative position of this fracture defect.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (15)
1. a test structure, is characterized in that, comprising:
Semiconductor substrate, is positioned at the silicon through hole interconnect structure of Semiconductor substrate;
Cover the dielectric layer of described Semiconductor substrate;
Be arranged in the first metal interconnecting layer be separated from each other and second metal interconnecting layer of dielectric layer, the aluminum metal layer that described first metal interconnecting layer and the second metal interconnecting layer comprise the second diffusion impervious layer and be positioned on the second diffusion impervious layer, described first metal interconnecting layer is connected with the surface of silicon through hole interconnect structure, second metal interconnecting layer shape is annular, and the first metal interconnecting layer is positioned at annular;
The first test lead be connected with the first metal interconnecting layer;
The second test lead be connected with the second metal interconnecting layer.
2. test structure as claimed in claim 1, it is characterized in that, described silicon through hole interconnect structure comprise the through hole being positioned at Semiconductor substrate, the insulating barrier being positioned at through-hole side wall and bottom, be positioned at surface of insulating layer the first diffusion impervious layer and to be positioned on diffusion impervious layer and the copper metal layer of filling vias.
3. test structure as claimed in claim 1, it is characterized in that, described first metal interconnecting layer is positioned at directly over silicon through hole interconnect structure, and the size of the first metal interconnecting layer is greater than the size of silicon through hole interconnect structure.
4. test structure as claimed in claim 3, it is characterized in that, the edge of described first metal interconnecting layer and the distance at silicon through hole interconnect structure edge are 4 ~ 6 microns.
5. test structure as claimed in claim 1, it is characterized in that, described first metal interconnecting layer is positioned at the center of the annular of the second metal interconnecting layer.
6. test structure as claimed in claim 5, it is characterized in that, the distance between described first metal interconnecting layer and the second metal interconnecting layer is 3 ~ 5 microns.
7. test structure as claimed in claim 1, is characterized in that, the second metal interconnecting layer of described annular comprises at least two discrete son annulars, and discrete at least two sub-annular rings are around described first metal interconnecting layer.
8. test structure as claimed in claim 7, it is characterized in that, described second test lead comprises some sub-test leads, and the quantity of sub-test lead is equal with the quantity of subring shape, and every sub-test lead is connected with corresponding subring shape.
9. test structure as claimed in claim 7, it is characterized in that, the radian of each subring shape is equal, and equal angular around described first metal interconnecting layer.
10. a method of testing, is characterized in that, comprising:
There is provided test structure, described test structure comprises: Semiconductor substrate, is positioned at the silicon through hole interconnect structure of Semiconductor substrate; Cover the dielectric layer of described Semiconductor substrate; Be arranged in the first metal interconnecting layer be separated from each other and second metal interconnecting layer of dielectric layer, the aluminum metal layer that described first metal interconnecting layer and the second metal interconnecting layer comprise the second diffusion impervious layer and be positioned on the second diffusion impervious layer, described first metal interconnecting layer is connected with the surface of silicon through hole interconnect structure, second metal interconnecting layer shape is annular, and the first metal interconnecting layer is positioned at annular; The first test lead be connected with the first metal interconnecting layer; The second test lead be connected with the second metal interconnecting layer;
First test lead is connected power end, the second test lead ground connection;
Measure the leakage current value between acquisition first test lead and the second test lead;
When leakage current value be greater than reference current value time, then there is the defect that ruptures in the second diffusion impervious layer between silicon through hole interconnect structure and the first metal interconnecting layer.
11. method of testings as claimed in claim 10, is characterized in that, the voltage swing of described power end is 1 ~ 20 volt.
12. method of testings as claimed in claim 11, is characterized in that, the size of described reference current value is 1E-6 ~ 9E-6 peace.
13. method of testings as claimed in claim 10, it is characterized in that, second metal interconnecting layer of described annular comprises at least two discrete son annulars, discrete at least two sub-annular rings are around described the first metal layer, described second test lead comprises some sub-test leads, the quantity of sub-test lead is equal with the quantity of subring shape, and every sub-test lead is connected with corresponding subring shape, every sub-test lead ground connection.
14. method of testings as claimed in claim 13, it is characterized in that, test the electric current between the first test lead and every sub-test lead respectively, obtain some sub-measuring currents, when a certain sub-measuring current is greater than reference current value, then there is the defect that ruptures in the second corresponding with this subring shaped position diffusion barrier layer region.
The formation method of 15. 1 kinds of test structures, is characterized in that, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, forms silicon through hole interconnect structure;
Form the first metal interconnecting layer and the second metal interconnecting layer that are separated from each other on the semiconductor substrate, the aluminum metal layer that described first metal interconnecting layer and the second metal interconnecting layer comprise the second diffusion impervious layer and be positioned on the second diffusion impervious layer, described first metal interconnecting layer is connected with the surface of silicon through hole interconnect structure, second metal interconnecting layer shape is annular, and the first metal interconnecting layer is positioned at annular;
Form the dielectric layer covering described first metal interconnecting layer, the second metal interconnecting layer and Semiconductor substrate;
Form the first test lead be connected with the first metal interconnecting layer, the second test lead be connected with the second metal interconnecting layer.
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| CN106571311A (en) * | 2015-10-10 | 2017-04-19 | 中芯国际集成电路制造(上海)有限公司 | Silicon through hole test device and test method thereof |
| WO2020083284A1 (en) * | 2018-10-22 | 2020-04-30 | Changxin Memory Technologies, Inc. | Through-silicon via crack detecting apparatus, detecting method, and semiconductor device fabrication method having the same |
| US20230008748A1 (en) * | 2021-07-09 | 2023-01-12 | Changxin Memory Technologies, Inc. | Electrical test structure, semiconductor structure and electrical test method |
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| CN106571311B (en) * | 2015-10-10 | 2019-04-26 | 中芯国际集成电路制造(上海)有限公司 | The test device and its test method of through silicon via |
| WO2020083284A1 (en) * | 2018-10-22 | 2020-04-30 | Changxin Memory Technologies, Inc. | Through-silicon via crack detecting apparatus, detecting method, and semiconductor device fabrication method having the same |
| US11531057B2 (en) | 2018-10-22 | 2022-12-20 | Changxin Memory Technologies, Inc. | Through-silicon via crack detecting apparatus, detecting method, and semiconductor device fabrication method having the same |
| US20230008748A1 (en) * | 2021-07-09 | 2023-01-12 | Changxin Memory Technologies, Inc. | Electrical test structure, semiconductor structure and electrical test method |
| WO2023279432A1 (en) * | 2021-07-09 | 2023-01-12 | 长鑫存储技术有限公司 | Electrical test structure, semiconductor structure, and electrical test method |
| US11854915B2 (en) | 2021-07-09 | 2023-12-26 | Changxin Memory Technologies, Inc. | Electrical test structure, semiconductor structure and electrical test method |
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