CN104516710A - Asynchronous cache method, asynchronous cache and integrated circuit - Google Patents
Asynchronous cache method, asynchronous cache and integrated circuit Download PDFInfo
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Abstract
The invention discloses an asynchronous cache method. Address blocks of a first asynchronous cache are coded according to coding of middle portion address blocks and the coding of virtual address blocks of a second asynchronous cache; the depth of the first asynchronous cache is any even number of address blocks which are smaller than the depth of the second asynchronous cache; the state of the first asynchronous cache is determined according to the address block coding indicated through a reading or writing pointer in the data reading and writing process. Meanwhile the invention also discloses the asynchronous cache and an integrated circuit. According to the asynchronous cache method, the asynchronous cache and the integrated circuit, the requirements for the depth of the asynchronous cache can be met, the more waste of the addressing space in the using process of the large depth of asynchronous cache is avoided, the structure is simple, the circuit implementation is easy, the size of the asynchronous cache is reduced as far as possible, and the miniaturization of equipment with the asynchronous cache is facilitated.
Description
Technical field
The present invention relates to caching technology, particularly relate to a kind of asynchronous buffer method, asynchronous buffer device and integrated circuit.
Background technology
FIFO (First Input First Output) buffer is a kind of data buffer of first in first out, the data be introduced into first read from FIFO buffer, exterior read-write address wire is not had compared with RAM, use fairly simple, but can only data be sequentially written in, the sense data of order, can not can be determined read or write certain address of specifying by address wire as normal memory.
FIFO buffer is generally used for the data transmission between different clock-domains, and one end of such as FIFO is AD data acquisition, and the other end is pci bus, so between two different clock zones, FIFO just can be adopted to be used as data buffering.Data-interface in addition for different in width also can use FIFO buffer, and such as monolithic seat in the plane 8 bit data exports, and DSP may be 16 bit data inputs, and FIFO buffer just can be used when single-chip microcomputer is connected with DSP to reach the object of Data Matching.
According to FIFO work clock territory, FIFO buffer can be divided into synchronization fifo buffer and asynchronous FIFO buffer.Synchronization fifo buffer refers to that reading clock and writing clock is same clock, at clock along read-write operation occurring temporarily simultaneously; Asynchronous FIFO buffer refers to that read-write clock is inconsistent, and read-write clock is mutually independently.
For asynchronous FIFO buffer, generally how the depth design of FIFO buffer is become 2^N address block at present, wherein, N is the width of FIFO buffer, but the degree of depth of the FIFO buffer that may need in practical application is often much little than 2^N, such as: the degree of depth of the FIFO buffer of needs is 100, but the FIFO buffer that the degree of depth must be used to be 2^7=128.Like this, the addressing space of FIFO buffer can be wasted, also can increase taking up room of FIFO buffer, be unfavorable for the miniaturization of the equipment using FIFO buffer.
Summary of the invention
For solving the problems of the prior art, the invention provides a kind of asynchronous buffer method, asynchronous buffer device and integrated circuit.
Technical scheme of the present invention is achieved in that
A kind of asynchronous buffer method provided by the invention, the method comprises:
Encode according to the coding of the second asynchronous buffer device center section address block and the address block of coding to the first asynchronous buffer device of virtual address block, the degree of depth of described first asynchronous buffer device is any even number address block of the degree of depth being less than the second asynchronous buffer device;
First asynchronous buffer device, in the process of reading and writing data, determines the state of self according to the coding of the address block reading or writing pointer instruction.
The present invention also provides a kind of first asynchronous buffer device, and the degree of depth of this first asynchronous buffer device is any even number address block of the degree of depth being less than the second asynchronous buffer device, comprising: even number address block, positioning indicator arbitrarily; Wherein,
Described any even number address block be encoded to the coding of the second asynchronous buffer device center section address block and the coding of virtual address block;
Described positioning indicator, is configured in the process of reading and writing data, and determines the state of the first asynchronous buffer device according to the coding of the address block reading or writing pointer instruction.
The present invention also provides a kind of integrated circuit, and this integrated circuit comprises the first asynchronous buffer device, and the degree of depth of this first asynchronous buffer device is any even number address block of the degree of depth being less than the second asynchronous buffer device, comprising: even number address block, positioning indicator arbitrarily; Wherein,
Described any even number address block be encoded to the coding of the second asynchronous buffer device center section address block and the coding of virtual address block;
Described positioning indicator, is configured in the process of reading and writing data, and determines the state of the first asynchronous buffer device according to the coding of the address block reading or writing pointer instruction.
The embodiment of the present invention provides a kind of asynchronous buffer method, asynchronous buffer device and integrated circuit, encode according to the coding of the second asynchronous buffer device center section address block and the address block of coding to the first asynchronous buffer device of virtual address block, the degree of depth of described first asynchronous buffer device is any even number address block of the degree of depth being less than the second asynchronous buffer device, described first asynchronous buffer device, in the process of reading and writing data, determines the state of self according to the coding of the address block reading or writing pointer instruction; So, the degree of depth of asynchronous buffer device can be made more to meet demand, avoid wasting more addressing space when using large degree of depth asynchronous buffer device, and structure is simple, be easy to circuit realiration, reduce the size of asynchronous buffer device as much as possible, be more beneficial to the miniaturization of the equipment using asynchronous buffer device.
Accompanying drawing explanation
The schematic flow sheet of the asynchronous buffer method that Fig. 1 provides for the embodiment of the present invention;
The structural representation of the first asynchronous buffer device that Fig. 2 provides for the embodiment of the present invention;
The structural representation of the driving chip that Fig. 3 provides for the embodiment of the present invention.
Embodiment
In the embodiment of the present invention, encode according to the coding of the second asynchronous buffer device center section address block and the address block of coding to the first asynchronous buffer device of virtual address block, the degree of depth of described first asynchronous buffer device is any even number address block of the degree of depth being less than the second asynchronous buffer device, described first asynchronous buffer device, in the process of reading and writing data, determines the state of self according to the coding of the address block reading or writing pointer instruction.
The first asynchronous buffer device described in the embodiment of the present invention, the second asynchronous buffer device can be all FIFO buffers.
Below by drawings and the specific embodiments, the present invention is described in further detail.
The embodiment of the present invention realizes a kind of asynchronous buffer method, and as shown in Figure 1, the method comprises following step:
Step 101: encode according to the coding of the second asynchronous buffer device center section address block and the address block of coding to the first asynchronous buffer device of virtual address block, the degree of depth of described first asynchronous buffer device is any even number address block of the degree of depth being less than the second asynchronous buffer device;
Concrete, the degree of depth of the first asynchronous buffer device is M address block, the degree of depth of the second asynchronous buffer device is 2^N address block, described M is any even number being less than 2^N, described N is the width of the addressing encoding indicators of the first asynchronous buffer device and the second asynchronous buffer device, by the configuration of class Gray code corresponding for the address block being numbered (2^N-M)/2 ~ ~ 2^N-1-(2^N-M)/2 in the second asynchronous buffer device correspondence to M address block of described first asynchronous buffer device, and by the configuration of class Gray code corresponding for the virtual address block being numbered 2^N+ (2^N-M)/2 ~ ~ 2*2^N-1-(2^N-M)/2 correspondence to M address block of described first asynchronous buffer device.Here, described class Gray code is N+1 position, according to the address block and the virtual address block being numbered 2^N+ (2^N-M)/2 ~ ~ 2*2^N-1-(2^N-M)/2 that are numbered (2^N-M)/2 ~ ~ 2^N-1-(2^N-M)/2 corresponding binary coding conversion obtain, can be specifically:
Bn={b
M，b
M-1，......b
0}
Gn={g
M，g
M-1，......g
0}
Gn=(Bn>>1)^Bn；
Wherein, Bn represents the binary coding of the corresponding pointer of n-th layer address block, b
mb
0represent each bit of binary coding pointer, such as: b
7b
0represent each bit of the binary coding pointer of 8; Gn represents the class Gray code of the corresponding pointer of n-th layer address block, g
mg
0each bit of representation class Gray code pointer, such as: g
7g
0represent each bit of 8 class Gray code pointers; Gn=(Bn>>1) ^Bn represents the transformational relation of binary coding and class Gray code.
Such as: M=100, N=7, the binary coding of all address blocks of the second asynchronous buffer device is converted to class Gray code as shown on the left of table 1, the binary coding of the virtual address block being numbered 128 ~ 255 is converted to class Gray code as shown on the right side of table 1, can the class Gray code being numbered the address block of 14 ~ 113 in the second asynchronous buffer device be configured to the first asynchronous buffer device, and the class Gray code of the virtual address block being numbered 142 ~ 241 is configured to the first asynchronous buffer device, like this, in first asynchronous buffer device 100 address blocks coding with will be numbered the coding of the address block of 14 ~ 113 in the second asynchronous buffer device and be numbered the coding one_to_one corresponding of virtual address block of 142 ~ 241.
Table 1
Step 102: the first asynchronous buffer device, in the process of reading and writing data, determines the state of self according to the coding of the address block reading or writing pointer instruction;
In this step, the described indicating range reading or writing pointer is be numbered (2^N-M)/2 ~ ~ 2^N-1-(2^N-M)/2 address block and class Gray code that virtual 2^N+ (2^N-M)/2 ~ ~ 2*2^N-1-(2^N-M)/2 address block is corresponding in the second asynchronous buffer device, described M is the degree of depth of the first asynchronous buffer device, described N is the width of the addressing encoding indicators of the first asynchronous buffer device and the second asynchronous buffer device, described M is any even number being less than 2^N, when reading or writing pointer and being indicated to class Gray code corresponding to 2^N-1-(2^N-M)/2 address block, read or write pointer upper once read or write after redirect indicate the class Gray code that virtual 2^N+ (2^N-M)/2 address block is corresponding.
Such as: M=100, N=7, as shown in table 1, when reading or writing pointer and being indicated to 113 address block, read or write pointer upper once read or write after redirect indicate 142 address blocks.
Here, the coding of the address block of the coding of the address block that can be indicated by read pointer and write pointer instruction determines the sky of the first asynchronous buffer device or full state, concrete, when the class Gray code of the address block of read pointer instruction is identical with the class Gray code of the address block that write pointer indicates, first asynchronous buffer device is empty, when the front two of read pointer and the class Gray code of the address block that write pointer indicates is contrary, other identical time, the first asynchronous buffer device is full.
In order to realize said method, the embodiment of the present invention also provides a kind of first asynchronous buffer device, the degree of depth of this first asynchronous buffer device is any even number address block of the degree of depth being less than the second asynchronous buffer device, as shown in Figure 2, comprising: even number address block 21, positioning indicator 22 arbitrarily; Wherein,
Described any even number address block 21 be encoded to the coding of the second asynchronous buffer device center section address block and the coding of virtual address block;
Described positioning indicator 22, in the process of reading and writing data, reads or writes according to the appropriate address block that is coded in of the address block reading or writing pointer instruction the state that data determine the first asynchronous buffer device;
The coding of described second asynchronous buffer device center section address block can be specifically be numbered class Gray code corresponding to the address block of (2^N-M)/2 ~ ~ 2^N-1-(2^N-M)/2, described virtual address block be encoded to class Gray code corresponding to the virtual address block being numbered 2^N+ (2^N-M)/2 ~ ~ 2*2^N-1-(2^N-M)/2; Wherein, described M is the degree of depth of the first asynchronous buffer device, and described N is the width of the addressing encoding indicators of the first asynchronous buffer device and the second asynchronous buffer device, and described M is any even number being less than 2^N; Here, described class Gray code is N+1 position, the binary coding conversion corresponding according to the address block and the virtual address block being numbered 2^N+ (2^N-M)/2 ~ ~ 2*2^N-1-(2^N-M)/2 that are numbered (2^N-M)/2 ~ ~ 2^N-1-(2^N-M)/2 obtains, and can be specifically:
Bn={b
M，b
M-1，......b
0}
Gn={g
M，g
M-1，......g
0}
Gn=(Bn>>1)^Bn；
Wherein, Bn represents the binary coding of the corresponding pointer of n-th layer address block, b
mb
0represent each bit of binary coding pointer, such as: b
7b
0represent each bit of the binary coding pointer of 8; Gn represents the class Gray code of the corresponding pointer of n-th layer address block, g
mg
0each bit of representation class Gray code pointer.
It is described that to read or write scope that pointer can indicate be numbered (2^N-M)/2 ~ ~ 2^N-1-(2^N-M)/2 address block and class Gray code that virtual 2^N+ (2^N-M)/2 ~ ~ 2*2^N-1-(2^N-M)/2 address block is corresponding in the second asynchronous buffer device, described M is the degree of depth of the first asynchronous buffer device, described N is the width of the addressing encoding indicators of the first asynchronous buffer device and the second asynchronous buffer device, described M is any even number being less than 2^N, when reading or writing pointer and being indicated to class Gray code corresponding to 2^N-1-(2^N-M)/2 address block, described read-write controller 22 control to read or write pointer upper once read or write after redirect indicate the class Gray code that virtual 2^N+ (2^N-M)/2 address block is corresponding.
Such as: M=100, N=7, as shown in table 1, when reading or writing pointer and being indicated to 113 address block, read or write pointer upper once read or write after redirect indicate 142 address blocks.
Here, the coding of the address block of the coding of the address block that described positioning indicator 23 can be indicated by read pointer and write pointer instruction determines the sky of the first asynchronous buffer device or full state, concrete, when the class Gray code of the address block of read pointer instruction is identical with the class Gray code of the address block that write pointer indicates, indicate the first asynchronous buffer device for empty, when the front two of read pointer and the class Gray code of the address block that write pointer indicates is contrary, other identical time, indicate the first asynchronous buffer device to be full.
Described sky or full state can be zone bits, and as 0 represents empty, 1 represents full.
Based on above-mentioned first asynchronous buffer device, the embodiment of the present invention also provides a kind of integrated circuit, this integrated circuit comprises the first asynchronous buffer device, the degree of depth of this first asynchronous buffer device is any even number address block of the degree of depth being less than the second asynchronous buffer device, as shown in Figure 2, comprising: even number address block 21, positioning indicator 22 arbitrarily; Wherein,
Described any even number address block 21 be encoded to the coding of the second asynchronous buffer device center section address block and the coding of virtual address block;
Described positioning indicator 22, in the process of reading and writing data, reads or writes according to the appropriate address block that is coded in of the address block reading or writing pointer instruction the state that data determine the first asynchronous buffer device;
The coding of described second asynchronous buffer device center section address block can be specifically be numbered class Gray code corresponding to the address block of (2^N-M)/2 ~ ~ 2^N-1-(2^N-M)/2, described virtual address block be encoded to class Gray code corresponding to the virtual address block being numbered 2^N+ (2^N-M)/2 ~ ~ 2*2^N-1-(2^N-M)/2; Wherein, described M is the degree of depth of the first asynchronous buffer device, and described N is the width of the addressing encoding indicators of the first asynchronous buffer device and the second asynchronous buffer device, and described M is any even number being less than 2^N; Here, described class Gray code is N+1 position, the binary coding conversion corresponding according to the address block and the virtual address block being numbered 2^N+ (2^N-M)/2 ~ ~ 2*2^N-1-(2^N-M)/2 that are numbered (2^N-M)/2 ~ ~ 2^N-1-(2^N-M)/2 obtains, and can be specifically:
Bn＝{b
M，b
M-1，......b
0}
Gn={g
M，g
M-1，......g
0}
Gn=(Bn>>1)^Bn；
Wherein, Bn represents the binary coding of the corresponding pointer of n-th layer address block, b
mb
0represent each bit of binary coding pointer, such as: b
7b
0represent each bit of the binary coding pointer of 8; Gn represents the class Gray code of the corresponding pointer of n-th layer address block, g
mg
0each bit of representation class Gray code pointer.
It is described that to read or write scope that pointer can indicate be numbered (2^N-M)/2 ~ ~ 2^N-1-(2^N-M)/2 address block and class Gray code that virtual 2^N+ (2^N-M)/2 ~ ~ 2*2^N-1-(2^N-M)/2 address block is corresponding in the second asynchronous buffer device, described M is the degree of depth of the first asynchronous buffer device, described N is the width of the addressing encoding indicators of the first asynchronous buffer device and the second asynchronous buffer device, described M is any even number being less than 2^N, when reading or writing pointer and being indicated to class Gray code corresponding to 2^N-1-(2^N-M)/2 address block, described read-write controller 22 control to read or write pointer upper once read or write after redirect indicate the class Gray code that virtual 2^N+ (2^N-M)/2 address block is corresponding.
Such as: M=100, N=7, as shown in table 1, when reading or writing pointer and being indicated to 113 address block, read or write pointer upper once read or write after redirect indicate 142 address blocks.
Here, the coding of the address block of the coding of the address block that described positioning indicator 23 can be indicated by read pointer and write pointer instruction determines the sky of the first asynchronous buffer device or full state, concrete, when the class Gray code of the address block of read pointer instruction is identical with the class Gray code of the address block that write pointer indicates, indicate the first asynchronous buffer device for empty, when the front two of read pointer and the class Gray code of the address block that write pointer indicates is contrary, other identical time, indicate the first asynchronous buffer device to be full.
Described sky or full state can be zone bits, and as 0 represents empty, 1 represents full.
In one embodiment, described integrated circuit is driving chip, as shown in Figure 3, this driving chip, except comprising above-mentioned first asynchronous buffer device 31, also comprises: I2C is from equipment 32, digital to analog converter 33, amplifier 34, write signal generator 35, read signal generator 36, oscillator 37, wherein, oscillator 37 is to write signal generator 35, read signal generator 36 provides clock, I2C is from equipment receiving data, data are sent to the first asynchronous buffer device 31, first asynchronous buffer device 31 is when receiving the write signal that write signal generator 35 produces, the data that write I2C transmits from equipment, when receiving the read signal that read signal generator 36 produces, sense data, and the data of reading sent to digital to analog converter 33 to carry out digital-to-analog conversion, obtain simulating signal, amplifier 34 amplifies described simulating signal, wherein, the degree of depth of described first asynchronous buffer device 31 is any even number address block of the degree of depth being less than the second asynchronous buffer device, as shown in Figure 2, comprise: even number address block 21 arbitrarily, positioning indicator 22, wherein,
Described any even number address block 21 be encoded to the coding of the second asynchronous buffer device center section address block and the coding of virtual address block;
Described positioning indicator 22, in the process of reading and writing data, reads or writes according to the appropriate address block that is coded in of the address block reading or writing pointer instruction the state that data determine the first asynchronous buffer device;
The coding of described second asynchronous buffer device center section address block can be specifically be numbered class Gray code corresponding to the address block of (2^N-M)/2 ~ ~ 2^N-1-(2^N-M)/2, described virtual address block be encoded to class Gray code corresponding to the virtual address block being numbered 2^N+ (2^N-M)/2 ~ ~ 2*2^N-1-(2^N-M)/2; Wherein, described M is the degree of depth of the first asynchronous buffer device, and described N is the width of the addressing encoding indicators of the first asynchronous buffer device and the second asynchronous buffer device, and described M is any even number being less than 2^N; Here, described class Gray code is N+1 position, the binary coding conversion corresponding according to the address block and the virtual address block being numbered 2^N+ (2^N-M)/2 ~ ~ 2*2^N-1-(2^N-M)/2 that are numbered (2^N-M)/2 ~ ~ 2^N-1-(2^N-M)/2 obtains, and can be specifically:
Bn={b
M，b
M-1，......b
0}
Gn={g
M，g
M-1，......g
0}
Gn=(Bn>>1)^Bn；
Wherein, Bn represents the binary coding of the corresponding pointer of n-th layer address block, b
mb
0represent each bit of binary coding pointer, such as: b
7b
0represent each bit of the binary coding pointer of 8; Gn represents the class Gray code of the corresponding pointer of n-th layer address block, g
mg
0each bit of representation class Gray code pointer.
It is described that to read or write scope that pointer can indicate be numbered (2^N-M)/2 ~ ~ 2^N-1-(2^N-M)/2 address block and class Gray code that virtual 2^N+ (2^N-M)/2 ~ ~ 2*2^N-1-(2^N-M)/2 address block is corresponding in the second asynchronous buffer device, described M is the degree of depth of the first asynchronous buffer device, described N is the width of the addressing encoding indicators of the first asynchronous buffer device and the second asynchronous buffer device, described M is any even number being less than 2^N, when reading or writing pointer and being indicated to class Gray code corresponding to 2^N-1-(2^N-M)/2 address block, described read-write controller 22 control to read or write pointer upper once read or write after redirect indicate the class Gray code that virtual 2^N+ (2^N-M)/2 address block is corresponding.
Such as: M=100, N=7, as shown in table 1, when reading or writing pointer and being indicated to 113 address block, read or write pointer upper once read or write after redirect indicate 142 address blocks.
Here, the coding of the address block of the coding of the address block that described positioning indicator 23 can be indicated by read pointer and write pointer instruction determines the sky of the first asynchronous buffer device or full state, concrete, when the class Gray code of the address block of read pointer instruction is identical with the class Gray code of the address block that write pointer indicates, indicate the first asynchronous buffer device for empty, when the front two of read pointer and the class Gray code of the address block that write pointer indicates is contrary, other identical time, indicate the first asynchronous buffer device to be full.
Described sky or full state can be zone bits, and as 0 represents empty, 1 represents full.
In sum, the present invention can provide a kind of asynchronous buffer device of any even number address block of the degree of depth, the degree of depth of asynchronous buffer device can be made more to meet demand, when avoiding using large degree of depth asynchronous buffer device, waste more addressing space, and structure is simple, is easy to circuit realiration, reduce the size of asynchronous buffer device as much as possible, be more beneficial to the miniaturization of the equipment using asynchronous buffer device.
The above, be only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention.
Claims (15)
1. an asynchronous buffer method, is characterized in that, the method comprises:
Encode according to the coding of the second asynchronous buffer device center section address block and the address block of coding to the first asynchronous buffer device of virtual address block, the degree of depth of described first asynchronous buffer device is any even number address block of the degree of depth being less than the second asynchronous buffer device;
First asynchronous buffer device, in the process of reading and writing data, determines the state of self according to the coding of the address block reading or writing pointer instruction.
2. asynchronous buffer method according to claim 1, is characterized in that, the described address block of coding to the first asynchronous buffer device according to the second asynchronous buffer device center section address block is encoded to:
The degree of depth of the first asynchronous buffer device is M address block, the degree of depth of the second asynchronous buffer device is 2^N address block, described M is any even number being less than 2^N, described N is the width of the addressing encoding indicators of the first asynchronous buffer device and the second asynchronous buffer device, by the configuration of class Gray code corresponding for the address block being numbered (2^N-M)/2 ~ ~ 2^N-1-(2^N-M)/2 in the second asynchronous buffer device correspondence to M address block of described first asynchronous buffer device, and by the configuration of class Gray code corresponding for the virtual address block being numbered 2^N+ (2^N-M)/2 ~ ~ 2*2^N-1-(2^N-M)/2 correspondence to M address block of described first asynchronous buffer device.
3. asynchronous buffer method according to claim 2, it is characterized in that, described in read or write pointer indicating range be in the second asynchronous buffer device, be numbered (2^N-M)/2 ~ ~ 2^N-1-(2^N-M)/2 address block and class Gray code that virtual 2^N+ (2^N-M)/2 ~ ~ 2*2^N-1-(2^N-M)/2 address block is corresponding.
4. asynchronous buffer method according to claim 3, it is characterized in that, the method also comprises:
When reading or writing pointer and being indicated to class Gray code corresponding to 2^N-1-(2^N-M)/2 address block, read or write pointer upper once read or write after redirect indicate the class Gray code that virtual 2^N+ (2^N-M)/2 address block is corresponding.
5. asynchronous buffer method according to claim 4, is characterized in that, the coding of the described address block according to reading or writing pointer instruction determines that the state of self is:
When the class Gray code of the address block of read pointer instruction is identical with the class Gray code of the address block that write pointer indicates, first asynchronous buffer device is empty, when the front two of read pointer and the class Gray code of the address block that write pointer indicates is contrary, other identical time, the first asynchronous buffer device is full.
6. a first asynchronous buffer device, is characterized in that, the degree of depth of this first asynchronous buffer device is any even number address block of the degree of depth being less than the second asynchronous buffer device, comprising: even number address block, positioning indicator arbitrarily; Wherein,
Described any even number address block be encoded to the coding of the second asynchronous buffer device center section address block and the coding of virtual address block;
Described positioning indicator, is configured in the process of reading and writing data, and determines the state of the first asynchronous buffer device according to the coding of the address block reading or writing pointer instruction.
7. the first asynchronous buffer device according to claim 6, it is characterized in that, the class Gray code that the address block that being encoded to of described second asynchronous buffer device center section address block is numbered (2^N-M)/2 ~ ~ 2^N-1-(2^N-M)/2 is corresponding;
Described virtual address block be encoded to class Gray code corresponding to the virtual address block being numbered 2^N+ (2^N-M)/2 ~ ~ 2*2^N-1-(2^N-M)/2;
Wherein, described M is the degree of depth of the first asynchronous buffer device, and described N is the width of the addressing encoding indicators of the first asynchronous buffer device and the second asynchronous buffer device, and described M is any even number being less than 2^N.
8. the first asynchronous buffer device according to claim 7, it is characterized in that, described in read or write pointer indicating range be in the second asynchronous buffer device, be numbered (2^N-M)/2 ~ ~ 2^N-1-(2^N-M)/2 address block and class Gray code that virtual 2^N+ (2^N-M)/2 ~ ~ 2*2^N-1-(2^N-M)/2 address block is corresponding.
9. the first asynchronous buffer device according to claim 8, it is characterized in that, the described pointer that reads or writes is when being indicated to class Gray code corresponding to 2^N-1-(2^N-M)/2 address block, upper once read or write after redirect indicate the class Gray code that virtual 2^N+ (2^N-M)/2 address block is corresponding.
10. the first asynchronous buffer device according to claim 9, it is characterized in that, described positioning indicator, also be configured to when the class Gray code of the address block of read pointer instruction is identical with the class Gray code of the address block that write pointer indicates, indicate the first asynchronous buffer device for empty, when the front two of read pointer and the class Gray code of the address block that write pointer indicates is contrary, other identical time, indicate the first asynchronous buffer device to be full.
11. 1 kinds of integrated circuit, is characterized in that, this integrated circuit comprises the first asynchronous buffer device, and the degree of depth of this first asynchronous buffer device is any even number address block of the degree of depth being less than the second asynchronous buffer device, comprising: even number address block, positioning indicator arbitrarily; Wherein,
Described any even number address block be encoded to the coding of the second asynchronous buffer device center section address block and the coding of virtual address block;
Described positioning indicator, is configured in the process of reading and writing data, and determines the state of the first asynchronous buffer device according to the coding of the address block reading or writing pointer instruction.
12. integrated circuit according to claim 11, it is characterized in that, the class Gray code that the address block that being encoded to of described second asynchronous buffer device center section address block is numbered (2^N-M)/2 ~ ~ 2^N-1-(2^N-M)/2 is corresponding;
Described virtual address block be encoded to class Gray code corresponding to the virtual address block being numbered 2^N+ (2^N-M)/2 ~ ~ 2*2^N-1-(2^N-M)/2;
Wherein, described M is the degree of depth of the first asynchronous buffer device, and described N is the width of the addressing encoding indicators of the first asynchronous buffer device and the second asynchronous buffer device, and described M is any even number being less than 2^N.
13. integrated circuit according to claim 12, it is characterized in that, described in read or write pointer indicating range be in the second asynchronous buffer device, be numbered (2^N-M)/2 ~ ~ 2^N-1-(2^N-M)/2 address block and class Gray code that virtual 2^N+ (2^N-M)/2 ~ ~ 2*2^N-1-(2^N-M)/2 address block is corresponding.
14. integrated circuit according to claim 13, it is characterized in that, the described pointer that reads or writes is when being indicated to class Gray code corresponding to 2^N-1-(2^N-M)/2 address block, upper once read or write after redirect indicate the class Gray code that virtual 2^N+ (2^N-M)/2 address block is corresponding.
15. integrated circuit according to claim 14, it is characterized in that, described positioning indicator, also be configured to when the class Gray code of the address block of read pointer instruction is identical with the class Gray code of the address block that write pointer indicates, indicate the first asynchronous buffer device for empty, when the front two of read pointer and the class Gray code of the address block that write pointer indicates is contrary, other identical time, indicate the first asynchronous buffer device to be full.
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|---|---|---|---|
| CN201310455730.6A CN104516710A (en) | 2013-09-26 | 2013-09-26 | Asynchronous cache method, asynchronous cache and integrated circuit |
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| CN201310455730.6A CN104516710A (en) | 2013-09-26 | 2013-09-26 | Asynchronous cache method, asynchronous cache and integrated circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110427168A (en) * | 2019-06-26 | 2019-11-08 | 天津芯海创科技有限公司 | A kind of method and device of asynchronous FIFO that realizing any depth low transmission delay |
| CN112114934A (en) * | 2016-08-17 | 2020-12-22 | 超威半导体公司 | Method and apparatus for power reduction in multi-thread programming mode |
-
2013
- 2013-09-26 CN CN201310455730.6A patent/CN104516710A/en active Pending
Non-Patent Citations (3)
| Title |
|---|
| 刘国栋等: "《第十四届计算机工程与工艺会议》", 20 August 2010 * |
| 彭莉等: ""异步FIFO的设计与验证"", 《计算机工程与应用》 * |
| 陈效军等: ""任意深度的异步FIFO设计"", 《合肥学院学报（自然科学版）》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112114934A (en) * | 2016-08-17 | 2020-12-22 | 超威半导体公司 | Method and apparatus for power reduction in multi-thread programming mode |
| CN112114934B (en) * | 2016-08-17 | 2024-07-09 | 超威半导体公司 | Method and apparatus for power reduction in multi-threaded mode |
| CN110427168A (en) * | 2019-06-26 | 2019-11-08 | 天津芯海创科技有限公司 | A kind of method and device of asynchronous FIFO that realizing any depth low transmission delay |
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