CN104503431A - Magnetic torquer electric simulator with function of fault simulation - Google Patents
Magnetic torquer electric simulator with function of fault simulation Download PDFInfo
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- CN104503431A CN104503431A CN201410705537.8A CN201410705537A CN104503431A CN 104503431 A CN104503431 A CN 104503431A CN 201410705537 A CN201410705537 A CN 201410705537A CN 104503431 A CN104503431 A CN 104503431A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B23/00—Testing or monitoring of control systems or parts thereof
- G05B23/02—Electric testing or monitoring
- G05B23/0205—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
- G05B23/0218—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterised by the fault detection method dealing with either existing or incipient faults
- G05B23/0243—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterised by the fault detection method dealing with either existing or incipient faults model based detection method, e.g. first-principles knowledge model
Abstract
The invention discloses a magnetic torquer electric simulator with a function of fault simulation, and relates to the field of satellite simulation tests. The invention solves a problem that a conventional mini satellite attitude control system is short of a device for simulating a fault function of a magnetic torquer. Three TTL receiving interfaces are respectively connected with three input ends of an input signal isolation circuit, and three output ends of the input signal isolation circuit are respectively connected with three input ends of an FPGA. The output end of a G485 fault receiving interface is connected with the input end of the FPGA, and the FPGA is sued for analyzing the type of a fault and achieving the pulse width collection and time delay of three-channel fault data. The three output ends of the FPGA are respectively connected with three input ends of an output signal isolation circuit, and three output ends of the output signal isolation circuit are respectively connected with three input ends of a drive amplification circuit. Three output ends of the drive amplification circuit are respectively connected with the input ends of three TTL transmitting interfaces. The simulator can be used for the semi-physical simulation and testing of a mini satellite attitude control subsystem.
Description
Technical field
The present invention relates to a kind of design of magnetic torquer electric simulator.Belong to satellite simulation field tests.
Background technology
In Micro-Satellite Attitude Control subsystem, along with the development of satellite technology, moonlet proposes more requirement in volume, weight, power consumption, magnetic torquer has advantage in this regard, add that perfect, the remanent magnetism of geomagnetic model compensates, the development of spaceborne computer software algorithm and satellite with Active Magnetic Control technology, magnetic torquer is widely applied in satellite gravity anomaly and has had remarkable progress.Magnetic torquer, as a kind of topworks of small satellite attitude control, is mainly used in carrying out momentum discharge to flywheel.Its principle of work is as follows: three-axis magnetorquer is made up of three power circuits and corresponding driving circuit, respectively power circuit is installed at satellite body coordinate X, Y, Z tri-orthogonal directionss, satellite body is fixed on by mounting bracket, its relies on the size and Orientation of electric current in control coil to produce corresponding magnetic moment, and the magnetic moment of generation and terrestrial magnetic field interact the magnetic torque producing and control the attitude of satellite.Magnetic torquer external interface General Principle block diagram as shown in Figure 1.Fig. 1 describes magnetic torquer and the interface relationship between spaceborne computer, star power source and telemetry system.In figure: star power source is drive circuitry; Spaceborne computer provides magnetic moment control signal for driving circuit, and this signal is generally the voltage analog of 3 road ﹣ 5 ~ ﹢ 5V; Driving circuit is then the signal receiving spaceborne computer output, by the amplification of driving circuit, be energized the corresponding voltage required for coil, the voltage being added in coil two ends converts the exciting curent needed for coil real work to by coil self-resistance, and then makes coil produce corresponding magnetic moment; The effect of bar magnet is exactly produce magnetic moment, and the output of bar magnet coil is generally the voltage analog of 0 ~ ﹢ 5V, and requires to have certain corresponding relation with exciting curent; Signal conversion circuit adopts A/D sample chip usually, and its function is the size and Orientation of the exciting curent that reflection driving circuit exports, and carries out overvoltage protection; The telesignalisation that telechirics exports for receiving bar magnet coil, is used for reflecting the state of exciting curent.
Summary of the invention
The present invention is to solve the problem lacking the analogue means to magnetic torquer fault function in existing Micro-Satellite Attitude Control subsystem.The magnetic torquer electric simulator with fault simulating function and the fault detection method adopting this electric simulator to realize now are provided.
There is the magnetic torquer electric simulator of fault simulating function, it comprises a TTL receiving interface, No. two TTL receiving interfaces, No. three TTL receiving interfaces, G485 fault receiving interface, input signal buffer circuit, FPGA, output signal buffer circuit, drive amplification circuit, TTL transmission interface, No. two TTL transmission interfaces and No. three TTL transmission interfaces
A described TTL receiving interface, No. two TTL receiving interfaces and the parallel data signal output terminal of No. three TTL receiving interfaces are connected the parallel data signal input end of input signal buffer circuit respectively, 3 tunnel isolation signals output terminals of input signal buffer circuit connect the 3 tunnel isolation signals input ends of FPGA respectively, the direct fault location signal output part of G485 fault receiving interface connects the direct fault location signal input part of FPGA
FPGA is used for resolve fault type, carries out pulsewidth collection and time delays according to fault type to 3 road fault datas,
The 3 tunnel control signal output terminals of FPGA connect 3 tunnel control signal input ends of output signal buffer circuit respectively, 3 tunnel isolation signals output terminals of output signal buffer circuit connect 3 tunnel isolation signals input ends of drive amplification circuit respectively, and 3 road drive singal output terminals of drive amplification circuit connect the driving signal input of the driving signal input of a TTL transmission interface, the driving signal input of No. two TTL transmission interfaces and No. three TTL transmission interfaces respectively.
Have the magnetic torquer electric simulator of fault simulating function, FPGA adopts the mode of state machine to realize:
FPGA inside comprises idle condition, fault handling state, Gather and input pulsewidth state, delay state and output state,
When idle condition has received fault data injection, jump to fault handling state;
When fault handling state receives the complete signal of fault handling, parse fault data type, jump to idle condition;
When idle condition receive input signal have a saltus step time, jump to Gather and input pulsewidth state;
After Gather and input pulsewidth state receives collection, jump to delay state,
When delay state receives after delay time terminates, jump to output state,
Idle condition is entered after exporting TTL signal.
There is the magnetic torquer electric simulator of fault simulating function, the fault data that idle condition receives is injected to 6 bytes, byte 1 to byte 4 is delay time, byte 5 is fault data type, byte 6 is fault-time, fault data type is 7 types, fault data Class1 is data bit 0x00, fault data type 2 is data bit 0x01, fault data type 3 is data bit 0x02, and fault data type 4 is data bit 0x03, and fault data type 5 is data bit 0x04, fault data type 6 is data bit 0x05, and fault data type 7 is data bit 0x06.
There is the magnetic torquer electric simulator of fault simulating function,
When fault handling state receives the complete signal of fault handling, parsing fault data type is data bit 0x00, jumps to idle condition,
When idle condition receives Gather and input Transistor-Transistor Logic level pulse width signal, export between Late phase is seasonable, electric simulator is in normal operating conditions;
When fault handling state receives the complete signal of fault handling, parsing fault data type is data bit 0x01, jumps to idle condition,
When idle condition receives Gather and input Transistor-Transistor Logic level pulsewidth, export TTL and export relative to the double delay time under input time delay normal condition;
When fault handling state receives the complete signal of fault handling, parsing fault data type is data bit 0x02, jumps to idle condition,
When idle condition receives Gather and input Transistor-Transistor Logic level pulsewidth, export TTL negative edge and relatively input the corresponding time output of TTL rising edge time delay;
When fault handling state receives the complete signal of fault handling, parsing fault data type is data bit 0x03, jumps to idle condition,
When idle condition receives Gather and input Transistor-Transistor Logic level pulsewidth, export the half that TTL pulsewidth is input TTL pulsewidth, without time delay;
When fault handling state receives the complete signal of fault handling, parsing fault data type is data bit 0x04, jumps to idle condition,
When idle condition receives Gather and input Transistor-Transistor Logic level pulsewidth, export 2 times that TTL pulsewidth is input TTL pulsewidth, without time delay;
When fault handling state receives the complete signal of fault handling, parsing fault data type is data bit 0x05, jumps to idle condition,
When idle condition receives Gather and input Transistor-Transistor Logic level pulsewidth, it is anti-phase that output TTL inputs TTL relatively, without time delay;
When fault handling state receives the complete signal of fault handling, parsing fault data type is data bit 0x06, jumps to idle condition,
When idle condition receives Gather and input Transistor-Transistor Logic level pulsewidth, export TTL and relatively input TTL homophase, without time delay.
Beneficial effect of the present invention is: adopt a TTL receiving interface, No. two TTL receiving interfaces and No. three TTL receiving interfaces to receive signal on star, G485 fault receiving interface is adopted to receive 485 direct fault location signals, the 485 direct fault location signals received by FPGA carry out pulsewidth collection and time delay to control signal on 3 road stars, result is carried out signal isolation and signal amplification, finally by a TTL transmission interface, No. two TTL transmission interfaces and No. three TTL transmission interfaces, the signal after process is exported, complete the simulation of fault.It can be used for the hardware-in-the-loop simulation of Micro-Satellite Attitude Control subsystem with in test.
Beneficial effect: 1, magnetic torquer analogue means can magnetic torquer on effective star that is virtually reality like reality, pulsewidth collection and time delay are carried out to control signal on 3 road stars, from star control signal is made to form a closed loop to the test access of ground receiver terminals, the shortening equipment R&D cycle, there is economy, safety and reliability.
2, comprise direct fault location passage and the collection of TTL pulsewidth and delay function, and possess the running parameter configurable functionality such as direct fault location and delay time adjustable, effectively can improve the versatility of testing efficiency and electric simulator.
Accompanying drawing explanation
Fig. 1 is magnetic torquer external interface principle schematic,
Fig. 2 is magnetic torquer electric simulator functional schematic,
Fig. 3 is the principle schematic with the magnetic torquer electric simulator of fault simulating function described in embodiment one,
Fig. 4 is the logic diagram of FPGA in the magnetic torquer electric simulator with fault simulating function,
Fig. 5 is the malfunctioning module process flow diagram of the magnetic torquer electric simulator with fault simulating function.
Embodiment
Embodiment one: illustrate present embodiment with reference to Fig. 3, the magnetic torquer electric simulator with fault simulating function described in present embodiment, it comprises a TTL receiving interface 1, No. two TTL receiving interfaces 2, No. three TTL receiving interfaces 3, G485 fault receiving interface 4, input signal buffer circuit 5, FPGA6, output signal buffer circuit 7, drive amplification circuit 8, TTL transmission interface 9, No. two TTL transmission interfaces 10 and No. three TTL transmission interfaces 11
A described TTL receiving interface 1, No. two TTL receiving interfaces 2 and the parallel data signal output terminal of No. three TTL receiving interfaces 3 are connected the parallel data signal input end of input signal buffer circuit 5 respectively, 3 tunnel isolation signals output terminals of input signal buffer circuit 5 connect the 3 tunnel isolation signals input ends of FPGA6 respectively, the direct fault location signal output part of G485 fault receiving interface 4 connects the direct fault location signal input part of FPGA6
FPGA (6), for resolve fault type, carries out pulsewidth collection and time delays according to fault type to 3 road fault datas,
The 3 tunnel control signal output terminals of FPGA (6) connect 3 tunnel control signal input ends of output signal buffer circuit 7 respectively, 3 tunnel isolation signals output terminals of output signal buffer circuit 7 connect 3 tunnel isolation signals input ends of drive amplification circuit 8 respectively, and 3 road drive singal output terminals of drive amplification circuit 8 connect the driving signal input of the driving signal input of a TTL transmission interface 9, the driving signal input of No. two TTL transmission interfaces 10 and No. three TTL transmission interfaces 11 respectively.
In present embodiment, magnetic torquer simulator is mainly used in the test of Micro-Satellite Attitude Control subsystem, substitute magnetic torquer on real star, simulate magnetic torquer driving circuit is passed on 3 roads TTL control signal from spaceborne computer, and driving circuit exports to telemetry system for detecting 3 road TTL telesignalisations of exciting curent, and be transferred to topworks's capture card carry out collection form closed loop, realize the debugging of Micro-Satellite Attitude Control subsystem.The functional schematic of simulator as shown in Figure 2, it possesses 3 road TTL receiving cables and 1 road G485 direct fault location passage, 3 paths can walk abreast and receive the control signal that transmits of spaceborne computer, the 3 road Transistor-Transistor Logic level signals received carry out pulsewidth collection and time delay through FPGA, then telesignalisation are sent by 3 road TTL signal sendaisles.Due in satellite in orbit process, have various failure condition and occur.For above-mentioned situation, this simulator adds a direct fault location passage, simulates the true fault that magnetic torquer occurs in-orbit.Compared with real magnetic torquer, magnetic torquer simulator can replace real magnetic torquer to participate in moonlet ground closed cycle simulation test, effectively reduce the testing cost in satellite ground test process, improve the safety and reliability of test process, and the function of magnetic torquer fault simulation and the reproduction of on-orbit fault ground can be realized.Meanwhile, due to can the inner parameter (such as delay time is adjustable) of on-line tuning analogue means, make simulator have versatility widely, can testing efficiency be improved simultaneously.
In present embodiment, during simulator work, the input of G485 bus failure and 3 road TTL control signals receive simultaneously, 485 fault datas, through the inner FIFO buffer memory of FPGA, after the data fault process of buffer memory, send to FPGA center module to carry out pulsewidth collection and delay process to 3 road TTL signals.
In present embodiment, during electric simulator work, receive 3 road TTL signals and 485 direct fault location signals, 3 paths are parallel receives G485 direct fault location data simultaneously.According to the different fault type parsed, FPGA inputs data to 3 road TTL and carries out corresponding fault handling and pulsewidth collection, and parallel output 3 road TTL outputs signal afterwards.The G485 data-signal injected corresponds to a FIFO buffer memory.During the capacity of the data stored in buffer memory more than frame data, just send request to center cell central processing module, inject fault and carry out respective handling to 3 road TTL signals.
Embodiment two: present embodiment is described further the magnetic torquer electric simulator with fault simulating function described in embodiment one, in present embodiment, the model that input signal buffer circuit 5 adopts NVE company to produce is that the signal isolating chip of IL715 is isolated with carrying out star.
Embodiment three: present embodiment is described further the magnetic torquer electric simulator with fault simulating function described in embodiment one, in present embodiment, the model that output signal buffer circuit 7 adopts AD company to produce is that the pulse transformer isolating chip of ADUM6400 realizes.
Embodiment four: the model that drive amplification circuit 8 adopts TI company to produce is that the eight bus transceiver chips of SN74ABT245DB realize.
Embodiment five: present embodiment is described further the magnetic torquer electric simulator with fault simulating function described in embodiment one, in present embodiment, the model that G485 fault receiving interface 4 adopts TI company to produce is that the bus transceiver of SN65LBC176QD realizes.
Embodiment six: present embodiment is described further the magnetic torquer electric simulator with fault simulating function described in embodiment one, in present embodiment, the model that FPGA6 adopts altera corp to produce is that the fpga chip of EP1C12Q240I7 realizes.
Embodiment seven: the failure simulation method that the magnetic torquer electric simulator with fault simulating function according to embodiment one realizes, during electric simulator work, from a TTL receiving interface 1, No. two TTL receiving interfaces 2, 3 road TTL signals of No. three TTL receiving interface 3 receptions enter FPGA6 by the isolation of input signal buffer circuit 5, the 485 direct fault location data-signals that FPGA6 receives 3 road TTL data-signals simultaneously and sends from G485 fault receiving interface 4, FPGA6 inputs data to 3 road TTL and carries out corresponding fault handling and pulsewidth collection, the different fault type parsed, amplified by the isolation of output signal buffer circuit 7 and the signal of drive amplification circuit 8 afterwards, from a TTL transmission interface 9, No. two TTL transmission interfaces 10 and No. three TTL transmission interface 11 parallel output 3 road TTL output signal.
Embodiment eight: illustrate present embodiment, the magnetic torquer electric simulator with fault simulating function according to embodiment one with reference to Fig. 4, FPGA6 adopts the mode of state machine to realize:
FPGA6 inside comprises idle condition, fault handling state, Gather and input pulsewidth state, delay state and output state,
When idle condition has received fault data injection, jump to fault handling state;
When fault handling state receives the complete signal of fault handling, parse fault data type, jump to idle condition;
When idle condition receive input signal have a saltus step time, jump to Gather and input pulsewidth state;
After Gather and input pulsewidth state receives collection, jump to delay state,
When delay state receives after delay time terminates, jump to output state,
Idle condition is entered after exporting TTL signal.
Embodiment nine: the magnetic torquer electric simulator with fault simulating function according to embodiment eight, the fault data that idle condition receives is injected to 6 bytes, byte 1 to byte 4 is delay time, byte 5 is fault type, byte 6 is fault-time, fault type is 7 types, fault type 1 is data bit 0x00, fault type 2 is data bit 0x01, fault type 3 is data bit 0x02, fault type 4 is data bit 0x03, fault type 5 is data bit 0x04, fault type 6 is data bit 0x05, fault type 7 is data bit 0x06.
In present embodiment, direct fault location module is medium to be sent stored in FPGA inside FIFO by data.Fault data frame is that frame is initial with EB90, and Fault analytical module detects that namely EB90 starts to process fault data, and the result of corresponding magnetic torquer fault is sent to TTL signal processing unit.Magnetic torquer electric simulator direct fault location byte (totally 6 bytes) is as shown in table 1.Byte 1 ~ 4 represents delay time, and the fault simulating function that different faults type parameter is corresponding is as shown in table 2.
Table 1 simulator direct fault location byte
| Byte 1 | Byte 2 | Byte 3 | Byte 4 | Byte 5 | Byte 6 |
| Data1 | Data2 | Data3 | Data4 | Fault type | Fault-time |
Analog functuion corresponding to table 2 different faults type
Embodiment ten: the magnetic torquer electric simulator with fault simulating function according to embodiment seven or eight, when fault handling state receives the complete signal of fault handling, parsing fault data type is data bit 0x00, jumps to idle condition
When idle condition receives Gather and input Transistor-Transistor Logic level pulse width signal, export between Late phase is seasonable, electric simulator is in normal operating conditions;
When fault handling state receives the complete signal of fault handling, parsing fault data type is data bit 0x01, jumps to idle condition,
When idle condition receives Gather and input Transistor-Transistor Logic level pulsewidth, export TTL and export relative to the double delay time under input time delay normal condition;
When fault handling state receives the complete signal of fault handling, parsing fault data type is data bit 0x02, jumps to idle condition,
When idle condition receives Gather and input Transistor-Transistor Logic level pulsewidth, export TTL negative edge and relatively input the corresponding time output of TTL rising edge time delay;
When fault handling state receives the complete signal of fault handling, parsing fault data type is data bit 0x03, jumps to idle condition,
When idle condition receives Gather and input Transistor-Transistor Logic level pulsewidth, export the half that TTL pulsewidth is input TTL pulsewidth, without time delay;
When fault handling state receives the complete signal of fault handling, parsing fault data type is data bit 0x04, jumps to idle condition,
When idle condition receives Gather and input Transistor-Transistor Logic level pulsewidth, export 2 times that TTL pulsewidth is input TTL pulsewidth, without time delay;
When fault handling state receives the complete signal of fault handling, parsing fault data type is data bit 0x05, jumps to idle condition,
When idle condition receives Gather and input Transistor-Transistor Logic level pulsewidth, it is anti-phase that output TTL inputs TTL relatively, without time delay;
When fault handling state receives the complete signal of fault handling, parsing fault data type is data bit 0x06, jumps to idle condition,
When idle condition receives Gather and input Transistor-Transistor Logic level pulsewidth, export TTL and relatively input TTL homophase, without time delay.In present embodiment, have the malfunctioning module process flow diagram of the magnetic torquer electric simulator of fault simulating function as shown in Figure 5, workflow is as follows:
1, after the initialization of simulation dress device completes, wait direct fault location state is entered;
2, in the wait state, moment detection failure is injected, and when direct fault location being detected, starts to resolve fault;
3, the description about fault-time, fault data type is had in fault data byte.Wherein, fault type data are not equal to 0 and trouble duration data are not equal to 0 that to arrange simulator duty be fault;
4, fault verification complete after, according to fault different faults type, input signal is processed;
5, after fault handling, TTL signal is exported;
6, terminate.
Claims (9)
1. there is the magnetic torquer electric simulator of fault simulating function, it is characterized in that, it comprises a TTL receiving interface (1), No. two TTL receiving interfaces (2), No. three TTL receiving interfaces (3), G485 fault receiving interface (4), input signal buffer circuit (5), FPGA (6), output signal buffer circuit (7), drive amplification circuit (8), TTL transmission interface (9), No. two TTL transmission interfaces (10) and No. three TTL transmission interfaces (11)
A described TTL receiving interface (1), No. two TTL receiving interfaces (2) and the parallel data signal output terminal of No. three TTL receiving interfaces (3) are connected the parallel data signal input end of input signal buffer circuit (5) respectively, 3 tunnel isolation signals output terminals of input signal buffer circuit (5) connect the 3 tunnel isolation signals input ends of FPGA (6) respectively, the direct fault location signal output part of G485 fault receiving interface (4) connects the direct fault location signal input part of FPGA (6)
FPGA (6), for resolve fault type, carries out pulsewidth collection and time delays according to fault type to 3 road fault datas,
The 3 tunnel control signal output terminals of FPGA (6) connect 3 tunnel control signal input ends of output signal buffer circuit (7) respectively, 3 tunnel isolation signals output terminals of output signal buffer circuit (7) connect 3 tunnel isolation signals input ends of drive amplification circuit (8) respectively, and 3 road drive singal output terminals of drive amplification circuit (8) connect the driving signal input of the driving signal input of a TTL transmission interface (9), the driving signal input of No. two TTL transmission interfaces (10) and No. three TTL transmission interfaces (11) respectively.
2. the magnetic torquer electric simulator with fault simulating function according to claim 1, is characterized in that, the model that input signal buffer circuit (5) adopts NVE company to produce is that the signal isolating chip of IL715 is isolated with carrying out star.
3. the magnetic torquer electric simulator with fault simulating function according to claim 1, is characterized in that, the model that output signal buffer circuit (7) adopts AD company to produce is that the pulse transformer isolating chip of ADUM6400 realizes.
4. the magnetic torquer electric simulator with fault simulating function according to claim 1, is characterized in that, the model that drive amplification circuit (8) adopts TI company to produce is that the eight bus transceiver chips of SN74ABT245DB realize.
5. the magnetic torquer electric simulator with fault simulating function according to claim 1, is characterized in that, the model that G485 fault receiving interface (4) adopts TI company to produce is that the bus transceiver of SN65LBC176QD realizes.
6. the magnetic torquer electric simulator with fault simulating function according to claim 1, is characterized in that, the model that FPGA (6) adopts altera corp to produce is that the fpga chip of EP1C12Q240I7 realizes.
7. the magnetic torquer electric simulator with fault simulating function according to claim 1, is characterized in that, FPGA (6) adopts the mode of state machine to realize:
FPGA (6) inside comprises idle condition, fault handling state, Gather and input pulsewidth state, delay state and output state,
When idle condition has received fault data injection, jump to fault handling state;
When fault handling state receives the complete signal of fault handling, parse fault data type, jump to idle condition;
When idle condition receive input signal have a saltus step time, jump to Gather and input pulsewidth state;
After Gather and input pulsewidth state receives collection, jump to delay state,
When delay state receives after delay time terminates, jump to output state,
Idle condition is entered after exporting TTL signal.
8. the magnetic torquer electric simulator with fault simulating function according to claim 7, it is characterized in that, the fault data that idle condition receives is injected to 6 bytes, byte 1 to byte 4 is delay time, byte 5 is fault data type, byte 6 is fault-time, fault data type is 7 types, fault data Class1 is data bit 0x00, fault data type 2 is data bit 0x01, fault data type 3 is data bit 0x02, fault data type 4 is data bit 0x03, fault data type 5 is data bit 0x04, fault data type 6 is data bit 0x05, fault data type 7 is data bit 0x06.
9. the magnetic torquer electric simulator with fault simulating function according to claim 7 or 8, is characterized in that,
When fault handling state receives the complete signal of fault handling, parsing fault data type is data bit 0x00, jumps to idle condition,
When idle condition receives Gather and input Transistor-Transistor Logic level pulse width signal, export between Late phase is seasonable, electric simulator is in normal operating conditions;
When fault handling state receives the complete signal of fault handling, parsing fault data type is data bit 0x01, jumps to idle condition,
When idle condition receives Gather and input Transistor-Transistor Logic level pulsewidth, export TTL and export relative to the double delay time under input time delay normal condition;
When fault handling state receives the complete signal of fault handling, parsing fault data type is data bit 0x02, jumps to idle condition,
When idle condition receives Gather and input Transistor-Transistor Logic level pulsewidth, export TTL negative edge and relatively input the corresponding time output of TTL rising edge time delay;
When fault handling state receives the complete signal of fault handling, parsing fault data type is data bit 0x03, jumps to idle condition,
When idle condition receives Gather and input Transistor-Transistor Logic level pulsewidth, export the half that TTL pulsewidth is input TTL pulsewidth, without time delay;
When fault handling state receives the complete signal of fault handling, parsing fault data type is data bit 0x04, jumps to idle condition,
When idle condition receives Gather and input Transistor-Transistor Logic level pulsewidth, export 2 times that TTL pulsewidth is input TTL pulsewidth, without time delay;
When fault handling state receives the complete signal of fault handling, parsing fault data type is data bit 0x05, jumps to idle condition,
When idle condition receives Gather and input Transistor-Transistor Logic level pulsewidth, it is anti-phase that output TTL inputs TTL relatively, without time delay;
When fault handling state receives the complete signal of fault handling, parsing fault data type is data bit 0x06, jumps to idle condition,
When idle condition receives Gather and input Transistor-Transistor Logic level pulsewidth, export TTL and relatively input TTL homophase, without time delay.
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| US20070129922A1 (en) * | 2005-12-01 | 2007-06-07 | Electronics And Telecommunications Research Institute | Satellite simulation system using component-based satellite modeling |
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| US20070129922A1 (en) * | 2005-12-01 | 2007-06-07 | Electronics And Telecommunications Research Institute | Satellite simulation system using component-based satellite modeling |
| CN102436186A (en) * | 2011-11-16 | 2012-05-02 | 清华大学 | Performer simulator and satellite closed loop simulation system with performer simulator |
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Application publication date: 20150408 |