CN105677990A

CN105677990A - Method for simplifying verification model implementation in chip verification

Info

Publication number: CN105677990A
Application number: CN201610015464.9A
Authority: CN
Inventors: 江源
Original assignee: Centec Networks Suzhou Co Ltd
Current assignee: Suzhou Centec Communications Co Ltd
Priority date: 2016-01-11
Filing date: 2016-01-11
Publication date: 2016-06-15
Anticipated expiration: 2036-01-11
Also published as: CN105677990B

Abstract

The invention discloses a method for simplifying verification model implementation in chip verification. According to the method, an excitation generator, a verification model and a design model to be tested are included, the excitation generator is used for generating start signals and corresponding control signals required by a whole message and a processed message, the start signals and the corresponding control signals required by the whole message and the processed message exist in two queues in the excitation generator at the same time, and one of the queues is used for being sent to the design model to be tested; the verification model directly takes data and the control signals from the other queue in the excitation generator, obtains all the control signals required by the whole message and the processed message, can directly process the message data according to the designed requirement, stores the processed data according to the output interface behavior of the designed module to be tested and waits to compare the stored data with the result of design to be tested. By means of the method, implementation of the verification model is simplified, and a great quantity of chip verification time is saved.

Description

A kind of method simplifying checking model realization in chip checking

Technical field

The present invention relates to communication technique field, a kind of method especially relating to simplify checking model realization in chip checking.

Background technology

In current chip checking, it is essentially all traditionally checking framework and builds excitation generator and verify model, as shown in Figure 1. Excitation generator is responsible for producing various excitation, at a time produces what a message in advance and processes the control signal needed for this message, existing in place queue. Input interface temporal aspect according to design to be tested, these message datas and control signal, be divided into different fragments, sends with time order and function order, gives the excitation waveform meeting designing requirement to be tested. Checking model realizes as the software of design to be tested, must be consistent with the behaviour of design to be tested, so checking model is also required to simulate the Interface design of design to be tested, according to the timing requirements that excitation produces, go to receive corresponding data and control signal, for message processing module (MPM), after all the elements needed for a message all receive, more in the lump message is processed.

The verification environment of this conventional architectures is fairly simple, but shortcoming is also apparent from: so can cause that checking model realization is complicated, cost great effort in Interface design, and our checking it is important that the function of design to be tested and behavior, and the Interface design of non-authentication model self. So when verifying that model itself is problematic, himself error detection difficulty is increased, and increase verify model realize difficulty and time overhead, the progress for chip checking is very unfavorable.

Summary of the invention

It is an object of the invention to overcome the defect of prior art, it is provided that a kind of method simplifying checking model realization in chip checking.

For achieving the above object, the present invention proposes following technical scheme: a kind of method simplifying checking model realization in chip checking, it includes excitation generator, checking model and design module to be tested, described excitation generator produces enabling signal, whole message and processes the corresponding control signal needed for message, described enabling signal and whole message and the corresponding control signal needed for processing message are concurrently present in the two places queue encouraged within generator, and wherein place queue is used for being sent to design module to be tested;

While excitation generator has produced data, also enabling signal being set to effectively, now checking model can directly detect this enabling signal, then takes out data from excitation generator and processes;

When checking model inspection to enabling signal is effective, checking model directly directly goes to fetch data and control signal from another queue of excitation generator, checking model has obtained complete message and has processed all control signals required for message, directly message data can be processed according to the requirement of design, output interface behavior further according to design module to be tested, the data processed are stored, waits and the result of design to be tested compares.

Preferably, when design to be tested returns the control signal that can continue to send, excitation generator just can send data.

Preferably, when design to be tested returns the control signal that can not retransmit, excitation generator is necessary for stopping the excitation of design to be tested is sent.

Preferably, the input interface of described design module to be tested is provided with relevant flow control signal, and data can not unconfined send.

Preferably, while excitation generator stops the excitation of design to be tested is sent, the input interface of design to be tested has front and back sequential to contact to relevant data receiver, also need to add time-sequence control mode, for the sequential that complete data require with design interface to be tested being sent inside excitation generator.

The invention has the beneficial effects as follows: the present invention starts based on excitation generator and checking model simultaneously, and the transmission of data and signal is independent of and the interface sequence of design to be tested, thus greatly simplify the realization of checking model, it is also convenient for the error detection of design to be tested, saves the time of a large amount of chip checking.

Accompanying drawing explanation

Fig. 1 is checking configuration diagram in prior art;

Fig. 2 is that the present invention verifies configuration diagram.

Detailed description of the invention

Below in conjunction with the accompanying drawing of the present invention, the technical scheme of the embodiment of the present invention is carried out clear, complete description.

The method simplifying checking model realization in disclosed a kind of chip checking, its core is in that excitation generator and checking model work at synchronization simultaneously, after checking model receives message data, all data just can be handled well in this moment, then it is stored in queue, waits that design output to be tested carries out data time effective and compares.

Now for message processing module (MPM), as in figure 2 it is shown, comprise the following steps:

First, excitation generator is at a time, produce enabling signal, corresponding control signal needed for whole message and process message, these message datas and signal exist in the excitation two places queue within generator simultaneously, wherein place queue is used for being sent to design module to be tested, owing to the input interface of design module to be tested has relevant flow control signal, namely data can not unconfined send, but when design to be tested returns the control signal that can continue to send, excitation generator just can send data, when design module to be tested returns the control signal that can not retransmit, excitation generator is necessary for stopping the excitation of design module to be tested is sent. the input interface of design module to be tested also requires that relevant data receiver has front and back sequential contact simultaneously, so also needing to add time-sequence control mode inside excitation generator, for the sequential that complete data require with design interface to be tested being sent.

Then, the input signal of checking model not transmits from the input interface of design module to be tested, its input and excitation generator internal signal link together, while excitation generator has produced data, also enabling signal can be set to effectively, now checking model can directly detect this enabling signal, then takes out data from excitation generator and processes.

Finally, checking model inspection is effective to enabling signal, now checking model directly directly goes to fetch data and control signal from another queue of excitation generator, without as checking model in conventional architectures, it is necessary to deflorate all data under time-consuming reception according to the timing requirements of interface. Now, checking model has obtained complete message and has processed all control signals required for message, thus can directly message data be processed according to the requirement of design, output interface behavior further according to design module to be tested, the data processed are stored, waits the results contrast with design module to be tested.

The present invention has excitation generator and verifies that model starts the function of work simultaneously, and verifies that model has just processed all operations at synchronization.

The technology contents of the present invention and technical characteristic have revealed that as above; but those of ordinary skill in the art are still potentially based on teachings of the present invention and announcement and do all replacements without departing substantially from spirit of the present invention and modification; therefore; scope should be not limited to the content that embodiment is disclosed; and the various replacement without departing substantially from the present invention and modification should be included, and contained by present patent application claim.

Claims

1. the method simplifying checking model realization in a chip checking, it includes excitation generator, checking model and design module to be tested, it is characterized in that: described excitation generator produces enabling signal, whole message and processes the corresponding control signal needed for message, described enabling signal and whole message and the corresponding control signal needed for processing message are concurrently present in the two places queue encouraged within generator, and wherein place queue is used for being sent to design module to be tested;

2. the method simplifying checking model realization in chip checking according to claim 1, it is characterised in that when design to be tested returns the control signal that can continue to send, excitation generator just can send data.

3. the method simplifying checking model realization in chip checking according to claim 1, it is characterised in that when design to be tested returns the control signal that can not retransmit, excitation generator is necessary for stopping the excitation of design to be tested is sent.

4. the method simplifying checking model realization in chip checking according to claim 1, it is characterised in that the input interface of described design module to be tested is provided with relevant flow control signal, and data can not unconfined send.

5. the method simplifying checking model realization in chip checking according to claim 1, it is characterized in that, while excitation generator stops the excitation of design to be tested is sent, the input interface of design to be tested has front and back sequential to contact to relevant data receiver, also need to add time-sequence control mode, for the sequential that complete data require with design interface to be tested being sent inside excitation generator.