CN104484129A - One-read and one-write memory, multi-read and multi-write memory and read and write methods for memories - Google Patents
One-read and one-write memory, multi-read and multi-write memory and read and write methods for memories Download PDFInfo
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Abstract
The invention discloses a one-read and one-write memory, a multi-read and multi-write memory and read and write methods for the memories. The 1R1W (one-read and one-write) memory comprises (1+N) 1RW (one-read-write) memories, a state memory unit and control logics and has target depths x. Invalid data are stored in x/N addresses of the (N+1) 1RW memories, and the x/N addresses are distributed in the (N+1) 1RW memories. The nRmW (n-read and m-write) memory comprises n*(N+m-1) 1R1W memories and a state memory unit. The state memory unit is used for recording and updating data memory states corresponding to each read address or write address of the 1R1W memory or the nRmW memory, and the control logics are used for controlling read and write operation on the one-read and one-write memory. Compared with the prior art, the one-read and one-write memory, the multi-read and multi-write memory and the read and write methods have the advantages that chip areas and power consumption of the 1R1W memory and the nRmW memory are further reduced, timing convergence is easy to implement, accordingly, the chip costs can be reduced, and the competitiveness of chips can be improved.
Description
Technical field
The present invention relates to the technical field of switch memory reservoir, especially relate to a kind of one and read a memory write and reading/writing method thereof, and be extended to read many memory writes and its implementation more.
Background technology
Realize one of high performance switch internal mass at present and read a memory write (1R1W storer, support read operation simultaneously and write operation), as realized data packet buffer (packet buffer), mainly contain two kinds of ways: a kind of method is stitched together by the 1R1W storer of multiple low capacity, so functionally can realize 1R1W storer, but the memory area after realizing is comparatively large, and power consumption especially can be caused high, the convergence of sequential difficulty; To realize the 1R1W storer of a 16384D540W, because the max cap. of 1R1W storer is limited, need the 1R1W storer of 15 pieces of 16384D36W to cascade up altogether and could realize the storer of one piece of 16384D540W, the power consumption of so multiple 1R1W storer is very large, and sequential is also difficult to convergence.
Another kind method is that employing two pieces jumbo is read or a memory write (1RW storer does not support read operation simultaneously and write operation), adds a small amount of steering logic to realize.Realize the 1R1W storer of 16384D540W equally, need the Large Copacity 1RW storer of two pieces of 16384D540W, add that steering logic controls read-write operation, make read and write operation respectively at different 1RW storeies, thus the 1R1W storer realized based on 1RW storer, this 1R1W storer only adopts two pieces of highdensity 1RW storeies of Large Copacity, can obtain good power consumption, sequential is relatively good convergence also, but can also do on the area of storer and optimize further.
Summary of the invention
The object of the invention is to the defect overcoming prior art, there is provided a kind of one to read a memory write, read many memory writes and reading/writing method thereof more, to read based on one of (1+N) individual 1/N target depth or a memory write realizes one and reads a memory write, read a memory write based on one of (1+N) individual 1/N target depth to realize reading many memory writes more, to reduce chip area, reduce chip power-consumption, thus reduce chip cost, improve chip competitive power.
For achieving the above object, the present invention proposes following technical scheme: a kind of one reads a memory write, described one target depth reading a memory write is x, x be greater than 0 integer, it is characterized in that: comprise (1+N) individual and read or a memory write, state storage unit and steering logic, N be more than or equal to 2 even number, and meeting target depth divided by N is integer, each described one reads or the degree of depth of a memory write is the 1/N of described target depth x, (N+1) individual described 1RW storer has x* (N+1)/N number of address, what wherein x address was deposited is valid data, what x/N address stored is invalid data, and a described x/N Address d istribution is in (N+1) individual described 1RW storer, described state storage unit eachly reads address or state data memory corresponding to write address for recording and upgrading, described steering logic is for controlling the read-write operation that described reads a memory write.
Preferably, described state storage unit is with being less than or equal to [(N+1) * (log
2n rounds+1)] individual bit eachly reads address or state data memory corresponding to write address to record.
Preferably, the storage depth of described state storage unit read with each described one or the storage depth of a memory write identical.
The reading/writing method that another object of the present invention is also to provide a kind of one to read a memory write, comprises the following steps:
S1, described steering logic reads address and state data memory corresponding to write address from described state storage unit;
S2, determines corresponding described one according to the described state data memory read and reads or read data in a memory write, and finds out described reading or memory write write data of can writing.
Preferably, if read data operation and data writing operation are simultaneously, and described in read address and data corresponding to write address and one to read or in a memory write described in same, then data write to be read except one of read data operation correspondence or one except a memory write is read or in a memory write.
Preferably, in step s 2, if described in read address and data corresponding to write address and one to read or in a memory write described in same, then select there is described one of invalid data to read or memory write write data, and upgrade the state data memory that in described state storage unit, write address is corresponding simultaneously; If described in read address and data corresponding to write address and one not read or in a memory write described in same, then directly write data into corresponding one the reading or in a memory write of described write address.
The present invention is based on (1+N) individual 1/N target depth one reads or a memory write, and add certain control logic circuit and state storage unit realize target capacity one reads a memory write.
The present invention can also realize nRmW based on 1R1W storer and read many memory writes more, the target depth of the nRmW storer realized is x, then need n 1RmW storage unit and a state storage unit, each 1RmW storage unit has (N+m-1) individual and reads a memory write, namely the individual 1R1W storer of n* (N+m-1) is altogether needed, wherein x, n, N, m, be the integer being greater than 0, the degree of depth of each one degree of depth and state storage unit reading a memory write is the 1/N of target depth x; State storage unit needs to support simultaneously (m+n) individual read operation and m write operation, for record and upgrade each more read many memory writes nRmW eachly read address or state data memory corresponding to write address.
Time when m write operation and n the read operation of nRmW storer while effectively, n read operation acts on each 1RmW storage unit respectively, and each like this 1RmW storage unit just has m write operation and 1 read operation simultaneously; Read operation or write operation effective time, its correspondence read address or write address is sent to the data mode that state storage unit searches corresponding address, any any can know from block storage reading data and to block storage write data according to the data mode read, write data while and upgrade state storage unit, be effectively by the Data Update of the storer corresponding address of up-to-date write data, so just can realize the nRmW storer based on (N+1) block 1R1W storer.
If the width of nRmW storer is y, then the width of each 1R1W storer is also y, and the width of state storage unit is [(N+m-1) * (log2 (N+m-1) rounds+1)].
Preferably, when (m+n) is greater than 2, available register realizes state storage unit.
The invention has the beneficial effects as follows: what the present invention realized one reads a memory write and read many memory writes more and compare existing one and read a memory write and read many memory writes more, chip area reduces further, power consumption reduces further, sequential is relatively good convergence also, thus reduction chip cost, improve chip competitive power.
Accompanying drawing explanation
Fig. 1 the present invention is based on the configuration diagram that (N+1) block 1RW storer realizes 1R1W storer;
Fig. 2 is the structural representation that the present invention realizes realizing based on 8192 degree of depth 1RW storeies (N=2) 16384 degree of depth 1R1W storeies;
Fig. 3 is the read-write operation schematic flow sheet of 16384 degree of depth 1R1W storeies that the present invention realizes;
Fig. 4 is the configuration diagram that the present invention realizes the nRmW storer realized based on (N+1) block 1R1W storer.
Embodiment
Below in conjunction with accompanying drawing of the present invention, clear, complete description is carried out to the technical scheme of the embodiment of the present invention.
As shown in Figure 1, disclosed one one reads a memory write, comprises (N+1) individual and reads or a memory write 1RW, state storage unit and steering logic, N be more than or equal to 2 even number, and to meet target depth divided by N be integer.If the target depth reading a memory write realized to be x, x be greater than 0 integer, then the degree of depth of each 1RW storer is x/N.(N+1) individual 1RW storer has x* (N+1)/N number of address, and what wherein x address was deposited is valid data, and what x/N address stored is invalid data, and this x/N Address d istribution is in (N+1) individual 1RW storer.
State storage unit eachly reads address or state data memory corresponding to write address for recording and upgrading, and the degree of depth of state storage unit is also x/N, and width is (N+1) * (int (log
2n)+1).Steering logic is used for the read-write operation of the 1R1W storer of control realization.
Be the 1RW storer of 8192 below based on 3 pieces of degree of depth, realize the 1R1W storer that 1 piece of degree of depth is 16384.As shown in Figure 2, these 3 pieces of 1RW storeies are labeled as storer 0 respectively, storer 1 and storer 2.Add certain steering logic, and 1 bulk state storage unit records the data mode of each address in these 3 pieces of 1RW storeies respectively simultaneously.Here address is the write address reading address or write port of read port.
For each block 1RW storer, the data that its any one address is deposited may be the data in 0 ~ 8191 address in 0 ~ 16383 external address space, also may be the data in 8192 ~ 16383 addresses in 0 ~ 16383 external address space, also may be invalid data.
The embodiment of the present invention two bits represent the data mode of a certain piece of any one address of 1RW storer, the data effective information of any one address of such 3 block storages needs 6 bits to represent altogether, and namely the address space of inner 1RW storer 0 ~ 8191 needs that a degree of depth is 8192, width is the state storage unit of 6 altogether.And this state storage unit needs the operation supporting two read ports and a write port simultaneously, due to 1R1W storer have a read-write operation simultaneously time, state storage unit to be arrived simultaneously and read address and data mode corresponding to write address, so state storage unit needs to support two read port operations simultaneously, and write port also will upgrade state storage unit when writing data to 1RW storer, so state storage unit also needs to support a write port operation simultaneously.
What in the embodiment of the present invention, state storage unit recorded 3 pieces of 1RW storeies with 6 bit eachly reads address or state data memory corresponding to write address.Particularly, the highest bit represents the data mode of storer 0, minimum 2bit represents the data mode of storer 2, middle 2bit represents the data mode of storer 1, wherein define respectively again in every two 2bit: the data that what " 10 " represented that this address deposits is in external address 0 ~ 8191, the data that what " 11 " represented that this address deposits is in external address 8192 ~ 16383, what " 00 " then represented that this address deposits is invalid data, the meaning that state data memory as " 101100 " represents is: what deposit in storer 0 is data in external address 0 ~ 8191, what deposit in storer 1 is data in external address 8192 ~ 16383, what deposit in storer 2 is invalid data.
When read port reads data, steering logic goes read states storage unit according to reading address, according to the effective 1RW memory read data of data selection that state storage unit is read.If there is write operation to come while read operation, then write operation can only be selected in other two pieces of 1RW storeies, because other two pieces of 1RW storeies always have the address space of 16K, then necessarily can ensure writing data and can writing and wherein go in a certain piece of 1RW storer of arbitrary address, so just can realize the storer of 1R1W.
Below for the embodiment of the present invention, specifically introduce the read-write operation flow process that of the present invention reads a memory write.As shown in the 1R1W memory read/write process flow diagram of Fig. 3, comprise the following steps:
Step 1, original state, the data in 1R1W storer and state storage unit are all 0;
Step 2, write address 0x0 wanted by 1R1W storer, the raw data reading address 0x0 from state cell is 000000, namely the data of the address 0x0 of three pieces of 1RW storeies are all invalid, storer 0 might as well be preferentially stored into according to the address of address 0-8191 (i.e. 0x0 ~ 0x1ffff), storer 1 is preferentially stored in the address of address 8192-16383 (i.e. 0x2000 ~ 0x3fff), and storer 2 carrys out selection memory write data as the principle of candidate storage device.Then the address 0x0 of selection memory 0 is the write of new data, and the data simultaneously upgrading the address 0x0 of state storage unit are 100000.
Step 3,1R1W storer will read address 0x0, write address 0x1, the data reading address 0x0 inside state storage unit are 100000, namely the data reading address 0x0 from storer 0 are needed, address 0x1 because storer 0 is 1RW storer, namely can only have a read operation or write operation sometime, so can only write storer 1 or storer 2; Write data selection principle, the data of selection memory 2 writing address 0x1 according to step 1, the data simultaneously upgrading state storage unit address 0x1 are 000010;
Step 4,1R1W storer will read address 0x1, write address 0x2001, the data reading address 0x1 from state storage unit are 000010, namely the data of address 0x1 are at storer 2, then selection memory 2 reads address 0x1, write data selection principle according to step 1, selection memory 1 writes the data of 0x2001, and the data upgrading state storage unit address 0x1 are 001110;
Step 5,1R1W reads address 0x2001, write address 0x2000, and the data reading data 001110,0x2001 from state storage unit address 0x1 are stored in storer 1, then read the data of 0x2001 from storer 1; The data simultaneously reading address 0x0 from state cell are 100000, known 0x2000 does not have valid data at present, again because storer 1 is in read operation, then select the address 0x0 of shelf storage 2 to write the data of 0x2000, the data simultaneously upgrading state storage unit address 0x0 are 100011.
What embodiment was set forth above is the scheme of N=2, if above-mentioned example gets N=4, then needs the 1RW storer of 5 pieces of 4096D540W, and principle and N get 2 the same, and all can be realized by the present invention, specific implementation is no longer repeated description herein.
The present invention also realizes nRmW storer based on 1R1W storer, as shown in Figure 4, if realize target storage depth is x, target storage width is the nRmW storer of y, n is read port number, m is write port number, x, y, m, n is the integer being greater than 0, then need n 1RmW storage unit and a state storage unit, each 1RmW storage unit has (N+m-1) individual 1R1W storer, namely the individual 1R1W storer of n* (N+m-1) is altogether needed, wherein x, n, N, m, be the integer being greater than 0, the degree of depth of each 1R1W storer is x/N, width is y, the degree of depth of state storage unit is x/N, width is [(N+m-1) * (log2 (N+m-1) rounds+1)], state storage unit needs to support simultaneously (m+n) individual read operation and m write operation, for record and upgrade each nRmW storer eachly read address or state data memory corresponding to write address.
Preferably, when (m+n) is greater than 2, available register realizes state storage unit.
Time when m write operation and n the read operation of nRmW storer while effectively, n read operation acts on each 1RmW storage unit respectively, and each like this 1RmW storage unit just has m write operation and 1 read operation simultaneously; Read operation or write operation effective time, its correspondence read address or write address is sent to the data mode that state storage unit searches corresponding address, any any can know from block storage reading data and to block storage write data according to the data mode read, write data while and upgrade state storage unit, be effectively by the Data Update of the storer corresponding address of up-to-date write data, so just can realize the nRmW storer based on (N+1) block 1R1W storer.
Certainly, the nRmW storer that the present invention realizes is not limited to realize based on the 1R1W storer of introduction of the present invention, also can directly be realized by existing 1R1W storer.
Following table is adopt conventional method and the present invention to realize the Area comparison of Large Copacity 1R1W storer under the storage chip 32nm technique of IBM, wherein option A is the method realizing Large Copacity 1R1W storer based on low capacity 1R1W storer, option b is the method realizing 1R1W storer based on 2 pieces of 1RW storeies, and scheme C is the method that the present invention realizes 1R1W storer.From following table, the 1R1W memory area adopting the present invention to realize is minimum, and the limited logic simultaneously increased, sequential is relatively good convergence also.
Table one
Technology contents of the present invention and technical characteristic have disclosed as above; but those of ordinary skill in the art still may do all replacement and the modification that do not deviate from spirit of the present invention based on teaching of the present invention and announcement; therefore; scope should be not limited to the content that embodiment discloses; and various do not deviate from replacement of the present invention and modification should be comprised, and contained by present patent application claim.
Claims (9)
1. read a memory write for one kind one, described one target depth reading a memory write is x, x be greater than 0 integer, it is characterized in that: comprise (1+N) individual and read or a memory write, state storage unit and steering logic, N be more than or equal to 2 even number, and meeting target depth divided by N is integer, each described one reads or the degree of depth of a memory write is the 1/N of described target depth x, (N+1) individual described 1RW storer has x* (N+1)/N number of address, what wherein x address was deposited is valid data, what x/N address stored is invalid data, and a described x/N Address d istribution is in (N+1) individual described 1RW storer, described state storage unit eachly reads address or state data memory corresponding to write address for recording and upgrading, described steering logic is for controlling the read-write operation that described reads a memory write.
2. according to claim 1 one read a memory write, it is characterized in that, described state storage unit is with being less than or equal to [(N+1) * (log
2n rounds+1)] individual bit eachly reads address or state data memory corresponding to write address to record.
3. according to claim 1 one read a memory write, it is characterized in that, the storage depth of described state storage unit read with each described one or the storage depth of a memory write identical.
4. according to claim 1 one reading/writing method reading a memory write, is characterized in that, comprise the following steps:
S1, described steering logic reads address and state data memory corresponding to write address from described state storage unit;
S2, determines corresponding described one according to the described state data memory read and reads or read data in a memory write, and finds out described reading or memory write write data of can writing.
5. according to claim 4 one reading/writing method reading a memory write, it is characterized in that, if read data operation and data writing operation are simultaneously, and described in read address and data corresponding to write address and one to read or in a memory write described in same, then data write to be read except one of read data operation correspondence or one except a memory write is read or in a memory write.
6. according to claim 4 or 5 one reading/writing method reading a memory write, it is characterized in that, in step s 2, if described in read address and data corresponding to write address and one to read or in a memory write described in same, then select there is described one of invalid data to read or memory write write data, and upgrade the state data memory that in described state storage unit, write address is corresponding simultaneously; If described in read address and data corresponding to write address and one not read or in a memory write described in same, then directly write data into corresponding one the reading or in a memory write of described write address.
7. one kind based on described in claim 1 one read one memory write realize read many memory writes more, the described target depth reading many memory writes nRmW is x more, it is characterized in that: comprise n 1RmW storage unit and a state storage unit, each described 1RmW storage unit has (N+m-1) individual and reads a memory write, wherein x, n, N, m, be the integer being greater than 0, the degree of depth of each described one degree of depth and described state storage unit reading a memory write is the 1/N of described target depth x, described state storage unit for record and upgrade described read many memory writes eachly read address or state data memory corresponding to write address.
8. according to claim 7ly read many memory writes, it is characterized in that, described state storage unit supports (m+n) individual read operation and m write operation simultaneously more.
9. the reading/writing method reading many memory writes according to claim 7, is characterized in that more, and time when m write operation and n the read operation of described nRmW storer while effectively, n read operation acts on 1RmW storage unit described in each respectively; When the read operation of described nRmW storer or write operation effective time, the corresponding state data memory reading address or write address is read from described state storage unit, determine described one of correspondence according to the described state data memory read to read to read data in a memory write, and find out can write described one read one memory write write data, write data while upgrade store status corresponding to described state storage unit.
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