CN104467803B - A kind of time division duplexed high-rate LVDS port circuits - Google Patents
A kind of time division duplexed high-rate LVDS port circuits Download PDFInfo
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- CN104467803B CN104467803B CN201410681914.9A CN201410681914A CN104467803B CN 104467803 B CN104467803 B CN 104467803B CN 201410681914 A CN201410681914 A CN 201410681914A CN 104467803 B CN104467803 B CN 104467803B
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Abstract
A kind of time division duplexed high-rate LVDS port circuits, the latter linked second level receiving circuit of Primary Receive circuit is controlled by digital controlled signal, the data for receiving Primary Receive circuit are separately sent to different second level receiving circuits as requested, improve Primary Receive percentage of circuit utilization, so as to improve the receiving circuit utilization rate of whole circuit, chip pin number is reduced；Primary Receive circuit is realized by the way of casacade multi-amplifier is cascaded, Primary Receive circuit bandwidth is improved；Second level receiving circuit is realized using with the comparator configuration resetted, is easy to data signal to be controlled, so as in the state of the different multiple second level receiving circuits of SECO, realize the separation of multiple input signals.
Description
Technical field
The present invention relates to a kind of port circuit, particularly a kind of time division duplexed high-rate LVDS port circuits belong to digital-to-analogue and turned
Exchanger technology field.
Background technology
Input port applied to the digital analog converter of the military equipments such as Wireless Telecom Equipment and radar inputs digital-to-analogue conversion
The numerical data of device.When the resolution ratio of digital analog converter is higher, the quantity of its input port is also corresponding more.As digital-to-analogue turns
Parallel operation switching rate more and more higher, its port uses difference port to reduce noise mostly, and this further increases the number of port
Mesh.In multinuclear application, traditional digital analog converter puts corresponding FPDP for each converter caryogamy, makes its port number
Mesh doubles.Excessive port have impact on the application difficulty of digital analog converter, and add the packaging cost of circuit.
In general application, the input port of high-speed A/D converter all uses LVDS signals, its advantage be speed it is high,
Low in energy consumption, noise is small, can low power supply power, sequential accurate positioning, and have the ability of stronger suppression electromagnetic interference.Each pair
LVDS ports include the two paths of signals of difference, and receiver is generally high direct current input impedance, and whole driving currents all flow through 100
Ω terminal coupling resistance, about 350mV (maximum 400mV) voltage is produced in receiver input.
In general, the number of pins drawn is needed when excessive port adds encapsulation, difficulty and envelope that envelope turns is added
The cost of dress, adds the size after circuit package, is unfavorable for the application of circuit.For the angle of user, excessive pipe
Pin adds the difficulty of welding, is also unfavorable for application.
The content of the invention
Present invention solves the technical problem that being：Overcoming the deficiencies in the prior art, there is provided a kind of time division duplexed high-rate LVDS ends
How mouth circuit, The present invention reduces multinuclear high-speed, high precision D/A converter input port number, solve by numeral control
System realizes the problem of multiple signals are sent, and substantially increases the utilization ratio of logarithmic mode ADC data input port.By when
Divide multiplexing LVDS ports, port number is reduced to original a quarter, substantially reduces the number of output port.
The present invention technical solution be：A kind of time division duplexed high-rate LVDS port circuits, including：Primary Receive electricity
Road, the first Secondary Receive circuit, the second Secondary Receive circuit, the 3rd Secondary Receive circuit, the 4th Secondary Receive circuit and control
Circuit；
The input of Primary Receive circuit is connected with external signal, and the input of control circuit is electrically connected with external timing signal
Connect, the first Secondary Receive circuit, the second Secondary Receive circuit, the data of the 3rd Secondary Receive circuit and the 4th Secondary Receive circuit
Output end of the input with Primary Receive circuit is electrically connected, and output end of the control signal input with control circuit is electrically connected
Connect；
When first 1/4 cycle of the Primary Receive circuit within one clock cycle of the first clock signal is to the 4th 1/4
The clock cycle receives four groups of standard LVDS signals successively, and carries out signal acquisition and level translation to the signal received, by outside
LVDS signal levels are converted to after standard CMOS level, and the signal of a cycle length is exported simultaneously and gives the first Secondary Receive electricity
The Secondary Receive circuit of road~the 4th；Control circuit to receive the first clock signal and generate the control signal of the first control signal~the 4th,
The Secondary Receive circuit of the first Secondary Receive circuit~the 4th is controlled respectively using the control signal of the first control signal~the 4th；
The Secondary Receive circuit of first Secondary Receive circuit~the 4th receives the control signal of the first control signal~the 4th respectively,
Worked successively within the same clock cycle, receive output signal and the output of Primary Receive circuit.
The Primary Receive circuit includes：Prime amplifier, source follower, comparator, the first pseudo-differential amplifier and second
Pseudo-differential amplifier；
Prime amplifier receives external perimysium reference LVDS signals, and the two paths of differential signals in external perimysium reference LVDS signals is adopted respectively
Sample and amplifying is exported after N1 times to source follower, and source follower carries out level translation to the two paths of differential signals received, by two
In the level translation of road differential signal to the accessible level range of comparator, comparator receives the two-pass DINSAR after level translation
Signal, two paths of differential signals is amplified after N2 times, the correction data in two paths of differential signals is exported to the first pseudo-differential amplifier,
Negative data is exported to the second pseudo-differential amplifier, and the first pseudo-differential amplifier and the second pseudo-differential amplifier are by the data received
Level conversion is exported into after CMOS level, and described 1.7>N1>1.2, N2>20；
The control circuit includes frequency multiplier and decoding circuit；
The input of frequency multiplier is connected with external timing signal, input and external timing signal and the frequency multiplier of decoder
Output end is connected, and the control end of four output ends of decoding circuit respectively with four second level receiving circuits is connected；
Frequency multiplier receives the first clock signal and to the signal frequency multiplication, generates second clock signal, and decoding circuit receives the
One clock signal and second clock signal, and the first clock signal and second clock signal are carried out as a binary code word
2-4 is decoded, and exports four tunnel control signals, and the control signal of respectively the first control signal~the 4th is used as the first Secondary Receive electricity
The control signal of the Secondary Receive circuit of road~the 4th, the control signal time span of first control signal~the 4th is one
Clock cycle, wherein the first control signal is effective in first 1/4 cycle of the clock cycle, the second control signal is in the clock
Second 1/4 cycle in cycle, effectively the 3rd control signal was effective in the 3rd 1/4 cycle of the clock cycle, the 4th control
Signal is effective in the 4th 1/4 cycle of the clock cycle.
The Secondary Receive circuit of the first Secondary Receive circuit~the 4th is identical band reset comparator.
The Secondary Receive circuit of the first Secondary Receive circuit~the 4th receives the control signal of the first control signal~the 4th,
Worked successively within the same clock cycle, receive output signal and the output of Primary Receive circuit, be specially：
First Secondary Receive circuit receives the first control signal, and is worked within first 1/4 cycle of the first clock signal,
Receive after the data in Primary Receive circuit output signal in first 1/4 clock cycle are handled and export, the two or two grade connects
Receive circuit and receive the second control signal, and worked within first 1/4 cycle of the first clock signal, receive Primary Receive circuit defeated
Go out after the data in signal in second 1/4 clock cycle are handled and export, the 3rd Secondary Receive circuit receives the 3rd and controlled
Signal, and worked within first 1/4 cycle of the first clock signal, the 3rd 1/4 is received in Primary Receive circuit output signal
Data in clock cycle are exported after being handled, and the 4th Secondary Receive circuit receives the 4th control signal, and in the first clock
Signal works in first 1/4 cycle, receives the data in Primary Receive circuit output signal in the 4th 1/4 clock cycle and enters
Exported after row processing, the processing includes：Waveform shaping and increase power output.
Compared with the prior art, the invention has the advantages that：
(1) present invention innovative design has been carried out to the input port in the check figure weighted-voltage D/A converter of high-speed, high precision four, using by
Realize four check figure weighted-voltage D/A converters in the time division multiplexing LVDS ports that Primary Receive circuit, control circuit and second level receiving circuit are constituted
Data acquisition, solve the problem of check figure weighted-voltage D/A converter port of high-speed, high precision four is excessive, port number is reduced to originally
A quarter, substantially reduce the port number of circuit, improve the utilization rate of port, while greatly reducing port section
The power consumption of circuit, while reducing the area of encapsulation；
(2) present invention constitutes Primary Receive circuit by the way of casacade multi-amplifier cascade, substantially increases Primary Receive
The bandwidth of circuit, improves the operating rate of port；
(3) present invention realizes second level receiving circuit using with the comparator resetted, makes the working method of second level circuit
It is easy to be controlled with data signal, improves the control flexibility of circuit, while is easy to the generation of control signal.
Brief description of the drawings
Fig. 1 is the fundamental diagram of time division duplexed high-rate LVDS ports of the present invention；
Fig. 2 is Primary Receive electrical block diagram of the present invention；
Fig. 3 is control circuit structural representation of the present invention；
Fig. 4 is control signal time diagram of the present invention.
Embodiment
The present invention is described in further detail with specific embodiment below in conjunction with the accompanying drawings：
A kind of implementation method of time division duplexed high-rate LVDS ports of the present invention passes through the data reception in digital analog converter
Block is realized, is data reception module fundamental diagram of the present invention as shown in Figure 1, and data reception module connects including one-level as seen from the figure
Receive circuit, the first Secondary Receive circuit, the second Secondary Receive circuit, the 3rd Secondary Receive circuit, the 4th Secondary Receive circuit and
Control circuit.The input of Primary Receive circuit is connected with external signal, controls the input and external timing signal electricity of circuit
Connection, the first Secondary Receive circuit, the second Secondary Receive circuit, the number of the 3rd Secondary Receive circuit and the 4th Secondary Receive circuit
Output end according to input with Primary Receive circuit is electrically connected, and output end of the control signal input with control circuit is electrically connected
Connect.
When first 1/4 cycle of the Primary Receive circuit within one clock cycle of the first clock signal is to the 4th 1/4
The clock cycle receives four groups of standard LVDS signals successively, and carries out signal acquisition and level translation to the signal received, by outside
LVDS signal levels are converted to after standard CMOS level, and the signal of a cycle length is exported simultaneously and gives the first Secondary Receive electricity
The Secondary Receive circuit of road~the 4th；Control circuit to receive the first clock signal and generate the control signal of the first control signal~the 4th,
The Secondary Receive circuit of the first Secondary Receive circuit~the 4th is controlled respectively using the control signal of the first control signal~the 4th；
The Secondary Receive circuit of first Secondary Receive circuit~the 4th receives the control signal of the first control signal~the 4th respectively,
Worked successively within the same clock cycle, receive output signal and the output of Primary Receive circuit.
Primary Receive electrical block diagram in data reception module of the present invention is illustrated in figure 2, one-level connects as seen from the figure
Receiving circuit includes prime amplifier, source follower, comparator, the first pseudo-differential amplifier and the second pseudo-differential amplifier；Pre-amplification
The input of device is connected with external data, and the input of source follower and the output end of prime amplifier are connected, the input of comparator
End is connected with the output end of prime amplifier, and the input of pseudo-differential amplifier and the output end of comparator are connected.
Prime amplifier receives external perimysium reference LVDS signals, and the two paths of differential signals in external perimysium reference LVDS signals is adopted respectively
Sample and amplifying is exported after N1 times to source follower, and source follower carries out level translation to the two paths of differential signals received, by two
In the level translation of road differential signal to the accessible level range of comparator, comparator receives the two-pass DINSAR after level translation
Signal, two paths of differential signals is amplified after N2 times, the correction data in two paths of differential signals is exported to the first pseudo-differential amplifier,
Negative data is exported to the second pseudo-differential amplifier, and the first pseudo-differential amplifier and the second pseudo-differential amplifier are by the data received
Level conversion is exported into after CMOS level, and described 1.7>N1>1.2, N2>20；
The structural representation that circuit is controlled in data reception module of the present invention is illustrated in figure 3, circuit is controlled as seen from the figure
Including frequency multiplier and decoding circuit, the input of frequency multiplier is connected with external timing signal, when the input of decoder is with outside
Clock signal and the connection of frequency multiplier output end, the control end of four output ends of decoding circuit respectively with four second level receiving circuits
Connection.
Frequency multiplier receives the first clock signal and to the signal frequency multiplication, generates second clock signal, and decoding circuit receives the
One clock signal and second clock signal, and the first clock signal and second clock signal are carried out as a binary code word
2-4 is decoded, and exports four tunnel control signals, and the control signal of respectively the first control signal~the 4th is used as the first Secondary Receive electricity
The control signal of the Secondary Receive circuit of road~the 4th, the control signal time span of first control signal~the 4th is one
Clock cycle, wherein the first control signal is effective in first 1/4 cycle of the clock cycle, the second control signal is in the clock
Second 1/4 cycle in cycle, effectively the 3rd control signal was effective in the 3rd 1/4 cycle of the clock cycle, the 4th control
Signal is effective in the 4th 1/4 cycle of the clock cycle.
The input and output sequential chart that circuit is controlled in data reception module of the present invention is illustrated in figure 4, input signal is the
One clock signal and second clock signal, wherein the first clock signal is external timing signal, second clock signal is frequency multiplier
Output signal, the first clock signal frequency is twice of second clock signal frequency, and output signal is the first control signal-the
Four control signals, first the-the four control signal of control signal is first the-the four Secondary Receive circuit of Secondary Receive circuit respectively
Control signal.When the first clock signal and second clock signal change, first the-the four control signal of control signal is successively
For low level, first the-the four Secondary Receive circuit of Secondary Receive circuit of control works successively, receives the signal of Primary Receive circuit
And exported.
Embodiment
Under 0.18um dimension process, if digital data rates are 625M, each port number data rate is 625M,
And under 0.18um dimension process, receiving circuit bandwidth, which can be relatively easy to, reaches 3GHz, the waste of bandwidth is caused；Using
This circuit structure, the bandwidth Design of Primary Receive circuit is 2.5GHz, and a width of 625MHz of band of each second level receiving circuit,
Agreement sends data using time-multiplexed mode in data transmission procedure, i.e. each cycle is 1600ps, 0~
The first data are sent during 400ps, the second data are sent in 400ps~800ps, the 3rd is sent in 800ps~1200ps and is counted
According to the 4th data of transmission in 1200ps~1600ps within each clock cycle, send four data successively.
Using conventional method input digital data, the port related to numerical data input is 16 × 4 × 2=128 end
Mouthful, if packing forms are encapsulated using QFP, lead pin pitch 0.5mm, then the Zhou Changwei 64mm that digital input data pin takes.If
Realized using this method, the pin related to numerical data input is 32 ports, is encapsulated according to identical, then numeral input
The Zhou Changwei 16mm that data pins take.
Table 1 is traditional port circuit and this comparison using this circuit realiration under the conditions of several conventional packaging technologies, from table 1
In contrast understand, 16bit four-way high-speed A/D converter chips numerical data input implementation process in, using this electricity
Road, which is realized, can greatly reduce outside port quantity, reduce package dimension.Table 1
Claims (5)
1. a kind of time division duplexed high-rate LVDS port circuits, it is characterised in that including：Primary Receive circuit, the first Secondary Receive
Circuit, the second Secondary Receive circuit, the 3rd Secondary Receive circuit, the 4th Secondary Receive circuit and control circuit；
The input of Primary Receive circuit is connected with external perimysium reference LVDS signals, controls the input and the first clock signal of circuit
Electrical connection, the first Secondary Receive circuit, the second Secondary Receive circuit, the 3rd Secondary Receive circuit and the 4th Secondary Receive circuit
Output end of the data input pin with Primary Receive circuit is electrically connected, output end electricity of the control signal input with controlling circuit
Connection；
First 1/4 cycle of the Primary Receive circuit within one clock cycle of the first clock signal to the 4th 1/4 clock week
Phase receives four groups of external perimysium reference LVDS signals successively, and carries out signal acquisition and level translation to the signal received, by outside
Standard LVDS signal levels are converted to after standard CMOS level, and the signal of a cycle length is exported simultaneously and connect to the one or two grade
Receive the Secondary Receive circuit of circuit~the 4th；Control circuit to receive the first clock signal generation the first control signal~4th and control letter
Number, the Secondary Receive circuit of the first Secondary Receive circuit~the 4th is controlled respectively using the control signal of the first control signal~the 4th；
The Secondary Receive circuit of first Secondary Receive circuit~the 4th receives the control signal of the first control signal~the 4th respectively, same
Worked successively in one clock cycle, receive output signal and the output of Primary Receive circuit.
2. a kind of time division duplexed high-rate LVDS port circuits according to claim 1, it is characterised in that：The Primary Receive
Circuit includes：Prime amplifier, source follower, comparator, the first pseudo-differential amplifier and the second pseudo-differential amplifier；
Prime amplifier receives external perimysium reference LVDS signals, and the two paths of differential signals in external perimysium reference LVDS signals is sampled simultaneously respectively
Exported after N1 times of amplification to source follower, source follower carries out level translation to the two paths of differential signals received, and two-way is poor
In the level translation of sub-signal to the accessible level range of comparator, comparator receives the two-pass DINSAR letter after level translation
Number, two paths of differential signals is amplified after N2 times, the correction data in two paths of differential signals is exported to the first pseudo-differential amplifier, is born
Data output gives the second pseudo-differential amplifier, and the first pseudo-differential amplifier and the second pseudo-differential amplifier are electric by the data received
Flat turn is changed into and exported after CMOS level, and described 1.7>N1>1.2, N2>20.
3. a kind of time division duplexed high-rate LVDS port circuits according to claim 1, it is characterised in that：The control circuit
Including frequency multiplier and decoding circuit；
The input of frequency multiplier is connected with the first clock signal, and the input of decoder and the first clock signal and frequency multiplier are exported
End connection, the control end of four output ends of decoding circuit respectively with four second level receiving circuits is connected；
Frequency multiplier receives the first clock signal and to the first clock signal frequency multiplication, generates second clock signal, decoding circuit
The first clock signal and second clock signal are received, and regard the first clock signal and second clock signal as a binary code
Word carries out 2-4 decodings, exports four tunnel control signals, and the control signal of respectively the first control signal~the 4th is used as the one or two grade
The control signal of the Secondary Receive circuit of receiving circuit~the 4th, first control signal~the 4th control signal time span is equal
For a clock cycle, wherein the first control signal the clock cycle first 1/4 cycle effectively, the second control signal exists
Second 1/4 cycle of the clock cycle, effectively the 3rd control signal was effective in the 3rd 1/4 cycle of the clock cycle, the
Four control signals are effective in the 4th 1/4 cycle of the clock cycle.
4. a kind of time division duplexed high-rate LVDS port circuits according to claim 1, it is characterised in that：Described one or two grade
The Secondary Receive circuit of receiving circuit~the 4th is identical band reset comparator.
5. a kind of time division duplexed high-rate LVDS port circuits according to claim 1, it is characterised in that：Described one or two grade
The Secondary Receive circuit of receiving circuit~the 4th receives the control signal of the first control signal~the 4th, within the same clock cycle according to
Task, receives output signal and the output of Primary Receive circuit, is specially：
First Secondary Receive circuit receives the first control signal, and is worked within first 1/4 cycle of the first clock signal, receives
Data in Primary Receive circuit output signal in first 1/4 clock cycle are exported after being handled, the second Secondary Receive electricity
Road receives the second control signal, and is worked within first 1/4 cycle of the first clock signal, receives Primary Receive circuit output letter
Data in number in second 1/4 clock cycle are exported after being handled, and the 3rd Secondary Receive circuit receives the 3rd control signal,
And worked within first 1/4 cycle of the first clock signal, receive the 3rd 1/4 clock week in Primary Receive circuit output signal
Data in phase are exported after being handled, and the 4th Secondary Receive circuit receives the 4th control signal, and in the first clock signal the
Worked in one 1/4 cycle, receive the data in Primary Receive circuit output signal in the 4th 1/4 clock cycle and handled
After export, the processing includes：Waveform shaping and increase power output.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410681914.9A CN104467803B (en) | 2014-11-24 | 2014-11-24 | A kind of time division duplexed high-rate LVDS port circuits |
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| CN201410681914.9A CN104467803B (en) | 2014-11-24 | 2014-11-24 | A kind of time division duplexed high-rate LVDS port circuits |
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| CN104467803A CN104467803A (en) | 2015-03-25 |
| CN104467803B true CN104467803B (en) | 2017-09-05 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109656735A (en) * | 2018-12-03 | 2019-04-19 | 晶晨半导体(上海)股份有限公司 | Function port, electronic equipment and the method for promoting electronic equipment ESD performance |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07202940A (en) * | 1993-12-28 | 1995-08-04 | Toshiba Corp | Packet exchange |
| CN1156365A (en) * | 1995-12-28 | 1997-08-06 | 美国电报电话公司 | Multiple layer star form passive optical network based on terminal unit remote interrogation |
| CN101632229A (en) * | 2007-02-28 | 2010-01-20 | 松下电器产业株式会社 | A/D converter and A/D converting method |
| CN102468852A (en) * | 2010-11-09 | 2012-05-23 | 中国电子科技集团公司第五十四研究所 | High-speed analog/digital converter (AD) parallel sampling device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3889613B2 (en) * | 2001-12-10 | 2007-03-07 | 富士通株式会社 | Interface device |
-
2014
- 2014-11-24 CN CN201410681914.9A patent/CN104467803B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07202940A (en) * | 1993-12-28 | 1995-08-04 | Toshiba Corp | Packet exchange |
| CN1156365A (en) * | 1995-12-28 | 1997-08-06 | 美国电报电话公司 | Multiple layer star form passive optical network based on terminal unit remote interrogation |
| CN101632229A (en) * | 2007-02-28 | 2010-01-20 | 松下电器产业株式会社 | A/D converter and A/D converting method |
| CN102468852A (en) * | 2010-11-09 | 2012-05-23 | 中国电子科技集团公司第五十四研究所 | High-speed analog/digital converter (AD) parallel sampling device |
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