CN104467755B - Method for calibrating integrated adjustable clock through radio frequency reception path - Google Patents
Method for calibrating integrated adjustable clock through radio frequency reception path Download PDFInfo
- Publication number
- CN104467755B CN104467755B CN201410612264.2A CN201410612264A CN104467755B CN 104467755 B CN104467755 B CN 104467755B CN 201410612264 A CN201410612264 A CN 201410612264A CN 104467755 B CN104467755 B CN 104467755B
- Authority
- CN
- China
- Prior art keywords
- frequency
- signal
- clock
- error
- integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses a method for calibrating an integrated adjustable clock through a radio frequency reception path. The method includes the steps that low-noise amplification is performed on a received single-frequency signal; a signal generated by the integrated clock passes a frequency synthesizer, so that a new signal is obtained, and then frequency mixing is performed on the new signal and the single-frequency signal obtained after low-noise amplification, so that an intermediate and low frequency error signal is obtained; low-pass filtering is performed on the error signal generated through frequency mixing; an intermediate and low frequency signal generated through low-pass filtering is converted into a digital signal, frequency division is performed on the digital signal, and frequency error estimation is performed; the frequency of the integrated adjustable clock is adjusted through the frequency error estimation result till the frequency error is within a specified range. By the utilization of the method, the clock frequency precision of a system can be improved, and the defect that an integrated clock signal generator is large in frequency error can be overcome.
Description
Technical field
The present invention relates to clock signal generation technique field, it is specifically a kind of using radio frequency reception path to it is integrated can timing
The method that clock is calibrated.
Background technology
Due to powerful data processing and logic control ability, very strong antijamming capability, and can be in different works
Convenient between skill reliably to transplant, digital circuit has become essential part in any a SoC.And clock signal is to appoint
The precondition that what one digital Synchronous sequential logic circuit can work.Exactly under the beat that clock signal gives, numeral
Circuit completes the function of predetermined data processing and logic control without any confusion.
Oscillator based on quartz crystal is acknowledged as optimal clock signal generation always due to its remarkable performance
Device.However, with the continuous progress of semiconductor process technique, single chip integrated function is stronger and stronger, the power consumption and body of system
Product is also increasingly subject to the attention of designer.The characteristics of due to its working mechanism, the volume and work(of the oscillator based on quartz crystal
Consumption is difficult further to reduce, the continuous reduction of this power consumption that certainly will limit system and volume.In the requirement to volume and power consumption
In very strict system, using can be integrated clock signal generators come instead of quartz oscillator would is that one it is important
Solution.
At present, using analogy method or digital method design can be integrated clock signal generators frequency error compared with
Greatly, very big clock jitter can be produced in transmitting-receiving both sides, it is impossible to for carrying out the communication of high speed.The method that the present invention is provided exists
In transceiver on existing radio frequency reception path, little analog circuit and digital control logic is increased, by frequency
Rate error is estimated and is adjusted the clock frequency of receiving side, so as to reduce the clock jitter of transmitting-receiving both sides, in being allowed to meet
The requirement of high-speed communication.
The content of the invention
(1) technical problem to be solved
In consideration of it, being carried out to integrated adjustable clock using radio frequency reception path it is a primary object of the present invention to provide one kind
The method of calibration, to reduce its frequency departure, makes it possible to carry out the communication of high speed.
(2) technical scheme
To reach above-mentioned purpose, integrated adjustable clock is calibrated using radio frequency reception path the invention provides one kind
Method, the method includes：
Step 1：Simple signal to receiving carries out low noise amplification；
Step 2：The signal that integrated clock is produced by frequency synthesizer, the signal for obtaining with carry out low noise amplification after
Simple signal be mixed, obtain the error signal of middle low frequency；
Step 3：LPF is carried out to the error signal that mixing is produced；
Step 4：The middle low frequency signal that LPF is produced is converted into data signal, carrying out frequency dividing to data signal goes forward side by side
Line frequency estimation error；
Step 5：The frequency of integrated adjustable clock is adjusted the result estimated using frequency error until frequency error
Reach in the scope specified.
In such scheme, before carrying out low noise amplification to the simple signal for receiving described in step 1, also include：Hair
Sending end first sends out the simple signal of a period of time before transmitting data, and receiving terminal enters row clock using the simple signal for receiving
The calibration of frequency.
In such scheme, the integrated clock described in step 2 is the clock of frequency-adjustable, you can its frequency is adjusted
It is whole.
In such scheme, LPF is carried out to the error signal that mixing is produced described in step 3, the low pass filtered for being used
The bandwidth of ripple device is not less than the absolute value of frequency error, to ensure simple signal by being not filtered out after LPF.
Carry out to data signal frequency dividing in such scheme, described in step 4 to go forward side by side line frequency estimation error, wherein entering line frequency
The method of rate estimation error is to be counted the frequency error signal that LPF is produced within a certain period of time as clock, and
And comparing the size of count value, count value is smaller to show that frequency error is smaller.
In such scheme, the frequency described in step 5 to integrated adjustable clock is adjusted, and the method for using is a kind of base
In the two-value search method for comparing.
It is described based on the two-value search method for comparing in such scheme, it is to be compared to by the result to counting twice
Determine the direction of frequency adjustment.
(3) beneficial effect
The method calibrated to integrated adjustable clock using radio frequency reception path that the present invention is provided, using what is received
Simple signal can be calibrated, with advantages below：
(1) due to the method using search iteration, the direction that frequency is adjusted is determined by the result of comparison search window, because
This present invention is to insensitive for noise；
(2) method due to gradually being halved using search window, therefore characteristic of the present invention with Fast Convergent；
(3) present invention can make full use of existing receiving path in receiver, it is only necessary to increase a small amount of control logic, because
The characteristics of this has expense low.
(4) using the present invention, the precision of integrated adjustable clock can be improved, reduces the clock jitter of transmitting-receiving side, overcome collection
Into the shortcoming that clock signal generators frequency error is larger, it is allowed to meet the demand of high speed communication.
Brief description of the drawings
Fig. 1 is the method flow diagram calibrated to integrated adjustable clock using radio frequency reception path that the present invention is provided；
Fig. 2 is the structural representation of the system for realizing method shown in Fig. 1；
Fig. 3 is a kind of schematic diagram of frequency error method of estimation；
Fig. 4 is the schematic diagram based on the two-value searching method for comparing.
Specific embodiment
To make the object, technical solutions and advantages of the present invention become more apparent, below in conjunction with specific embodiment, and reference
Accompanying drawing, the present invention is described in more detail.
As shown in figure 1, Fig. 1 is the side calibrated to integrated adjustable clock using radio frequency reception path that the present invention is provided
Method flow chart, the method includes the steps of：
Step 1：Simple signal to receiving carries out low noise amplification；
Step 2：The signal that integrated clock is produced by frequency synthesizer, the signal for obtaining with carry out low noise amplification after
Simple signal be mixed, obtain the error signal of middle low frequency；
Step 3：LPF is carried out to the error signal that mixing is produced；
Step 4：The middle low frequency signal that LPF is produced is converted into data signal, carrying out frequency dividing to data signal goes forward side by side
Line frequency estimation error；
Step 5：The frequency of integrated adjustable clock is adjusted the result estimated using frequency error until frequency error
Reach in the scope specified.
Wherein, before carrying out low noise amplification to the simple signal for receiving described in step 1, also include：Transmitting terminal exists
The simple signal of a period of time is first sent out before sending data, receiving terminal carries out clock frequency using the simple signal for receiving
Calibration.In addition, the simple signal to receiving carries out low noise amplification, make when the low-noise amplifier for being used is with normal work
Low-noise amplifier is identical, without any particular/special requirement.
Integrated clock described in step 2 is the clock of frequency-adjustable, you can its frequency is adjusted.The clock passes through
The signal produced after frequency synthesizer is used for being mixed with the simple signal for receiving, and the result of mixing is error signal, should
Error signal is the signal of middle low frequency.
LPF is carried out to the error signal that mixing is produced described in step 3, the bandwidth of the low pass filter for being used
Not less than the absolute value of frequency error, to ensure simple signal by being not filtered out after LPF.
The middle low frequency signal that LPF is produced is converted into data signal described in step 4, it is possible to use Schmitt is touched
Signal after LPF is converted to data signal by hair device, and the method for carrying out frequency error estimation is to produce LPF
Frequency error signal is counted within a certain period of time as clock, and compares the size of count value, final count value it is big
The small size for indicating frequency departure, count value is smaller to show that frequency error is smaller.
Frequency described in step 5 to integrated adjustable clock is adjusted, and the method for using is for a kind of based on compare two
Value search method.The method does not rely on the absolute size of step 4 count value, but compares by the result for counting twice
Relatively come determine frequency adjustment direction, which reduce the influence that noise is estimated frequency error, it is ensured that searching algorithm it is steady
It is qualitative.Additionally, described, based on the two-value search method for comparing, the search window of initial frequency error is possible maximum, it
The search window of each frequency error all halves afterwards, so both ensure that the scope of frequency search, causes that searching algorithm can be with again
Fast Convergent.
Integrated adjustable clock is calibrated using radio frequency reception path to what the present invention was provided below in conjunction with Fig. 2 to Fig. 4
Method be described in detail.In order to describe conveniently, the frequency of the simple signal received in note Fig. 2 is fREF, the signal be by
Frequency is f0Clock signal obtain by frequency synthesis, and meet：
fREF=f0·NSYN (1)
Wherein, NSYNIt is the multiplier parameter of frequency synthesizer.
The frequency of the clock signal that note receiving terminal is produced by integrated adjustable clock is fDCO, and meet：
fDCO=f0·(1+ε) (2)
Wherein, ε is fDCORelative to f0Deviation factor.
The frequency of the signal that note receiving terminal frequency mixer is produced is fSYN, and meet：
fSYN=fDCO·NSYN (3)
Overall work process can be expressed as follows：
After the signal for receiving is by low-noise amplifier (101), frequency mixer (201) and low pass filter (301), institute
The frequency of the middle low frequency signal for producing is fIF', and meet：
fI'F=f0·NSYN·ε (4)
The bandwidth BW of low pass filter (301)LPFF should be not less thanIF'.The signal is carried out by Schmidt trigger (401)
Digitlization, and carry out NSYNAfter frequency dividing (402) again, frequency is changed into fIF, and meet：
fIF=f0·ε (5)
From formula (4), fIFSize characterize the size of frequency departure ε.
Method of estimation to frequency departure ε is as shown in Figure 3：Counted using two counters, its Counter A
(404) clock is integrated adjustable clock, and frequency is fDCO, the clock of counter B (403) is LPF, digitlization and frequency dividing
Signal afterwards, frequency is fIF.The N in terms of counter ACNTThe time T of numberACCTo count total time, compare the count value of counter B
Size NIFJust can determine whether the trend of frequency departure ε changes.Although fDCOAdjustment of the size with control logic (501) to it exist
Real-time change, but as long as meeting ε<<1, the conclusion is still set up.This be due to：
Enter the line frequency strategy that uses of adjustment to integrated adjustable clock (601) for based on the two-value searching algorithm for comparing, such as
Shown in Fig. 4, each search window is respectively f comprising 3 frequency valuesL,n, fM,nAnd fH,n, the result of frequency offset estimation is respectively
NL,n, NM,nAnd NH,n.Specifically search procedure is：
(1) with the original frequency f of systemDCOAs fM,1, the result of the frequency offset estimation for obtaining is NM,1；
(2) respectively with fDCO(1-εmax) and fDCO(1+εmax) as fL,1With fH,1, fL,1With fH,1Constitute the 1st search
Window S1, and the count results for obtaining are NL,1And NH,1；
(3) N is comparedL,1And NH,1, select the corresponding frequency of less count value and fM,1Constitute the 2nd search window S2, S2
The frequency range of covering is S11/2.If than NL,1<NH,1, then f is selectedL,1, and make fL,2=fL,1, fH,2=fM,1。
(4) f is madeM,2=(fL,2+fH,2)/2, and the Frequency Estimation result for obtaining is NM,2。
(5) N is comparedL,2And NH,2, select the corresponding frequency of less count value and fM,2Constitute the 3rd search window S3, S3
The frequency range of covering is S21/2.
(6) it is iterated in this way, until NL,2And NH,2Difference be less than a certain threshold value.Now, the mistake of system frequency
Difference converges to desired value f0(1+ε0)。
Due to entering not having to rely on absolute count value when line frequency is adjusted, come just with relative counting size
Direction and the scope of search are adjusted, therefore the method has preferable resistivity to noise and interference.Additionally, being searched by two-value
The method of rope accelerates the convergence rate of frequency adjustment.
Particular embodiments described above, has been carried out further in detail to the purpose of the present invention, technical scheme and beneficial effect
Describe in detail bright, should be understood that and the foregoing is only specific embodiment of the invention, be not intended to limit the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvements done etc., should be included in guarantor of the invention
Within the scope of shield.
Claims (7)
1. a kind of method calibrated to integrated adjustable clock using radio frequency reception path, it is characterised in that the method is included：
Step 1：Simple signal to receiving carries out low noise amplification；
Step 2：The signal that integrated clock is produced by frequency synthesizer, the signal for obtaining with carry out the list after low noise amplification
Frequency signal is mixed, and obtains the error signal of middle low frequency；
Step 3：LPF is carried out to the error signal that mixing is produced；
Step 4：The middle low frequency signal that LPF is produced is converted into data signal, frequency dividing is carried out to data signal and is gone forward side by side line frequency
Rate estimation error；
Step 5：The result estimated using frequency error is adjusted to the frequency of integrated adjustable clock until frequency error reaches
In the scope specified.
2. the method calibrated to integrated adjustable clock using radio frequency reception path according to claim 1, its feature
It is before carrying out low noise amplification to the simple signal for receiving described in step 1, also to include：
Transmitting terminal first sends out the simple signal of a period of time before transmitting data, and receiving terminal is entered using the simple signal for receiving
The calibration of row clock frequency.
3. the method calibrated to integrated adjustable clock using radio frequency reception path according to claim 1, its feature
It is that the integrated clock described in step 2 is the clock of frequency-adjustable, you can its frequency is adjusted.
4. the method calibrated to integrated adjustable clock using radio frequency reception path according to claim 1, its feature
It is that LPF is carried out to the error signal that mixing is produced described in step 3, the bandwidth of the low pass filter for being used is not small
In the absolute value of frequency error, to ensure simple signal by being not filtered out after LPF.
5. the method calibrated to integrated adjustable clock using radio frequency reception path according to claim 1, its feature
It is to carry out to data signal frequency dividing described in step 4 to go forward side by side line frequency estimation error, wherein carrying out the side of frequency error estimation
Method is to be counted the frequency error signal that LPF is produced within a certain period of time as clock, and compares count value
Size, count value is smaller to show that frequency error is smaller.
6. the method calibrated to integrated adjustable clock using radio frequency reception path according to claim 1, its feature
It is that the frequency described in step 5 to integrated adjustable clock is adjusted, the method for using is searched for a kind of based on the two-value for comparing
Suo Fa.
7. the method calibrated to integrated adjustable clock using radio frequency reception path according to claim 6, its feature
It is, it is described based on the two-value search method for comparing, it is to be compared to determine what frequency was adjusted by the result to counting twice
Direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410612264.2A CN104467755B (en) | 2014-11-04 | 2014-11-04 | Method for calibrating integrated adjustable clock through radio frequency reception path |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410612264.2A CN104467755B (en) | 2014-11-04 | 2014-11-04 | Method for calibrating integrated adjustable clock through radio frequency reception path |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104467755A CN104467755A (en) | 2015-03-25 |
| CN104467755B true CN104467755B (en) | 2017-05-24 |
Family
ID=52913239
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410612264.2A Active CN104467755B (en) | 2014-11-04 | 2014-11-04 | Method for calibrating integrated adjustable clock through radio frequency reception path |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104467755B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110781557B (en) * | 2019-10-14 | 2023-04-07 | 中国航空工业集团公司沈阳飞机设计研究所 | Aircraft system model simulation test flow optimization method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1866799A (en) * | 2006-06-15 | 2006-11-22 | 北京北方烽火科技有限公司 | TD-SCDMA signal generator and its regulating method |
| CN201285555Y (en) * | 2008-11-03 | 2009-08-05 | 上海复旦微电子股份有限公司 | RFID label for calibrating time clock signal |
| CN101727601A (en) * | 2008-11-03 | 2010-06-09 | 上海复旦微电子股份有限公司 | Radio frequency identification tag and method for calibrating clock signals |
| CN102231636A (en) * | 2011-06-21 | 2011-11-02 | 清华大学 | Radio frequency front end device of receiver and signal receiving method thereof |
| CN102682330A (en) * | 2011-03-17 | 2012-09-19 | 北京同方微电子有限公司 | Clock generating circuit for radio frequency identification (RFID) tag and calibrating method of clock generating circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10029421C2 (en) * | 2000-06-15 | 2002-07-11 | Infineon Technologies Ag | Calibration device and method for clock generation on an integrated circuit |
-
2014
- 2014-11-04 CN CN201410612264.2A patent/CN104467755B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1866799A (en) * | 2006-06-15 | 2006-11-22 | 北京北方烽火科技有限公司 | TD-SCDMA signal generator and its regulating method |
| CN201285555Y (en) * | 2008-11-03 | 2009-08-05 | 上海复旦微电子股份有限公司 | RFID label for calibrating time clock signal |
| CN101727601A (en) * | 2008-11-03 | 2010-06-09 | 上海复旦微电子股份有限公司 | Radio frequency identification tag and method for calibrating clock signals |
| CN102682330A (en) * | 2011-03-17 | 2012-09-19 | 北京同方微电子有限公司 | Clock generating circuit for radio frequency identification (RFID) tag and calibrating method of clock generating circuit |
| CN102231636A (en) * | 2011-06-21 | 2011-11-02 | 清华大学 | Radio frequency front end device of receiver and signal receiving method thereof |
Non-Patent Citations (1)
| Title |
|---|
| 基于FPGA的多模式信号源的研究与实现;汪东雷;《全国优秀硕士学位论文》;20101130;全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104467755A (en) | 2015-03-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2016095679A1 (en) | Digital fractional frequency phase-locked loop control method and phase-locked loop | |
| CN103490777B (en) | low spurious frequency synthesizer | |
| CN104348471B (en) | Clock and data recovery method and circuit | |
| JP3857696B2 (en) | Semiconductor integrated circuit and inspection method thereof | |
| CN104601259B (en) | Wireless communication receiver with i/q imbalance estimation and correction techniques | |
| CN107924158A (en) | Dynamic error in calibrated high-resolution numeral to time converter | |
| CN103152034A (en) | Decimal frequency dividing phase-locked loop circuit and control method for frequency dividing ratio | |
| JPWO2016104464A1 (en) | Phase digital converter, phase difference pulse generator, radio communication apparatus, and radio communication method | |
| US11212017B2 (en) | Phase-locked loop (PLL) calibration | |
| CN104467755B (en) | Method for calibrating integrated adjustable clock through radio frequency reception path | |
| US9503135B2 (en) | Sliding intermediate frequency (IF) receiver with adjustable division ratio and sliding IF reception method | |
| US10879910B1 (en) | Method and apparatus for locking a transmitter oscillator to a reference clock signal in a frequency domain | |
| CN204376873U (en) | For wireless frequency synthesizer | |
| CN103812505B (en) | bit synchronization lock detector | |
| US20090079497A1 (en) | Phase tuning techniques | |
| CN207150565U (en) | A kind of high speed delay phase-locked loop | |
| CN106505997A (en) | clock and data recovery circuit and clock and data recovery method | |
| CN109004931A (en) | The extraction system of phase adjusting apparatus and terahertz signal | |
| Chiueh et al. | A 6-Gb/s adaptive-loop-bandwidth clock and data recovery (CDR) circuit | |
| CN104518786B (en) | A kind of auto frequency control method, automatic frequency control apparatus and user equipment | |
| CN107565958A (en) | To the gain calibration of digital controlled oscillator in fast lock phase-locked loop | |
| CN103647510A (en) | Limited random frequency difference reflection control method of microwave signal | |
| CN104467832A (en) | A wireless communication apparatus frequency synthesizer | |
| Kim et al. | A 1.248 Gb/s-2.918 Gb/s Low-Power Receiver for MIPI-DigRF M-PHY with a Fast Settling Fully Digital Frequency Detection Loop in 0.11㎛ CMOS | |
| CN107565959A (en) | A kind of high speed delay phase-locked loop and its automatic frequency calibration method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20201217 Address after: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee after: AoXin integrated circuit technology (Guangdong) Co.,Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220506 Address after: 510000 room 710, Jianshe building, No. 348, Kaifa Avenue, Huangpu District, Guangzhou, Guangdong Patentee after: Ruili flat core Microelectronics (Guangzhou) Co.,Ltd. Address before: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee before: AoXin integrated circuit technology (Guangdong) Co.,Ltd. |
|
| TR01 | Transfer of patent right |