CN104465621B - Dual graphing electrical testing structure and monitoring method - Google Patents
Dual graphing electrical testing structure and monitoring method Download PDFInfo
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- CN104465621B CN104465621B CN201410686757.0A CN201410686757A CN104465621B CN 104465621 B CN104465621 B CN 104465621B CN 201410686757 A CN201410686757 A CN 201410686757A CN 104465621 B CN104465621 B CN 104465621B
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- dual graphing
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Abstract
The invention provides a kind of Dual graphing electrical testing structure and monitoring method, it includes：Upper metal level, lower metal layer, and it is connected to the through-hole structure of the upper and lower metal level；Through-hole structure is located at the overlapping region of upper metal level and lower metal layer.There is Dual graphing to split graph layer for upper metal level and/or lower metal layer, and Dual graphing, which splits graph layer, has splicing overlay region；Splicing overlay region is located in the overlapping region of upper metal level and lower metal layer, and is connected with the top of through-hole structure and/or bottom.Electrical testing is carried out to this group of electrical testing structure, the resistance value of corresponding through-hole structure can be obtained, it may thereby determine that the zone of reasonableness of splicing lap, the zone of reasonableness of the splicing lap can instruct the fractionation situation in Dual graphing split process, it is set to establish more rational fractionation rule, so as to monitor the splice region formed in metal level Dual graphing split process to the influence for the through hole resistance being attached thereto.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of Dual graphing electrical testing structure and to double picture
The monitoring method of the through hole resistance of shape splicing regions.
Background technology
When the step that Moore's Law continuation extends forward is irreversible, Dual graphing technology undoubtedly becomes industry
The optimal selection on boundary, Dual graphing technology only need the change for carrying out very little to existing photoetching infrastructure can be effectively
Fill up the photoetching technique blank of 32 nanometers of even more minor nodes.The principle of Dual graphing technology is by a set of highdensity circuit
Graphics decomposition into two sets discrete, figure that density is lower, then they are prepared on wafer.
In 32 nanometers even more lithography process of fine pith, due to the presence of optical approach effect, there is line
End is rounded (line end rounding), and line end shortens (line end shorting), and corner is rounded (corner
Rounding), key size deviation (critical dimension offset), patterns such as (line bridge) is bridged between line
Distortion phenomenon.
When Dual graphing is split, some splicing regions can be produced.Because the presence of these above-mentioned distortion phenomenons, double
There is some difference for the pattern of pattern and design of the graphical splicing regions of weight on actual silicon chip.These splicing regions warp simultaneously
Go through Twi-lithography (photoetching-photo etching process：LLE) or even twice hard mask layer etches (photoetching-etching-photoetching-etching：
LELE), electrical testing result is influenceed there is also certain.
Refer to Fig. 1 a and 1b, Fig. 1 a and Fig. 1 b show Dual graphing split after splice region by optical approach effect shadow
Loud and caused aliasing phenomenon；Fig. 1 a show Dual graphing split after splice region lap be zero schematic diagram,
The line end caused by optical proximity effect is rounded the distortion phenomenon to be shortened with line end, is when design configuration 101 splices lap
When zero, then after double-pattern technique, the figure 102 of the formation on silicon chip is rendered as open circuit；Fig. 1 b show dual
The lap of splice region is more than zero schematic diagram after graphical fractionation, also due to distortion phenomenon, this design configuration 201 finally exists
The area of the actual splicing overlay region of the figure 202 of formation on silicon chip is less than design configuration.Therefore, how to avoid double
The influence of the through hole resistance connected after the graphical fractionation of weight to splice region can not be ignored.
The content of the invention
In order to overcome problem above, the present invention proposes a kind of Dual graphing electrical testing structure and to Dual graphing
The monitoring method of the through hole resistance of splicing regions, so as to determine to splice the zone of reasonableness of lap.
In order to achieve the above object, the invention provides a kind of Dual graphing electrical testing structure, it includes：Upper metal
Layer, lower metal layer, and it is connected to the through-hole structure of the upper and lower metal level；The through-hole structure is located at the upper metal level
With the overlapping region of the lower metal layer；Wherein,
There is Dual graphing to split graph layer for the upper metal level and/or lower metal layer, and the Dual graphing is split
Graph layer has splicing overlay region；The splicing overlay region is located at the overlay region of the upper metal level and the lower metal layer
In domain, and it is connected with the top of the through-hole structure and/or bottom.
Preferably, the Dual graphing splits the lap of the splicing overlay region of graph layer more than or equal to zero.
Preferably, the splicing overlay region covers the top/of the through-hole structure or bottom.
Preferably, the splicing overlay region is identical with the top of the through-hole structure and/or the figure of bottom.
Preferably, the upper metal level and/or the lower metal layer are strip.
Present invention also offers a kind of monitoring method of the through hole resistance of Dual graphing splice region, it is characterised in that adopts
With above-mentioned electrical testing structure；The monitoring method comprises the following steps：
Step 01：One group of difference lap is set, and accordingly to the upper metal level and/or the figure of the lower metal layer
Dual graphing fractionation is carried out, obtains one group of electrical testing structure that there is Dual graphing to split graph layer；Wherein, group electricity
Learn the Dual graphing in test structure and split the splicing overlay region that graph layer contains different laps；It is described to splice overlapping position
In the overlapping region of the upper metal level and the lower metal layer, and with the top and/or bottom of the through-hole structure
Portion is connected；
Step 02：Electrical testing is carried out to this group of electrical testing structure, obtained in the corresponding electrical testing structure
The resistance value of through-hole structure；
Step 03：Electrical testing is carried out to the electrical testing structure split without Dual graphing, obtained corresponding
Through-hole structure resistance value；
Step 04：The resistance value in resistance value and the step 03 in the step 02, determine the splicing weight
The target zone of the lap in folded area.
Preferably, the lap of the splicing overlay region in the step 01 is more than or equal to zero.
Preferably, the splicing overlay region covers the top/of the through-hole structure or bottom.
Preferably, the splicing overlay region is identical with the top of the through-hole structure and/or the shape of bottom.
Preferably, the electrical testing is carried out in the step 02 or using four end methods of testing in the step 03.
Dual graphing electrical testing structure of the invention and the prison for the through hole resistance for splicing overlay region to Dual graphing
Prosecutor method, by setting the through-hole structure of upper and lower metal level and the upper lower metal layer of connection, by upper metal level and/or lower metal
Layer carries out Dual graphing fractionation, obtains the electricity that one group of Dual graphing for containing different splicing laps splits graph layer and surveys
Structure is tried, electrical testing is carried out to this group of electrical testing structure, the resistance value of corresponding through-hole structure can be obtained, so as to true
Surely the zone of reasonableness of lap is spliced, such as according to technological requirement and electrical testing specification, to determine to splice the reasonable of lap
Scope, the zone of reasonableness of the splicing lap can instruct the fractionation situation in Dual graphing split process, make its foundation
It is more rational to split rule, so as to monitor the splice region that is formed in metal level Dual graphing split process to being attached thereto
The influence of through hole resistance.
Brief description of the drawings
Fig. 1 a show the schematic diagram that Dual graphing splices overlay region lap after splitting is zero
Fig. 1 b show that Dual graphing splices schematic diagram of the lap more than zero of overlay region after splitting
Fig. 2 shows the electrical testing structure various pieces schematic diagram of the preferred embodiment of the present invention
Fig. 3 shows showing for the electrical testing structure split without Dual graphing of the preferred embodiment of the present invention
It is intended to
Fig. 4 shows showing for the electrical testing structure split without Dual graphing of the preferred embodiment of the present invention
It is intended to
Fig. 5 a-5d show the dual of the splicing overlay region with different laps of the preferred embodiment of the present invention
The graphical schematic diagram for splitting graph layer
Fig. 6 shows the schematic flow sheet of the monitoring method of the through hole resistance of Dual graphing splice region
Embodiment
To make present disclosure more clear understandable, below in conjunction with Figure of description, present disclosure is made into one
Walk explanation.Certainly the invention is not limited in the specific embodiment, the general replacement known to those skilled in the art
Cover within the scope of the present invention.
Present invention utilizes the different splicing laps of Dual graphing splicing regions to have different shadows to through hole resistance
Loud principle, devise Dual graphing electrical testing structure and splice the monitoring of the through hole resistance of overlay region to Dual graphing
Method.
A kind of Dual graphing electrical testing structure of the present invention, it includes：Upper metal level, lower metal layer, and connection
In the through-hole structure of the upper and lower metal level；Through-hole structure is located at the overlapping region of upper metal level and lower metal layer.Upper metal level
And/or there is lower metal layer Dual graphing to split graph layer, Dual graphing, which splits graph layer, has splicing overlay region；Splicing
Overlay region is located in the overlapping region of upper metal level and lower metal layer, and is connected with the top of through-hole structure and/or bottom.
Dual graphing electrical testing structure is made below with reference to accompanying drawing 2- Fig. 5 d and a specific embodiment further detailed
Describe in detail bright.Wherein, Fig. 2 shows the electrical testing structure various pieces of the preferred embodiment of the present invention；Fig. 3 shows this
The schematic diagram of the electrical testing structure split without Dual graphing of one preferred embodiment of invention；Fig. 4 shows this hair
The schematic diagram of the electrical testing structure split without Dual graphing of a bright preferred embodiment；Fig. 5 a-5d show this
The Dual graphing of the splicing overlay region with different laps of one preferred embodiment of invention splits the signal of graph layer
Figure.It should be noted that accompanying drawing is using very simplified form, using non-accurately ratio, and only to it is convenient, clearly reach
To the purpose for aiding in illustrating the present embodiment.
Referring to Fig. 2, the Dual graphing electrical testing structure of the present embodiment includes：The upper metal level 1 of strip, strip
The lower metal layer 2 of shape, and it is connected to the square through hole structure 3 of upper and lower metal level 1,2；Through-hole structure 3 is located at upper metal level 1
With the overlapping region of lower metal layer 2.In the present embodiment, there is upper metal level 1 Dual graphing to split graph layer：First broken away view
Shape 11 and second splits figure 12, has splicing overlay region between the first and second fractionation graph layers 11,12；It splices overlay region
In the overlapping region of upper and lower metal level 1,2, and it is connected with the top of through-hole structure 3.Dual graphing splits graph layer
Splicing overlay region lap be more than or equal to zero.
Referring to Fig. 3, in the case where being split without Dual graphing, through-hole structure 3 and first split graph layer 11, under
Metal level 2 is connected, and the link position for being through-hole structure 3 does not splice overlay region；Referring to Fig. 4, torn open without Dual graphing
Point, through-hole structure 3 is connected with the second fractionation graph layer 12, lower metal layer 2, that is to say that the link position of through-hole structure 3 is not spelled
Connect overlay region；The resistance of through-hole structure can be as the through hole resistance value after Dual graphing in this two kinds of electrical testing structures
Normative reference.
Fig. 5 a-5d are referred to, the Dual graphing being connected in electrical testing structure with through-hole structure is show respectively and splits
The lap of the splicing overlay region of graph layer is more than zero situation for zero-sum, and in Fig. 5 a, the first fractionation graph layer 11 and second is torn open
The lap of the splicing overlay region of point graph layer 12 is zero, and this is situation most extreme in Dual graphing split process, through hole
Structure 3 is connected to the first fractionation graph layer 11 and second and splits the splicing overlay region of graph layer 12, and is located at upper metal level 1 with
The overlapping region of metal level 2；In Fig. 5 b, first splits splicing overlay region and the through hole that graph layer 11 and second splits graph layer 12
The top of structure 3 is connected, and the top of through-hole structure 3 is covered, and the splicing overlay region is identical with the shape at the top of through-hole structure 3, but
It is the area that the former area is more than the latter；In Fig. 5 c, first splits the splicing weight that graph layer 11 and second splits graph layer 12
The lap increase in folded area, the splicing overlay region are connected with through-hole structure 3, and by the covering of the top of through-hole structure 3 and beyond logical
The top area of pore structure 3；In Fig. 5 d, first splits the lap that graph layer 11 and second splits the splicing overlay region of graph layer 12
Further increase, the splicing overlay region are connected with through-hole structure 3, and by the covering of the top of through-hole structure 3 and beyond through-hole structure 3
Top area.
Electrical testing is carried out to the above-mentioned electrical testing structure shown, may further determine that the lap of splicing overlay region
Target zone, that is to say zone of reasonableness, for instructing fractionation situation in Dual graphing split process, it is established more
Rule is split to be rational, so as to monitor the splicing overlay region formed in metal level Dual graphing split process to being attached thereto
Through hole resistance influence.
In the present invention, the method that electrical testing is carried out using above-mentioned test structure is additionally provided, it includes：
Step 01：One group of difference lap is set, and the figure of upper metal level and/or lower metal layer carried out accordingly dual
It is graphical to split, obtain one group of electrical testing structure that there is Dual graphing to split graph layer；Wherein, this group of electrical testing knot
Dual graphing in structure splits the splicing overlay region that graph layer contains different laps；Splicing overlay region be located at upper metal level with
In the overlapping region of lower metal layer, and it is connected with the top of through-hole structure and/or bottom；
Step 02：Electrical testing is carried out to this group of electrical testing structure, obtains the through hole of corresponding electrical testing structure
The resistance value of structure；
Step 03：Electrical testing is carried out to the electrical testing structure split without Dual graphing, obtains corresponding lead to
The resistance value of pore structure；
Step 04：According to the resistance value in the resistance value and step 03 in step 02, the mesh of the lap of splice region is determined
Mark scope.
Prison below in conjunction with the specific embodiment of accompanying drawing 6 and one to the through hole resistance of the Dual graphing splicing regions of the present invention
Prosecutor method is described in further detail.
In the present embodiment, referring to Fig. 6, the monitoring method of the through hole resistance of Dual graphing splice region uses above-mentioned electricity
Learn test structure；It comprises the following steps：
Step 11：One group of difference lap is set, and Dual graphing fractionation is carried out to the figure of upper metal level accordingly, is obtained
The electrical testing structure that to one group there is Dual graphing to split graph layer；Dual graphing in this group of electrical testing structure is torn open
The splicing overlay region for dividing graph layer to contain different laps；Splicing overlay region is located at the overlapping region of upper metal level and lower metal layer
In, and with being connected at the top of through-hole structure；
Specifically, lap is more than or equal to zero, different laps can be preset；In the present embodiment, to upper
The figure of metal level carries out Dual graphing fractionation；Please continue to refer to Fig. 5 a-5d, upper metal level is strip, will be spliced overlapping
The lap in area is set to zero-sum and is more than zero a variety of situations, then the lap set according to this carries out Dual graphing fractionation.When
When splicing lap more than zero, the lap for splicing overlay region covers the top of through-hole structure, and including splicing overlay region
It is identical with the shape at the top of through-hole structure, but the former area is more than the area of the latter, is specifically equal to zero in lap
Or corresponding electrical testing structure may refer to foregoing description during more than zero, repeat no more here.
Step 02：Electrical testing is carried out to this group of electrical testing structure, obtains through hole in corresponding electrical testing structure
The resistance value of structure；Here it is possible to but it is not limited to carry out electrical testing using four end methods of testing.
Step 03：Electrical testing is carried out to the electrical testing structure split without Dual graphing, obtains corresponding lead to
The resistance value of pore structure；Here it is possible to but it is not limited to carry out electrical testing using four end methods of testing；Split without Dual graphing
Electrical testing structure can be repeated no more here with continued reference to Fig. 3 and Fig. 4.
Step 04：According to the resistance value in the resistance value and step 03 in step 02, it is determined that the lap of splicing overlay region
Target zone.
Specifically, the resistance value in above-mentioned steps 02 and 03, can be come with combined process requirement and electrical testing specification
It is determined that the target zone of the lap of splicing overlay region, that is to say zone of reasonableness, for instructing in Dual graphing split process
In fractionation situation, make it establishes it is more rational split it is regular, so as to monitor shape in metal level Dual graphing split process
Into splice region to the influence for the through hole resistance being attached thereto.
It should be noted that above-described embodiment has carried out Dual graphing fractionation to upper metal level, the present invention is not limited to
This, can also carry out Dual graphing fractionation to lower metal layer, can also carry out Dual graphing to upper and lower metal level simultaneously and tear open
Point；Electrical testing structure and monitoring method corresponding to it can refer to above-described embodiment, and the present invention repeats no more to this.
Dual graphing electrical testing structure of the invention and the prison for the through hole resistance for splicing overlay region to Dual graphing
Prosecutor method, by setting the through-hole structure of upper and lower metal level and the upper lower metal layer of connection, by upper metal level and/or lower metal
Layer carries out Dual graphing fractionation, obtains the electricity that one group of Dual graphing for containing different splicing laps splits graph layer and surveys
Structure is tried, electrical testing is carried out to this group of electrical testing structure, the resistance value of corresponding through-hole structure can be obtained, so as to true
Surely the zone of reasonableness of lap is spliced, such as according to technological requirement and electrical testing specification, to determine to splice the reasonable of lap
Scope, the zone of reasonableness of the splicing lap can instruct the fractionation situation in Dual graphing split process, make its foundation
It is more rational to split rule, so as to monitor the splice region that is formed in metal level Dual graphing split process to being attached thereto
The influence of through hole resistance.
Although the present invention is disclosed as above with preferred embodiment, the right embodiment illustrated only for the purposes of explanation and
, the present invention is not limited to, if those skilled in the art can make without departing from the spirit and scope of the present invention
Dry change and retouching, the protection domain that the present invention is advocated should be to be defined described in claims.
Claims (10)
- A kind of 1. Dual graphing electrical testing structure, it is characterised in that including：Upper metal level, lower metal layer, and be connected to The through-hole structure of the upper and lower metal level；The through-hole structure is located at the overlay region of the upper metal level and the lower metal layer Domain；Wherein,There is Dual graphing to split graph layer for the upper metal level and/or lower metal layer, and the Dual graphing splits figure Layer has splicing overlay region；The splicing overlay region is located in the overlapping region of the upper metal level and the lower metal layer, and It is connected with the top of the through-hole structure and/or bottom.
- 2. Dual graphing electrical testing structure according to claim 1, it is characterised in that the Dual graphing is split The lap of the splicing overlay region of graph layer is more than or equal to zero.
- 3. Dual graphing electrical testing structure according to claim 2, it is characterised in that the overlay region of splicing is by institute State top/or the bottom covering of through-hole structure.
- 4. Dual graphing electrical testing structure according to claim 3, it is characterised in that the splicing overlay region and institute State through-hole structure top and/or bottom shape it is identical.
- 5. Dual graphing electrical testing structure according to claim 1, it is characterised in that the upper metal level and/or The lower metal layer is strip.
- 6. a kind of monitoring method of the through hole resistance of Dual graphing splice region, it is characterised in that using described in claim 1 Electrical testing structure；The monitoring method comprises the following steps：Step 01：One group of difference lap is set, and the figure of the upper metal level and/or the lower metal layer carried out accordingly Dual graphing is split, and obtains one group of electrical testing structure that there is Dual graphing to split graph layer；Wherein, this group of electricity is surveyed Dual graphing in examination structure splits the splicing overlay region that graph layer contains different laps；The splicing overlay region is located at institute In the overlapping region for stating metal level and the lower metal layer, and it is connected with the top of the through-hole structure and/or bottom；Step 02：Electrical testing is carried out to this group of electrical testing structure, obtains through hole in the corresponding electrical testing structure The resistance value of structure；Step 03：Electrical testing is carried out to the electrical testing structure split without Dual graphing, obtains corresponding through hole knot The resistance value of structure；Wherein, the electrical testing structure split without Dual graphing includes：In the feelings split without Dual graphing Under condition, metal level, lower metal layer are connected on through-hole structure, and the link position for being through-hole structure does not splice overlay region；Step 04：The resistance value in resistance value and the step 03 in the step 02, determines the splicing overlay region Lap target zone.
- 7. monitoring method according to claim 6, it is characterised in that the weight of the splicing overlay region in the step 01 Folded amount is more than or equal to zero.
- 8. monitoring method according to claim 7, it is characterised in that the overlay region of splicing is by the top of the through-hole structure Portion and/or bottom covering.
- 9. monitoring method according to claim 8, it is characterised in that the splicing overlay region and the top of the through-hole structure The shape of portion and/or bottom is identical.
- 10. monitoring method according to claim 6, it is characterised in that used in the step 02 or in the step 03 Four end methods of testing carry out the electrical testing.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101109911A (en) * | 2006-07-21 | 2008-01-23 | 海力士半导体有限公司 | Pattern decomposition method for double exposure |
| CN103311102A (en) * | 2012-03-13 | 2013-09-18 | 格罗方德半导体公司 | Methods of making jogged layout routings double patterning compliant |
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| JP2008051583A (en) * | 2006-08-23 | 2008-03-06 | Kokusai Gijutsu Kaihatsu Co Ltd | Inspection device |
| US8361335B2 (en) * | 2009-06-08 | 2013-01-29 | GlobalFoundries, Inc. | Methods for fabricating semiconductor devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101109911A (en) * | 2006-07-21 | 2008-01-23 | 海力士半导体有限公司 | Pattern decomposition method for double exposure |
| CN103311102A (en) * | 2012-03-13 | 2013-09-18 | 格罗方德半导体公司 | Methods of making jogged layout routings double patterning compliant |
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